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Fixed semantic and marker tests. Now only dump needs to be adjusted
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stefandesouza committed Dec 3, 2023
1 parent 2c32ccf commit 93ae586
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Showing 20 changed files with 206 additions and 183 deletions.
2 changes: 1 addition & 1 deletion osaca/osaca.py
Original file line number Diff line number Diff line change
Expand Up @@ -333,7 +333,7 @@ def inspect(args, output_file=sys.stdout):
# Reduce to marked kernel or chosen section and add semantics
if args.lines:
line_range = get_line_range(args.lines)
kernel = [line for line in parsed_code if line["line_number"] in line_range]
kernel = [line for line in parsed_code if line.line_number in line_range]
print_length_warning = False
else:
kernel = reduce_to_section(parsed_code, isa)
Expand Down
3 changes: 3 additions & 0 deletions osaca/parser/condition.py
Original file line number Diff line number Diff line change
Expand Up @@ -20,3 +20,6 @@ def ccode(self):
@ccode.setter
def ccode(self, ccode):
self._ccode = ccode

def __str__(self):
return f"ConditionOperand(ccode={self._ccode}, source={self._source}, destination={self._destination})"
12 changes: 6 additions & 6 deletions osaca/parser/directive.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@


class DirectiveOperand(Operand):
def __init__(self, name_id=None, parameter_id=None, comment_id=None):
super().__init__(name_id)
def __init__(self, name=None, parameter_id=None, comment_id=None):
super().__init__(name)
self._parameter_id = parameter_id
self._comment_id = comment_id

Expand Down Expand Up @@ -36,16 +36,16 @@ def comment(self, comment):
def __eq__(self, other):
if isinstance(other, DirectiveOperand):
return (
self._name_id == other._name_id
self._name == other._name
and self._parameter_id == other._parameter_id
and self._comment_id == other._comment_id
)
elif isinstance(other, dict):
return self._name_id == other["name"] and self._parameter_id == other["parameters"]
return self._name == other["name"] and self._parameter_id == other["parameters"]
return False

def __str__(self):
return f"Directive(name_id={self._name_id}, parameters={self._parameter_id}, comment={self._comment_id})"
return f"Directive(name={self._name}, parameters={self._parameter_id}, comment={self._comment_id})"

def __repr__(self):
return f"DirectiveOperand(name_id={self._name_id}, parameters={self._parameter_id}, comment={self._comment_id})"
return f"DirectiveOperand(name={self._name}, parameters={self._parameter_id}, comment={self._comment_id})"
1 change: 0 additions & 1 deletion osaca/parser/instruction_form.py
Original file line number Diff line number Diff line change
Expand Up @@ -217,7 +217,6 @@ def __eq__(self, other):
if isinstance(other, instructionForm):
return (
self._instruction_id == other._instruction_id
and self._operands_id == other._operands_id
and self._directive_id == other._directive_id
and self._comment_id == other._comment_id
and self._label_id == other._label_id
Expand Down
8 changes: 4 additions & 4 deletions osaca/parser/label.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@


class LabelOperand(Operand):
def __init__(self, name_id=None, comment_id=None):
super().__init__(name_id)
def __init__(self, name=None, comment_id=None):
super().__init__(name)
self._comment_id = comment_id

@property
Expand All @@ -25,7 +25,7 @@ def __next__(self):
return self._comment_id.pop(0)

def __str__(self):
return f"LabelOperand(name_id={self._name_id}, comment={self._comment_id})"
return f"LabelOperand(name={self._name}, comment={self._comment_id})"

def __repr__(self):
return f"LabelOperand(name_id={self._name_id}, comment={self._comment_id})"
return f"LabelOperand(name={self._name}, comment={self._comment_id})"
4 changes: 2 additions & 2 deletions osaca/parser/memory.py
Original file line number Diff line number Diff line change
Expand Up @@ -127,7 +127,7 @@ def indexed_val(self, value):

def __str__(self):
return (
f"MemoryOperand(name_id={self._name_id}, offset_ID={self._offset_ID}, "
f"MemoryOperand(name={self._name}, offset_ID={self._offset_ID}, "
f"base_id={self._base_id}, index_id={self._index_id}, scale_id={self._scale_id}, "
f"segment_ext_id={self._segment_ext_id}, mask={self._mask}, "
f"pre_indexed={self._pre_indexed}, post_indexed={self._post_indexed}, "
Expand All @@ -137,7 +137,7 @@ def __str__(self):

def __repr__(self):
return (
f"MemoryOperand(name_id={self._name_id}, offset_ID={self._offset_ID}, "
f"MemoryOperand(name={self._name}, offset_ID={self._offset_ID}, "
f"base_id={self._base_id}, index_id={self._index_id}, scale_id={self._scale_id}, "
f"segment_ext_id={self._segment_ext_id}, mask={self._mask}, "
f"pre_indexed={self._pre_indexed}, post_indexed={self._post_indexed}, "
Expand Down
12 changes: 6 additions & 6 deletions osaca/parser/operand.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,14 +2,14 @@


class Operand:
def __init__(self, name_id, source=False, destination=False):
self._name_id = name_id
def __init__(self, name, source=False, destination=False):
self._name = name
self._source = source
self._destination = destination

@property
def name(self):
return self._name_id
return self._name

@property
def source(self):
Expand All @@ -21,7 +21,7 @@ def destination(self):

@name.setter
def name(self, name):
self._name_id = name
self._name = name

@source.setter
def source(self, source):
Expand All @@ -32,7 +32,7 @@ def destination(self, destination):
self._destination = destination

def __repr__(self):
return f"Operand(name_id={self._name_id},source={self._source},destination={self._destination})"
return f"Operand(name={self._name},source={self._source},destination={self._destination})"

def __str__(self):
return f"Name: {self._name_id}, Source: {self._source}, Destination: {self._destination}"
return f"Name: {self._name}, Source: {self._source}, Destination: {self._destination}"
26 changes: 19 additions & 7 deletions osaca/parser/parser_AArch64.py
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
from osaca.parser.register import RegisterOperand
from osaca.parser.identifier import IdentifierOperand
from osaca.parser.immediate import ImmediateOperand

from osaca.parser.condition import ConditionOperand

class ParserAArch64(BaseParser):

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_instance = None
Expand Down Expand Up @@ -302,7 +302,7 @@ def parse_line(self, line, line_number=None):
self.directive.parseString(line, parseAll=True).asDict()
)
instruction_form.directive = DirectiveOperand(
name_id=result.name, parameter_id=result.parameters
name=result.name, parameter_id=result.parameters
)
if result.comment is not None:
instruction_form.comment = " ".join(result.comment)
Expand Down Expand Up @@ -383,18 +383,20 @@ def process_operand(self, operand):
return self.process_register_operand(operand[self.REGISTER_ID])
if self.directive_id in operand:
return DirectiveOperand(
name_id=operand["directive"]["name"],
name=operand["directive"]["name"],
parameter_id=operand["directive"]["parameters"],
comment_id=operand["directive"]["comment"]
if "comment" in operand["directive"]
else None,
)
if "condition" in operand:
return self.process_condition(operand["condition"])
return operand

def process_register_operand(self, operand):
return RegisterOperand(
prefix_id=operand["prefix"],
name_id=operand["name"],
name=operand["name"],
shape=operand["shape"] if "shape" in operand else None,
lanes=operand["lanes"] if "lanes" in operand else None,
index=operand["index"] if "index" in operand else None,
Expand Down Expand Up @@ -425,7 +427,7 @@ def process_memory_address(self, memory_address):
scale = 2 ** int(memory_address["index"]["shift"][0]["value"])
new_dict = MemoryOperand(
offset_ID=offset,
base_id=RegisterOperand(name_id=base["name"], prefix_id=base["prefix"]),
base_id=RegisterOperand(name=base["name"], prefix_id=base["prefix"]),
index_id=index,
scale_id=scale,
)
Expand All @@ -441,9 +443,12 @@ def process_memory_address(self, memory_address):
def process_sp_register(self, register):
"""Post-process stack pointer register"""
# reg = register
new_reg = RegisterOperand(prefix_id="x", name_id="sp")
new_reg = RegisterOperand(prefix_id="x", name="sp")
# reg["prefix"] = "x"
return new_reg

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def process_condition(self, condition):
return ConditionOperand(ccode=condition.lower())

def resolve_range_list(self, operand):
"""
Expand Down Expand Up @@ -536,7 +541,7 @@ def process_label(self, label):
# remove duplicated 'name' level due to identifier
# label["name"] = label["name"]["name"]
new_label = LabelOperand(
name_id=label["name"]["name"],
name=label["name"]["name"],
comment_id=label["comment"] if self.comment_id in label else None,
)
return new_label
Expand Down Expand Up @@ -602,12 +607,19 @@ def is_flag_dependend_of(self, flag_a, flag_b):
"""Check if ``flag_a`` is dependent on ``flag_b``"""
# we assume flags are independent of each other, e.g., CF can be read while ZF gets written
# TODO validate this assumption
if isinstance(flag_a, Operand):
return (flag_a.name == flag_b["name"])
else:
return (flag_a["name"] == flag_b["name"])

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if flag_a.name == flag_b["name"]:
return True
return False

def is_reg_dependend_of(self, reg_a, reg_b):
"""Check if ``reg_a`` is dependent on ``reg_b``"""
if not isinstance(reg_a, Operand):
reg_a = RegisterOperand(name=reg_a["name"])
prefixes_gpr = "wx"
prefixes_vec = "bhsdqvz"
if reg_a.name == reg_b.name:
Expand Down
16 changes: 10 additions & 6 deletions osaca/parser/parser_x86att.py
Original file line number Diff line number Diff line change
Expand Up @@ -234,7 +234,7 @@ def parse_line(self, line, line_number=None):
self.directive.parseString(line, parseAll=True).asDict()
)
instruction_form.directive = DirectiveOperand(
name_id=result.name,
name=result.name,
parameter_id=result.parameters,
)

Expand Down Expand Up @@ -303,7 +303,7 @@ def process_operand(self, operand):
prefix_id=operand["register"]["prefix"]
if "prefix" in operand["register"]
else None,
name_id=operand["register"]["name"],
name=operand["register"]["name"],
shape=operand["register"]["shape"] if "shape" in operand["register"] else None,
lanes=operand["register"]["lanes"] if "lanes" in operand["register"] else None,
index=operand["register"]["index"] if "index" in operand["register"] else None,
Expand All @@ -316,7 +316,7 @@ def process_operand(self, operand):
return operand

def process_directive(self, directive):
directive_new = DirectiveOperand(name_id=directive["name"], parameter_id=[])
directive_new = DirectiveOperand(name=directive["name"], parameter_id=[])
if "parameters" in directive:
directive_new.parameters = directive["parameters"]
if "comment" in directive:
Expand All @@ -341,11 +341,11 @@ def process_memory_address(self, memory_address):
offset = ImmediateOperand(value_id=int(offset["value"], 0))
if base != None:

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Comparison to None should be 'if cond is not None:' (E711)
baseOp = RegisterOperand(
name_id=base["name"], prefix_id=base["prefix"] if "prefix" in base else None
name=base["name"], prefix_id=base["prefix"] if "prefix" in base else None
)
if index != None:

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Comparison to None should be 'if cond is not None:' (E711)
indexOp = RegisterOperand(
name_id=index["name"], prefix_id=index["prefix"] if "prefix" in index else None
name=index["name"], prefix_id=index["prefix"] if "prefix" in index else None
)
if isinstance(offset, dict) and "identifier" in offset:
offset = IdentifierOperand(name=offset["identifier"]["name"])
Expand All @@ -362,7 +362,7 @@ def process_label(self, label):
# remove duplicated 'name' level due to identifier
label["name"] = label["name"][0]["name"]
new_label = LabelOperand(
name_id=label["name"], comment_id=label["comment"] if "comment" in label else None
name=label["name"], comment_id=label["comment"] if "comment" in label else None
)
return new_label

Expand Down Expand Up @@ -398,6 +398,10 @@ def is_flag_dependend_of(self, flag_a, flag_b):
"""Check if ``flag_a`` is dependent on ``flag_b``"""
# we assume flags are independent of each other, e.g., CF can be read while ZF gets written
# TODO validate this assumption
if isinstance(flag_b, Operand):
return (flag_a.name == flag_b.name)
else:
return (flag_a.name == flag_b["name"])
if flag_a.name == flag_b.name:
return True
return False
Expand Down
8 changes: 4 additions & 4 deletions osaca/parser/register.py
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
class RegisterOperand(Operand):
def __init__(
self,
name_id=None,
name=None,
width_id=None,
prefix_id=None,
reg_id=None,
Expand All @@ -22,7 +22,7 @@ def __init__(
pre_indexed=False,
post_indexed=False,
):
super().__init__(name_id, source, destination)
super().__init__(name, source, destination)
self._width_id = width_id
self._prefix_id = prefix_id
self._reg_id = reg_id
Expand Down Expand Up @@ -134,7 +134,7 @@ def zeroing(self, zeroing):

def __str__(self):
return (
f"RegisterOperand(name_id={self._name_id}, width_id={self._width_id}, "
f"RegisterOperand(name={self._name}, width_id={self._width_id}, "
f"prefix_id={self._prefix_id}, reg_id={self._reg_id}, REGtype_id={self._regtype_id}, "
f"lanes={self._lanes}, shape={self._shape}, index={self._index}, "
f"mask={self._mask}, zeroing={self._zeroing},source={self._source},destination={self._destination},"
Expand All @@ -148,7 +148,7 @@ def __repr__(self):
def __eq__(self, other):

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if isinstance(other, RegisterOperand):
return (
self._name_id == other._name_id
self._name == other._name
and self._width_id == other._width_id
and self._prefix_id == other._prefix_id
and self._reg_id == other._reg_id
Expand Down
10 changes: 5 additions & 5 deletions osaca/semantics/arch_semantics.py
Original file line number Diff line number Diff line change
Expand Up @@ -261,7 +261,7 @@ def assign_tp_lt(self, instruction_form):
]
)
# dummy_reg = {"class": "register", "name": reg_type}
dummy_reg = RegisterOperand(name_id=reg_type)
dummy_reg = RegisterOperand(name=reg_type)
data_port_pressure = [0.0 for _ in range(port_number)]
data_port_uops = []
if INSTR_flags.HAS_LD in instruction_form.flags:
Expand All @@ -280,7 +280,7 @@ def assign_tp_lt(self, instruction_form):
for ldp in load_perf_data
if ldp.dst != None

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and self._machine_model._check_operands(
dummy_reg, RegisterOperand(name_id=ldp.dst)
dummy_reg, RegisterOperand(name=ldp.dst)
)
]
if len(data_port_uops) < 1:
Expand Down Expand Up @@ -442,11 +442,11 @@ def convert_op_to_reg(self, reg_type, reg_id="0"):
"""Create register operand for a memory addressing operand"""
if self._isa == "x86":
if reg_type == "gpr":
register = RegisterOperand(name_id="r" + str(int(reg_id) + 9))
register = RegisterOperand(name="r" + str(int(reg_id) + 9))
else:
register = RegisterOperand(name_id=reg_type + reg_id)
register = RegisterOperand(name=reg_type + reg_id)
elif self._isa == "aarch64":
register = RegisterOperand(name_id=reg_id, prefix_id=reg_type)
register = RegisterOperand(name=reg_id, prefix_id=reg_type)
return register

def _nullify_data_ports(self, port_pressure):
Expand Down
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