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MISched: Don't schedule regions with 0 instructions
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I think this is correct, but may not necessarily be the correct fix
for the assertion I'm really trying to solve. If a scheduling region
was found that only has dbg_value instructions, the RegPressure
tracker would end up in an inconsistent state because it would skip
over any debug instructions and point to an instruction outside of the
scheduling region. It may still be possible for this to happen if
there are some real schedulable instructions between dbg_values, but I
haven't managed to break this.

The testcase is extremely sensitive and I'm not sure how to make it
more resistent to future scheduler changes that would avoid stressing
this situation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356926 91177308-0d34-0410-b5e6-96231b3b80d8
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@arsenm
arsenm committed Mar 25, 2019
1 parent 08e5a72 commit 58dc6ce
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Showing 2 changed files with 121 additions and 2 deletions.
8 changes: 6 additions & 2 deletions lib/CodeGen/MachineScheduler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -486,13 +486,17 @@ getSchedRegions(MachineBasicBlock *MBB,
MachineInstr &MI = *std::prev(I);
if (isSchedBoundary(&MI, &*MBB, MF, TII))
break;
if (!MI.isDebugInstr())
if (!MI.isDebugInstr()) {
// MBB::size() uses instr_iterator to count. Here we need a bundle to
// count as a single instruction.
++NumRegionInstrs;
}
}

Regions.push_back(SchedRegion(I, RegionEnd, NumRegionInstrs));
// It's possible we found a scheduling region that only has debug
// instructions. Don't bother scheduling these.
if (NumRegionInstrs != 0)
Regions.push_back(SchedRegion(I, RegionEnd, NumRegionInstrs));
}

if (RegionsTopDown)
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115 changes: 115 additions & 0 deletions test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,115 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=machine-scheduler -verify-machineinstrs %s -o - | FileCheck %s

# The sequence of DBG_VALUEs forms a scheduling region with 0 real
# instructions. The RegPressure tracker would end up skipping over any
# debug instructions, so it would point to the instruction
# before/outside of the region, hitting this assert:
# assert((BotRPTracker.getPos() == RegionEnd ||
# (RegionEnd->isDebugInstr() &&
# BotRPTracker.getPos() == priorNonDebug(RegionEnd, RegionBegin))) &&
# "Can't find the region bottom");

---
name: only_dbg_value_sched_region
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
waveLimiter: true
body: |
; CHECK-LABEL: name: only_dbg_value_sched_region
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64 = GLOBAL_LOAD_DWORDX2 [[DEF]], 0, 0, 0, implicit $exec
; CHECK: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF]], 8, 0, 0, implicit $exec
; CHECK: undef %4.sub1:vreg_64 = V_ADD_U32_e32 [[COPY]], [[COPY]], implicit $exec
; CHECK: %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
; CHECK: [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: undef %11.sub1:vreg_64 = IMPLICIT_DEF
; CHECK: [[DEF4:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[DEF5:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK: [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; CHECK: [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; CHECK: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[GLOBAL_LOAD_DWORDX2_]]
; CHECK: undef %6.sub0:vreg_64 = V_ADD_F32_e32 [[DEF]].sub0, [[COPY1]].sub0, implicit $exec
; CHECK: dead undef %6.sub1:vreg_64 = V_ADD_F32_e32 [[DEF]].sub1, [[COPY1]].sub0, implicit $exec
; CHECK: [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY1]], 0, 0, 0, implicit $exec
; CHECK: [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; CHECK: undef %19.sub0:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD1]], [[GLOBAL_LOAD_DWORDX2_]].sub0, implicit $exec
; CHECK: %19.sub1:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD]], [[GLOBAL_LOAD_DWORD]], implicit $exec
; CHECK: GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, implicit $exec
; CHECK: %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF1]], 0, 0, 0, implicit $exec
; CHECK: [[DEF2]].sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF3]], 0, 0, 0, implicit $exec
; CHECK: dead %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, implicit $exec
; CHECK: dead %21:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF4]], 0, 0, 0, implicit $exec
; CHECK: [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 2, [[DEF2]], implicit $exec
; CHECK: dead %22:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF5]], 0, 0, 0, implicit $exec
; CHECK: S_NOP 0, implicit [[DEF7]], implicit [[V_LSHLREV_B64_]].sub0, implicit [[DEF6]], implicit [[V_MOV_B32_e32_]]
; CHECK: GLOBAL_STORE_DWORD [[DEF5]], [[V_MOV_B32_e32_1]], 0, 0, 0, implicit $exec
; CHECK: bb.1:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: S_SETREG_IMM32_B32 0, 1
; CHECK: DBG_VALUE
; CHECK: DBG_VALUE
; CHECK: DBG_VALUE
; CHECK: S_SETREG_IMM32_B32 0, 1
; CHECK: bb.2:
; CHECK: S_NOP 0, implicit [[COPY]]
; CHECK: S_NOP 0, implicit [[DEF8]]
; CHECK: S_ENDPGM 0
bb.0:
liveins: $vgpr0
%0:vgpr_32 = COPY $vgpr0
%1:vreg_64 = IMPLICIT_DEF
%2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1, 0, 0, 0, implicit $exec
%3:vgpr_32 = GLOBAL_LOAD_DWORD %1, 8, 0, 0, implicit $exec
undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0, %0, implicit $exec
%4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
%5:vreg_64 = COPY %2
undef %6.sub0:vreg_64 = V_ADD_F32_e32 %1.sub0, %5.sub0, implicit $exec
%6.sub1:vreg_64 = V_ADD_F32_e32 %1.sub1, %5.sub0, implicit $exec
%7:vgpr_32 = GLOBAL_LOAD_DWORD %5, 0, 0, 0, implicit $exec
%8:vreg_64 = IMPLICIT_DEF
%9:vreg_64 = IMPLICIT_DEF
%10:vreg_64 = IMPLICIT_DEF
undef %11.sub1:vreg_64 = IMPLICIT_DEF
%12:vgpr_32 = IMPLICIT_DEF
%13:vgpr_32 = IMPLICIT_DEF
%14:vreg_64 = IMPLICIT_DEF
%15:vreg_64 = IMPLICIT_DEF
%16:vgpr_32 = IMPLICIT_DEF
%17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
%18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
undef %19.sub0:vreg_64 = V_ADD_F32_e32 %7, %2.sub0, implicit $exec
%19.sub1:vreg_64 = V_ADD_F32_e32 %3, %3, implicit $exec
GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, implicit $exec
%11.sub0:vreg_64 = GLOBAL_LOAD_DWORD %9, 0, 0, 0, implicit $exec
%8.sub0:vreg_64 = GLOBAL_LOAD_DWORD %10, 0, 0, 0, implicit $exec
%20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, implicit $exec
%21:vgpr_32 = GLOBAL_LOAD_DWORD %14, 0, 0, 0, implicit $exec
%22:vgpr_32 = GLOBAL_LOAD_DWORD %15, 0, 0, 0, implicit $exec
%23:vreg_64 = V_LSHLREV_B64 2, %8, implicit $exec
S_NOP 0, implicit %13, implicit %23.sub0, implicit %12, implicit %17
GLOBAL_STORE_DWORD %15, %18, 0, 0, 0, implicit $exec
bb.1:
S_SETREG_IMM32_B32 0, 1
DBG_VALUE
DBG_VALUE
DBG_VALUE
S_SETREG_IMM32_B32 0, 1
bb.2:
S_NOP 0, implicit %0
S_NOP 0, implicit %16
S_ENDPGM 0
...

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