Add OpenLane Support

.coveragerc

@@ -0,0 +1,3 @@
+[run]
+branch = True
+include = veriloggen/**/*.py

conftest.py

@@ -1,8 +1,23 @@
-from __future__ import absolute_import
-from __future__ import print_function
-
 import pytest
+from pathlib import Path
 
 
 def pytest_addoption(parser):
     parser.addoption('--sim', default='iverilog', help='Simulator')
+
+
+@pytest.fixture(scope='session', autouse=True)
+def clean():
+    yield
+    for p in Path('.').glob('*.out'):
+        p.unlink()
+    for p in Path('.').glob('*.vcd'):
+        p.unlink()
+    for p in Path('.').glob('**/*.pyc'):
+        p.unlink()
+    for p in Path('.').glob('**/__pycache__'):
+        p.rmdir()
+    for p in Path('.').glob('**/parser.out'):
+        p.unlink()
+    for p in Path('.').glob('**/parsetab.py'):
+        p.unlink()

pytest.ini

@@ -1,2 +1,3 @@
 [pytest]
-python_paths = ./
+pythonpath = .
+testpaths = examples tests

setup.py

@@ -23,9 +23,10 @@ def read(filename):
                     'veriloggen.simulation': ['*.cpp'],
                     },
       install_requires=['pyverilog>=1.3.0',
-                        'numpy>=1.17'],
+                        'numpy>=1.17',
+                        'rectpack>=0.2.2'],
       extras_require={
-          'test': ['pytest>=3.8.1', 'pytest-pythonpath>=0.7.3'],
+          'test': ['pytest>=7.0.0'],
           'graph': ['pygraphviz>=1.3.1'],
       },
       )

tests/extension/asic_/check/correct.json

@@ -0,0 +1,14 @@
+{
+    "DESIGN_NAME": "spm",
+    "VERILOG_FILES": "dir::src/*.v",
+    "CLOCK_PORT": "clk",
+    "CLOCK_PERIOD": 100,
+    "pdk::sky130A": {
+        "SYNTH_MAX_FANOUT": 6,
+        "FP_CORE_UTIL": 40,
+        "PL_TARGET_DENSITY": "expr::($FP_CORE_UTIL + 5.0) / 100.0",
+        "scl::sky130_fd_sc_hd": {
+            "CLOCK_PERIOD": 15
+        }
+    }
+}

tests/extension/asic_/check/test_asic_check.py

@@ -0,0 +1,18 @@
+from pathlib import Path
+import pytest
+
+from veriloggen.asic import check_file
+
+
+files = ['correct.json', 'wrong1.json', 'wrong2.json']
+
+
+@pytest.mark.parametrize('fname', files)
+def test(fname: str):
+    p = Path(__file__).parent / fname
+    try:
+        check_file(p)
+    except (TypeError, ValueError):
+        assert fname.startswith('wrong')
+    else:
+        assert fname.startswith('correct')

tests/extension/asic_/check/wrong1.json

@@ -0,0 +1,14 @@
+{
+    "DESIGN_NAME": "spm",
+    "VERILOG_FILE": "dir::src/*.v",
+    "CLOCK_PORT": "clk",
+    "CLOCK_PERIOD": 100,
+    "pdk::sky130A": {
+        "SYNTH_MAX_FANOUT": 6,
+        "FP_CORE_UTIL": 40,
+        "PL_TARGET_DENSITY": "expr::($FP_CORE_UTIL + 5.0) / 100.0",
+        "scl::sky130_fd_sc_hd": {
+            "CLOCK_PERIOD": 15
+        }
+    }
+}

tests/extension/asic_/check/wrong2.json

@@ -0,0 +1,12 @@
+{
+    "DESIGN_NAME": "spm",
+    "VERILOG_FILES": "dir::src/*.v",
+    "CLOCK_PORT": "clk",
+    "CLOCK_PERIOD": 100,
+    "pdk::sky130A": {
+        "SYNTH_MAX_FANOUT": 6,
+        "FP_CORE_UTIL": 40,
+        "PL_TARGET_DENSITY": "expr::($FP_CORE_UTIL + 5.0) / 100.0",
+        "scl::sky130_fd_sc_hd": "dummy"
+    }
+}

tests/extension/asic_/conftest.py

@@ -0,0 +1,25 @@
+from __future__ import annotations
+
+from typing import TYPE_CHECKING
+if TYPE_CHECKING:
+    from typing import Literal
+
+import subprocess
+from pathlib import Path
+
+import pytest
+
+
+@pytest.fixture(scope='session')
+def simulation_model_path():
+    subprocess.run('git clone https://github.com/VLSIDA/sky130_sram_macros.git',
+                   shell=True, check=True)
+    subprocess.run('git clone https://github.com/google/globalfoundries-pdk-ip-gf180mcu_fd_ip_sram.git',
+                   shell=True, check=True)
+    path_dict: dict[Literal['sky130', 'gf180mcu'], list[str]] = {}
+    path_dict['sky130'] = [str(p.absolute()) for p in Path('sky130_sram_macros').iterdir() if p.is_dir()]
+    path_dict['gf180mcu'] = [str(p.absolute()) for p in Path('globalfoundries-pdk-ip-gf180mcu_fd_ip_sram/cells').iterdir()]
+    yield path_dict
+    subprocess.run('rm -rf sky130_sram_macros', shell=True, check=True)
+    subprocess.run('rm -rf globalfoundries-pdk-ip-gf180mcu_fd_ip_sram',
+                   shell=True, check=True)

tests/extension/asic_/matmul_thread/asic_matmul_thread.py

@@ -0,0 +1,244 @@
+from __future__ import annotations
+
+from typing import TYPE_CHECKING
+if TYPE_CHECKING:
+    from typing import Literal
+
+
+# --- to run without installation ---
+
+import sys
+import os
+
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+# --- to run without installation ---
+
+
+import numpy as np
+
+from veriloggen import *
+from veriloggen.asic import ASICSRAM, make_arr, asic_sim, generate_configs
+from veriloggen import thread as vthread
+from veriloggen.thread.uart import UartRx, UartTx
+
+
+rand_seed = 123
+rand_range = (-16, 16)
+
+
+def make_uut(
+    pdk: Literal['sky130', 'gf180mcu'],
+    matrix_size: int,
+    baudrate: int,
+    clockfreq: int,
+) -> Module:
+    m = Module('asic_matmul_thread')
+    clk = m.Input('clk')
+    rst = m.Input('rst')
+    rxd = m.Input('rxd')
+    txd = m.Output('txd')
+
+    uart_rx = UartRx(m, 'uart_rx', 'rx_', clk, rst, rxd,
+                     baudrate=baudrate, clockfreq=clockfreq)
+    uart_tx = UartTx(m, 'uart_tx', 'tx_', clk, rst, txd,
+                     baudrate=baudrate, clockfreq=clockfreq)
+
+    addrwidth = (matrix_size*matrix_size - 1).bit_length()
+    ram_a = ASICSRAM(m, 'ram_a', clk, rst, 32, addrwidth, pdk=pdk)
+    ram_b = ASICSRAM(m, 'ram_b', clk, rst, 32, addrwidth, pdk=pdk)
+
+    def comp():
+        while True:
+            data = 0  # only to avoid undefined variable error
+
+            # receive matrix A
+            for idx in range(matrix_size * matrix_size):
+                # big endian
+                data[24:32] = uart_rx.recv()
+                data[16:24] = uart_rx.recv()
+                data[8:16] = uart_rx.recv()
+                data[0:8] = uart_rx.recv()
+                ram_a.write(idx, data)
+
+            # receive matrix B
+            for idx in range(matrix_size * matrix_size):
+                # big endian
+                data[24:32] = uart_rx.recv()
+                data[16:24] = uart_rx.recv()
+                data[8:16] = uart_rx.recv()
+                data[0:8] = uart_rx.recv()
+                ram_b.write(idx, data)
+
+            # multiply matrix A and B, transmitting matrix C
+            a_idx = 0
+            for i in range(matrix_size):
+                b_idx = 0
+                for j in range(matrix_size):
+                    # calculate inner product
+                    w = 0
+                    for k in range(matrix_size):
+                        x = ram_a.read(a_idx + k)
+                        y = ram_b.read(b_idx + k)
+                        z = x * y
+                        w += z
+
+                    # transmit matrix C
+                    # big endian
+                    uart_tx.send(w[24:32])
+                    uart_tx.send(w[16:24])
+                    uart_tx.send(w[8:16])
+                    uart_tx.send(w[0:8])
+
+                    b_idx += matrix_size
+                a_idx += matrix_size
+
+    thd = vthread.Thread(m, 'thd', clk, rst, comp, datawidth=32)
+    thd.start()
+
+    return m
+
+
+def make_tb(
+    pdk: Literal['sky130', 'gf180mcu'],
+    matrix_size: int,
+    baudrate: int,
+    clockfreq: int,
+):
+    m = Module('tb')
+
+    uut = Submodule(m, make_uut(pdk, matrix_size, baudrate, clockfreq),
+                    'uut', as_wire=('rxd', 'txd'))
+    clk = uut['clk']
+    rst = uut['rst']
+    rxd = uut['rxd']
+    txd = uut['txd']
+
+    uart_rx = UartRx(m, 'uart_rx', 'rx_', clk, rst, txd,
+                     baudrate=baudrate, clockfreq=clockfreq)
+    uart_tx = UartTx(m, 'uart_tx', 'tx_', clk, rst, rxd,
+                     baudrate=baudrate, clockfreq=clockfreq)
+
+    clockperiod = 1_000_000_000 / clockfreq  # in nanoseconds
+    simulation.setup_clock(m, clk, hperiod=clockperiod / 2)
+    init = simulation.setup_reset(m, rst, m.make_reset(),
+                                  period=clockperiod * 10)
+
+    init.add(
+        Delay(100_000_000_000),
+        Finish()
+    )
+
+    rng = np.random.default_rng(rand_seed)
+    mat_a = rng.integers(*rand_range, (matrix_size, matrix_size), endpoint=True)
+    mat_b = rng.integers(*rand_range, (matrix_size, matrix_size), endpoint=True)
+    mat_c = mat_a @ mat_b
+
+    a = make_arr(m, 'a', mat_a.ravel())
+    b = make_arr(m, 'b', mat_b.T.ravel())
+    c = make_arr(m, 'c', mat_c.ravel())
+
+    def test():
+        ok = True
+
+        # transmit matrix A
+        for i in range(matrix_size * matrix_size):
+            data = a[i]
+            uart_tx.send(data[24:32])
+            uart_tx.send(data[16:24])
+            uart_tx.send(data[8:16])
+            uart_tx.send(data[0:8])
+
+        # transmit matrix B
+        for i in range(matrix_size * matrix_size):
+            data = b[i]
+            uart_tx.send(data[24:32])
+            uart_tx.send(data[16:24])
+            uart_tx.send(data[8:16])
+            uart_tx.send(data[0:8])
+
+        # receive matrix C and check it
+        for i in range(matrix_size * matrix_size):
+            data[24:32] = uart_rx.recv()
+            data[16:24] = uart_rx.recv()
+            data[8:16] = uart_rx.recv()
+            data[0:8] = uart_rx.recv()
+            if data != c[i]:
+                ok = False
+
+        if ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+        vthread.finish()
+
+    thd = vthread.Thread(m, 'thd', clk, rst, test, datawidth=32)
+    thd.start()
+
+    return m
+
+
+def run(
+    pdk: Literal['sky130', 'gf180mcu'],
+    simulation_model_path: list[str],
+    matrix_size: int,
+    baudrate: int,
+    clockfreq: int,
+) -> str:
+    """
+    Simulate.
+    Used for testing (through `pytest`).
+    """
+    tb = make_tb(pdk, matrix_size, baudrate, clockfreq)
+    rslt = asic_sim(tb, macro_model_path=simulation_model_path)
+    return rslt
+
+
+def sim(
+    pdk: Literal['sky130', 'gf180mcu'],
+    pdk_root: str,
+    matrix_size: int,
+    baudrate: int,
+    clockfreq: int,
+) -> str:
+    """
+    Simulate.
+    Used for standalone execution (`if __name__ == '__main__':`).
+    """
+    tb = make_tb(pdk, matrix_size, baudrate, clockfreq)
+    rslt = asic_sim(tb, pdk, pdk_root)
+    return rslt
+
+
+def syn(
+    pdk: Literal['sky130', 'gf180mcu'],
+    pdk_root: str,
+    matrix_size: int,
+    baudrate: int,
+    clockfreq: int,
+    die_shape: tuple[int | float, int | float],
+):
+    """
+    Generate an HDL file and configuration files.
+    Used for standalone execution (`if __name__ == '__main__':`).
+    """
+    clockperiod = 1_000_000_000 / clockfreq
+    uut = make_uut(pdk, matrix_size, baudrate, clockfreq)
+    uut.to_verilog('asic_matmul_thread.v')
+    generate_configs('asic_matmul_thread.v', 'asic_matmul_thread', 'clk',
+                     clockperiod, die_shape, pdk, pdk_root)
+
+
+if __name__ == '__main__':
+    pdk = 'sky130'  # sky130 or gf180mcu
+    pdk_root = '/Users/mu/research/google/OpenLane/pdks'  # change this path
+    matrix_size = 15
+    baudrate = 2_000_000
+    clockfreq = 20_000_000
+    die_shape = (1000, 1000)
+
+    syn(pdk, pdk_root, matrix_size, baudrate, clockfreq, die_shape)
+    rslt = sim(pdk, pdk_root, matrix_size, baudrate, clockfreq)
+    print(rslt)