Top: add support for fixed ram latency

OpenXiangShan · Sep 15, 2023 · d7c2b43 · d7c2b43
1 parent 1f9dbb5
commit d7c2b43
Showing 1 changed file with 9 additions and 1 deletion.
diff --git a/src/main/scala/top/Top.scala b/src/main/scala/top/Top.scala
@@ -160,12 +160,20 @@ trait HaveAXI4MemPort {
 
   val mem_xbar = TLXbar()
   mem_xbar :=* TLBuffer() :=* TLCacheCork() :=* bankedNode
+
+  val ram_latency = 0
+  val buffers = Seq.fill(ram_latency)(TLBuffer())
+  val delayer = buffers.foldLeft(mem_xbar){ case (up, down) =>
+    down := up
+    down
+  }
+
   memAXI4SlaveNode :=
     AXI4UserYanker() :=
     AXI4Deinterleaver(L3BlockSize) :=
     TLToAXI4() :=
     TLWidthWidget(L3BusWidth / 8) :=
-    mem_xbar
+    delayer
 
   val memory = InModuleBody {
     memAXI4SlaveNode.makeIOs()