NYCU Digital Circuit System (2023) - writeup

This repository contained my designs (System Verilog) and patterns (System Verilog & Python3) is used to practice the homeworks and labs from Prof. Tien-Hsuan Chang's Digital Circuit System (DCS) course (2023) at NYCU.

Outline

Homeworks

HW#	Topic	Design	Custom Pattern (Generated by Python3)	Area
HW01	Simplified Mahjong Judgment	SMJ.sv	✅	6180.451257
HW02	Simplified I2C	I2S.sv		4081.49287
HW03	Traffic Light Controller
HW04	Histogram Equalizer
HW05	MIPS CPU

Labs

Lab#	Topic	Design	Custom Pattern (Generated by Python3)	Area
Lab01	Binary-Coded Decimal	BCD.sv	✅	1114.344017
Lab02	Merge Sort	Sort.sv	✅	4420.785636
Lab03	Frequency Divider	Counter.sv	✅	172.972801
Lab04	Sequential Circuit	Seq.sv	✅	1237.420825
Lab05	AHB Interconnect	inter.sv	✅	3073.593637
Lab06	Pattern	pattern.sv	❌	none
Lab07	Matrix Multiplication	DCT.sv	✅	88485.5678
Lab08	Floating Point Computation	Fpc.sv	✅	14972.12673
Lab09	Pipeline	P_MUL.sv	✅	295543.9876
Lab10	Clock Domain Crossing	CDC.sv	✅	3502.699259

Online Test

Topic	Design	Custom Pattern (Generated by Python3)	Area
Systolic Array

Final Project

Topic	Design	Custom Pattern (Generated by Python3)	Area
Simple CNN

Design Flow

%%{
  init: {
    'theme': 'neutral',
    'themeVariables': {
      'textColor': '#000000',
      'noteTextColor' : '#000000',
      'fontSize': '20px'
    }
  }
}%%

flowchart LR
    b0[                  ] --- b2[ ] --- b4[ ] --- DesignFlow --- b1[ ] --- b3[ ] --- b5[                  ]
    style b0 stroke-width:0px, fill: #FFFFFF00, color:#FFFFFF00
    style b1 stroke-width:0px, fill: #FFFFFF00
    style b2 stroke-width:0px, fill: #FFFFFF00
    style b3 stroke-width:0px, fill: #FFFFFF00
    style b4 stroke-width:0px, fill: #FFFFFF00
    style b5 stroke-width:0px, fill: #FFFFFF00, color:#FFFFFF00

    linkStyle 0 stroke-width:0px
    linkStyle 1 stroke-width:0px
    linkStyle 2 stroke-width:0px
    linkStyle 3 stroke-width:0px
    linkStyle 4 stroke-width:0px
    linkStyle 5 stroke-width:0px
    
    subgraph DesignFlow
    direction TB
    style DesignFlow fill:#ffffff00, stroke-width:0px

    direction TB
        A[Spec Development System models]
        A --> B[RTL and Verification]
        B --> C[Synthesis]
        C --> D[Timing Verificaiton]
        D --> E[Gate Level Simulation]
        E --> F[Finish]
        style A fill:#74c2b5,stroke:#000000,stroke-width:4px
        style B fill:#f8cecc,stroke:#000000,stroke-width:4px
        style C fill:#fff2cc,stroke:#000000,stroke-width:4px
        style D fill:#cce5ff,stroke:#000000,stroke-width:4px
        style E fill:#fa6800,stroke:#000000,stroke-width:4px
        style F fill:#ff6666,stroke:#000000,stroke-width:4px
    end

Loading

Usage

# RTL & Verification
$ make irun_rtl

# Install Python3 thirdparty library (Optional)
$ pip3 install -r requirements.txt

# Use Python3 to generate custom testcase (Optional)
$ python3 testdata_gen.py

# RTL & Verification with custom testcase
$ make irun_rtl_cust

# Synthesis & STA report
$ make syn

# Gate level simulation
$ make irun_gate

# Gate level simulation with custom testcase
$ make irun_gate_cust

# View waveform
$ make nWave

# Debug design and check critical path
$ make verdi_rtl
$ make verdi_gate

# Clean output file
$ make clean

Tool Chain

• Python3
• Cadence irun
• Synopsys VCS
• Synopsys Design Compiler
• Synopsys Verdi
• Process : UMC 0.18µm (Not provide in this repository)