Fix the generation of mem with 1 bit of write mask

Minres · Jan 13, 2025 · 2977ef3 · 2977ef3
1 parent 2c93394
commit 2977ef3
Show file tree

Hide file tree

Showing 2 changed files with 13 additions and 19 deletions.
diff --git a/core/src/main/scala/spinal/core/internals/ComponentEmitterVerilog.scala b/core/src/main/scala/spinal/core/internals/ComponentEmitterVerilog.scala
@@ -1311,16 +1311,13 @@ end
     def emitWrite(b: StringBuilder, mem: Mem[_], writeEnable: String, address: Expression, data: Expression, mask: Expression with WidthProvider, symbolCount: Int, bitPerSymbole: Int, tab: String): Unit = {
 
       if(memBitsMaskKind == SINGLE_RAM || symbolCount == 1) {
-        val ramAssign = s"$tab${emitReference(mem, false)}[${emitExpression(address)}] <= ${emitExpression(data)};\n"
-
-        if (writeEnable != null) {
-          b ++= s"${tab}if(${writeEnable}) begin\n  "
-          b ++= ramAssign
-          b ++= s"${tab}end\n"
-        } else {
-          b ++= ramAssign
-        }
-
+        val ramAssign = s"$tab  ${emitReference(mem, false)}[${emitExpression(address)}] <= ${emitExpression(data)};\n"
+        var conds = if(writeEnable != null) List(writeEnable) else Nil
+        if(mask != null)
+          conds =  s"${emitExpression(mask)}[0]" :: conds
+        if(conds.nonEmpty) b ++= s"${tab}if(${conds.mkString(" && ")}) begin\n"
+        b ++= ramAssign
+        if(conds.nonEmpty) b ++= s"${tab}end\n"
       } else {
 
         def maskCount = mask.getWidth

diff --git a/core/src/main/scala/spinal/core/internals/ComponentEmitterVhdl.scala b/core/src/main/scala/spinal/core/internals/ComponentEmitterVhdl.scala
@@ -1153,15 +1153,12 @@ class ComponentEmitterVhdl(
     def emitWrite(b: StringBuilder, mem: Mem[_], writeEnable: String, address: Expression, data: Expression, mask: Expression with WidthProvider, symbolCount: Int, bitPerSymbole: Int, tab: String): Unit = {
       if(memBitsMaskKind == SINGLE_RAM || symbolCount == 1) {
         val ramAssign = s"$tab${emitReference(mem, false)}(to_integer(${emitExpression(address)})) <= ${emitExpression(data)};\n"
-
-        if (writeEnable != null) {
-          b ++= s"${tab}if ${writeEnable} then\n  "
-          b ++= ramAssign
-          b ++= s"${tab}end if;\n"
-        } else {
-          b ++= ramAssign
-        }
-
+        var conds = if(writeEnable != null) List(writeEnable) else Nil
+        if(mask != null)
+          conds =  s"${emitExpression(mask)}(0) = '1'" :: conds
+        if(conds.nonEmpty) b ++= s"${tab}if ${conds.mkString(" and ")} then\n"
+        b ++= ramAssign
+        if(conds.nonEmpty) b ++= s"${tab}end if;\n"
       } else {
 
         def maskCount = mask.getWidth