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MEESAM749/README.md

๐Ÿ‘‹ Hi, I'm Meesam!

๐Ÿ”น Passionate about Embedded Systems & Hardware Development
๐Ÿ”น Exploring Microcontrollers, FPGAs, and Low-Level Programming
๐Ÿ”น Open to collaborating on Embedded Systems projects

๐Ÿ“ฉ Reach me at: [email protected]

๐Ÿš€ Currently working on:
RISC-V Pipelined Processor Simulation in Verilog

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  1. ESP32-Home-Underground-Water-Pump-Automation-System ESP32-Home-Underground-Water-Pump-Automation-System Public

    Automating an underground water pump using LoRa modules.

    C++ 1

  2. Single-Cycle-Non-Pipelined-MIPS-32-Processor Single-Cycle-Non-Pipelined-MIPS-32-Processor Public

    This is a simulation of the MIPS32 Single Cycle Processor on Xilinx ISE written in Verilog.

    C 1

  3. Hospital-Emergency-Department-Simulator Hospital-Emergency-Department-Simulator Public

    A satistical model based software to simulate a real emergency department to optimize resource allocation. Written in C++.

    C++

  4. RISC-V-PipelinedProcessor RISC-V-PipelinedProcessor Public

    RISC-V Pipelined Processor simulation in Verilog on Xilinx ISE

    HTML 1

  5. DigitalClockWithAlarm DigitalClockWithAlarm Public

    This is a hardware implementation of a basic digital clock using logic gates and some counter ICs and a clock generator.