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modernize hal files in testsuite
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get rid of 'newsig'; replace 'linkXX' with 'net'.  This gives
different signal names in places where 'linkpp' had been used,
but this proves to be unimportant to any test.
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@jepler
jepler committed Nov 1, 2010
1 parent 6f29079 commit 10ced44
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Showing 9 changed files with 45 additions and 57 deletions.
38 changes: 17 additions & 21 deletions tests/and-or-not-mux.0/test.hal
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Original file line number Diff line number Diff line change
Expand Up @@ -8,35 +8,31 @@ loadrt mux4
loadrt sampler depth=1000 cfg=bbbff
loadrt streamer depth=32 cfg=bbbb

newsig a bit
newsig b bit
newsig c bit
newsig d bit

linkps streamer.0.pin.0 a
linkps streamer.0.pin.1 b
linkps streamer.0.pin.2 c
linkps streamer.0.pin.3 d
net a streamer.0.pin.0
net b streamer.0.pin.1
net c streamer.0.pin.2
net d streamer.0.pin.3

linksp a and2.0.in0
linksp b and2.0.in1
linkpp and2.0.out sampler.0.pin.0
net a and2.0.in0
net b and2.0.in1
net n0 and2.0.out sampler.0.pin.0

linksp a or2.0.in0
linksp b or2.0.in1
linkpp or2.0.out sampler.0.pin.1
net a or2.0.in0
net b or2.0.in1
net n1 or2.0.out sampler.0.pin.1

linksp a not.0.in
linkpp not.0.out sampler.0.pin.2
net a not.0.in
net n2 not.0.out sampler.0.pin.2

linksp a mux2.0.sel
linkpp mux2.0.out sampler.0.pin.3
net a mux2.0.sel
net n3 mux2.0.out sampler.0.pin.3
setp mux2.0.in0 1
setp mux2.0.in1 2

linksp a mux4.0.sel0
linksp b mux4.0.sel1
linkpp mux4.0.out sampler.0.pin.4
net a mux4.0.sel0
net b mux4.0.sel1
net n4 mux4.0.out sampler.0.pin.4
setp mux4.0.in0 3
setp mux4.0.in1 4
setp mux4.0.in2 5
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22 changes: 9 additions & 13 deletions tests/flipflop.0/test.hal
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Original file line number Diff line number Diff line change
Expand Up @@ -4,22 +4,18 @@ loadrt flipflop
loadrt sampler depth=1000 cfg=b
loadrt streamer depth=32 cfg=bbbb

newsig a bit
newsig b bit
newsig c bit
newsig d bit

linkps streamer.0.pin.0 a
linkps streamer.0.pin.1 b
linkps streamer.0.pin.2 c
linkps streamer.0.pin.3 d
net a streamer.0.pin.0
net b streamer.0.pin.1
net c streamer.0.pin.2
net d streamer.0.pin.3

linksp a flipflop.0.data
linksp b flipflop.0.clk
linksp c flipflop.0.reset
linksp d flipflop.0.set
net a flipflop.0.data
net b flipflop.0.clk
net c flipflop.0.reset
net d flipflop.0.set

linkpp flipflop.0.out sampler.0.pin.0
net n0 flipflop.0.out sampler.0.pin.0

addf streamer.0 fast
addf flipflop.0 fast
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2 changes: 1 addition & 1 deletion tests/limit3.0/test.hal
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ loadrt limit3
loadrt threads name1=t period1=1000000
setp limit3.0.maxv 500.000000

linkpp limit3.0.out sampler.0.pin.0
net n0 limit3.0.out sampler.0.pin.0

addf limit3.0 t
addf sampler.0 t
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2 changes: 1 addition & 1 deletion tests/limit3.1/test.hal
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ loadrt limit3
loadrt threads name1=t period1=1000000
setp limit3.0.maxv 500.000000

linkpp limit3.0.out sampler.0.pin.0
net n0 limit3.0.out sampler.0.pin.0

addf limit3.0 t
addf sampler.0 t
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2 changes: 1 addition & 1 deletion tests/limit3.2/test.hal
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ setp limit3.0.maxv 500.000000
setp limit3.0.maxa 1000
setp limit3.0.max 160

linkpp limit3.0.out sampler.0.pin.0
net n0 limit3.0.out sampler.0.pin.0

addf limit3.0 t
addf sampler.0 t
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22 changes: 9 additions & 13 deletions tests/source.0/sourced.hal
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@@ -1,18 +1,14 @@
newsig a bit
newsig b bit
newsig c bit
newsig d bit

linkps streamer.0.pin.0 a
linkps streamer.0.pin.1 b
linkps streamer.0.pin.2 c
linkps streamer.0.pin.3 d
net a streamer.0.pin.0
net b streamer.0.pin.1
net c streamer.0.pin.2
net d streamer.0.pin.3

linksp a flipflop.0.data
linksp b flipflop.0.clk
linksp c flipflop.0.reset
linksp d flipflop.0.set
net a flipflop.0.data
net b flipflop.0.clk
net c flipflop.0.reset
net d flipflop.0.set

linkpp flipflop.0.out sampler.0.pin.0
net n0 flipflop.0.out sampler.0.pin.0


4 changes: 2 additions & 2 deletions tests/stepgen.0/test.hal
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Expand Up @@ -4,8 +4,8 @@ loadrt sampler cfg=bb depth=4096
loadrt stepgen step_type=0
loadrt threads name1=fast period1=100000

linkpp stepgen.0.dir sampler.0.pin.0
linkpp stepgen.0.step sampler.0.pin.1
net n0 stepgen.0.dir sampler.0.pin.0
net n1 stepgen.0.step sampler.0.pin.1

addf stepgen.update-freq fast
addf stepgen.make-pulses fast
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6 changes: 3 additions & 3 deletions tests/stepgen.1/test.hal
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Expand Up @@ -4,9 +4,9 @@ loadrt sampler cfg=bbs depth=4000
loadrt stepgen step_type=2
loadrt threads name1=fast period1=100000

linkpp stepgen.0.phase-A sampler.0.pin.0
linkpp stepgen.0.phase-B sampler.0.pin.1
linkpp stepgen.0.counts sampler.0.pin.2
net n0 stepgen.0.phase-A sampler.0.pin.0
net n1 stepgen.0.phase-B sampler.0.pin.1
net n2 stepgen.0.counts sampler.0.pin.2

addf stepgen.update-freq fast
addf stepgen.make-pulses fast
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4 changes: 2 additions & 2 deletions tests/stepgen.2/test.hal
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Original file line number Diff line number Diff line change
Expand Up @@ -4,8 +4,8 @@ loadrt sampler cfg=bb depth=4096
loadrt stepgen step_type=0
loadrt threads name1=fast period1=100000

linkpp stepgen.0.dir sampler.0.pin.0
linkpp stepgen.0.step sampler.0.pin.1
net n0 stepgen.0.dir sampler.0.pin.0
net n1 stepgen.0.step sampler.0.pin.1

addf stepgen.update-freq fast
addf stepgen.make-pulses fast
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