Add: windows guide

Innopolis University/fpga_calculator_with_uart/README.md

@@ -28,14 +28,60 @@
     ``` text
     Boundrate: 9600
     Data bits: 8
+    Stop bits: 2
+    Parity: none
     ```
 
     *Остальные по умалчанию*
 
 4. Выбрать нужное устройство (**Device**)
-5. В поле **Input** выбрать **CR** (После отправки идёт бит с возвратом каретки). 
+
+5. В поле **Input** выбрать **CR** (После отправки идёт бит с возвратом каретки).
+
 6. В самом низу окна установить флаг **Hex output**
+
 7. Нажать на кнопку **Open**  для открытия канала связи.
 
 ![CuteCome](.pictures/CuteCome.png)
+
+---
+
+# Инструкция UART для Windows
+
+1. Скачать и запустить программу **Terminal**:
+
+    `https://github.com/DigitalDesignSchool/ce2020labs/tree/master/day_8/terminal_win.Terminal1_9_b.zip`
+
+    >[ссылка](https://github.com/DigitalDesignSchool/ce2020labs/tree/master/day_8 "Terminal")
+
+2. Подключить кабель в USB разъем пк/ноутбука и посмотреть в диспетчере устройств определился ли виртуальный ComPort подлюченного преобразователя.
+
+    ![windows_COM](.pictures/windows_COM.png)
+
+    Если же ОС не определила его, то необходимо установить драйвер для микросхемы CH340 из:
+
+    `https://github.com/DigitalDesignSchool/ce2020labs/tree/master/day_8/usb_uart_driver.ch340.zip`
+
+    >[ссылка](https://github.com/DigitalDesignSchool/ce2020labs/tree/master/day_8/ "CH340")
+
+    После чего, виртуальный ComPort должен определиться в ОС.
+
+3. Запускаем Terminal, устанавливаем в нём номер COM (в нашем случае 9) и другиие настройки:
+
+    ``` text
+    Boundrate: 9600
+    Data bits: 8
+    Parity: none
+    Stop bits: 2
+    Send: +CR
+    ```
+
+    *Остальные по умалчанию*
+
+4. Установить флаг **Hex** для приёма.
+
+5. Нажать на кнопку **Connect**  для открытия канала связи.
+
+![Terminal](.pictures/Terminal.png)
+
 ---

Innopolis University/fpga_calculator_with_uart/common/data_aggregator.sv

@@ -0,0 +1,28 @@
+module data_aggregator (
+    input       clock,
+    input       reset,
+    input       enter,
+    input       add,
+    input       multiply,
+    input       separator,
+    input [3:0] data,
+
+    output reg [7:0] number,
+    output reg enter_occured
+);
+
+  always @(posedge clock) begin
+    if (reset) begin
+      number <= 8'b0;
+      enter_occured <= 1'b0;
+    end else if (enter) begin
+      number <= {number[3:0], data};
+      enter_occured <= 1'b1;
+    end else if (add || multiply) begin
+      enter_occured <= 1'b0;
+    end else if (separator) begin
+      number <= 8'b0;
+    end
+  end
+
+endmodule

Innopolis University/fpga_calculator_with_uart/common/top.sv

@@ -13,9 +13,9 @@ module top (
   wire [7:0] ascii_data;
 
   uart_receiver listener (
-      .clock     (clock),
-      .reset_n   (reset_n),
-      .rx        (rx),
+      .clock  (clock),
+      .reset_n(reset_n),
+      .rx     (rx),
 
       .byte_data (ascii_data),
       .byte_ready(byte_ready)
@@ -31,48 +31,48 @@ module top (
       .data (ascii_data),
 
       .separator(separator),
-      .add  (add),
+      .add      (add),
       .multiply (multiply),
-      .digit(digit),
-      .enter(enter),
-      .clear(clear),
-      .error(error_ascii)
+      .digit    (digit),
+      .enter    (enter),
+      .clear    (clear),
+      .error    (error_ascii)
   );
 
 
   // Prepare and accumulate data 
 
-  reg [7:0] number;
-  reg enter_occured;
-
-  always @(posedge clock) begin
-    if (!reset_n) begin
-      number <= 8'b0;
-      enter_occured <= 1'b0;
-    end else if (enter) begin
-      number <= {number[3:0], digit};
-      enter_occured <= 1'b1;
-    end else if (add || multiply || error_ascii) begin
-      enter_occured <= 1'b0;
-    end else if (separator) begin
-      number <= 8'b0;
-    end
-  end
+  logic [7:0] number;
+  logic enter_occured;
+
+  data_aggregator aggregator (
+      .clock    (clock),
+      .reset    (~reset_n),
+      .enter    (enter),
+      .add      (add),
+      .multiply (multiply),
+      .separator(separator),
+      .data     (digit),
+
+      .number       (number),
+      .enter_occured(enter_occured)
+  );
+
+  // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
   wire [15:0] result;
   wire overflow, newresult;
   wire [3:0] error_calculator;
   wire is_tx_busy;
-  // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
   calculator calculator (
-      .clock(clock),
-      .reset(~reset_n || clear),
-      .enter(separator & enter_occured),
-      .add  (add),
+      .clock   (clock),
+      .reset   (~reset_n || clear),
+      .enter   (separator & enter_occured),
+      .add     (add),
       .multiply(multiply),
-      .data (number),
-      
+      .data    (number),
+
       .newresult(newresult),
       .result   (result),
       .overflow (overflow),
@@ -84,17 +84,17 @@ module top (
       .reset (~reset_n),
       .number(result),
 
-      .digit(nx_digit),
+      .digit   (nx_digit),
       .abcdefgh(abcdefgh)
   );
 
-  two_bytes_uart_tx loader (
+  uart_transmitter loader (
       .clock(clock),
       .reset(~reset_n),
       .start(newresult),
       .data (result),
 
-      .q(tx),
+      .q   (tx),
       .busy(is_tx_busy)
   );
 

Innopolis University/fpga_calculator_with_uart/common/uart_tx.sv → Innopolis University/fpga_calculator_with_uart/common/uart_transmitter.sv

@@ -1,4 +1,4 @@
-module two_bytes_uart_tx (
+module uart_transmitter (
     input        clock,
     input        start,
     input        reset,
@@ -8,10 +8,14 @@ module two_bytes_uart_tx (
     output     busy
 );
 
+  parameter clock_frequency = 50000000;
+  parameter baud_rate       = 9600;
+  parameter clock_cycles_in_bit = clock_frequency / baud_rate;
+
   reg [12:0] cnt;
   reg [3:0]  bit_num;
 
-  wire bit_start = (cnt == 5208);
+  wire bit_start = (cnt == clock_cycles_in_bit);
   wire idle = (bit_num == 4'hF);
   assign busy = ~idle;
 
@@ -27,7 +31,7 @@ module two_bytes_uart_tx (
 
   always @(posedge clock) begin
     if (reset) begin
-      bit_num    <= 4'hf;
+      bit_num    <= 4'hF;
       byte_state <= 1'b0;
       q <= 1'b1;
     end else if (start && idle) begin

Innopolis University/fpga_calculator_with_uart/de10_lite/top.qsf

@@ -65,10 +65,10 @@ set_global_assignment -name VERILOG_FILE ../common/Calculator/calculator.v
 set_global_assignment -name VERILOG_FILE ../common/Calculator/alu.v
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/top.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/seven_segment_4_digits.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../common/mfp_uart_receiver.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/ascii_to_action.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_tx.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_transmitter.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_receiver.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../common/data_aggregator.sv
 
 set_global_assignment -name VERILOG_FILE top.v
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tx

Innopolis University/fpga_calculator_with_uart/omdazz/top.qsf

@@ -90,8 +90,9 @@ set_global_assignment -name VERILOG_FILE ../common/Calculator/calculator.v
 set_global_assignment -name VERILOG_FILE ../common/Calculator/alu.v
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/top.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/seven_segment_4_digits.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../common/mfp_uart_receiver.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/ascii_to_action.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_tx.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_transmitter.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_receiver.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../common/data_aggregator.sv
+
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Innopolis University/fpga_calculator_with_uart/piswords/top.qsf

@@ -73,10 +73,10 @@ set_global_assignment -name VERILOG_FILE ../common/Calculator/calculator.v
 set_global_assignment -name VERILOG_FILE ../common/Calculator/alu.v
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/top.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/seven_segment_4_digits.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../common/mfp_uart_receiver.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/ascii_to_action.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_tx.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_transmitter.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_receiver.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../common/data_aggregator.sv
 
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to nx_digit[1]
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to abcdefgh[0]

Innopolis University/fpga_calculator_with_uart/rzrd/top.qsf

@@ -90,9 +90,9 @@ set_global_assignment -name VERILOG_FILE ../common/Calculator/calculator.v
 set_global_assignment -name VERILOG_FILE ../common/Calculator/alu.v
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/top.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/seven_segment_4_digits.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../common/mfp_uart_receiver.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/ascii_to_action.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_tx.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_transmitter.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_receiver.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../common/data_aggregator.sv
 
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Innopolis University/fpga_calculator_with_uart/zeowaa/top.qsf

@@ -66,17 +66,16 @@ set_location_assignment PIN_132 -to nx_digit[2]
 set_location_assignment PIN_129 -to nx_digit[1]
 set_location_assignment PIN_23 -to clock
 
-
 set_global_assignment -name VERILOG_INCLUDE_FILE ../common/Calculator/defines.vh
 set_global_assignment -name VERILOG_FILE ../common/Calculator/stack.v
 set_global_assignment -name VERILOG_FILE ../common/Calculator/calculator.v
 set_global_assignment -name VERILOG_FILE ../common/Calculator/alu.v
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/top.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/seven_segment_4_digits.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../common/mfp_uart_receiver.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/ascii_to_action.sv
-set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_tx.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_transmitter.sv
 set_global_assignment -name SYSTEMVERILOG_FILE ../common/uart_receiver.sv
+set_global_assignment -name SYSTEMVERILOG_FILE ../common/data_aggregator.sv
 
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top