[upstream] [2024-02-09] Prepare commits

gcc/ChangeLog

@@ -1,3 +1,221 @@
+2024-02-08  Aldy Hernandez  <[email protected]>
+
+	PR tree-optimization/113735
+	* value-relation.cc (equiv_oracle::add_equiv_to_block): Call
+	limit_check().
+
+2024-02-08  Georg-Johann Lay  <[email protected]>
+
+	* config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
+	(main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
+
+2024-02-08  H.J. Lu  <[email protected]>
+
+	PR target/113711
+	PR target/113733
+	* config/i386/constraints.md: List all constraints with j prefix.
+	(j>): Change auto-dec to auto-inc in documentation.
+	(je): Changed to a memory constraint with APX NDD TLS operand
+	check.
+	(jM): New memory constraint for APX NDD instructions.
+	(jO): Likewise.
+	* config/i386/i386-protos.h (x86_poff_operand_p): Removed.
+	* config/i386/i386.cc (x86_poff_operand_p): Likewise.
+	* config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
+	(*add<mode>_1[SWI48]): Use je and jM.
+	(addsi_1_zext): Use jM.
+	(*addv<dwi>4_doubleword_1[DWI]): Likewise.
+	(*sub<mode>_1[SWI]): Use jM.
+	(@add<mode>3_cc_overflow_1[SWI]): Likewise.
+	(*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
+	(*and<dwi>3_doubleword): Likewise.
+	(*anddi_1): Use jM.
+	(*andsi_1_zext): Likewise.
+	(*and<mode>_1[SWI24]): Likewise.
+	(*<code><dwi>3_doubleword[any_or]): Use rjO
+	(*code<mode>_1[any_or SWI248]): Use jM.
+	(*<code>si_1_zext[zero_extend + any_or]): Likewise.
+	* config/i386/predicates.md (apx_ndd_memory_operand): New.
+	(apx_ndd_add_memory_operand): Likewise.
+
+2024-02-08  Georg-Johann Lay  <[email protected]>
+
+	PR target/113824
+	* config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
+	* doc/avr-mmcu.texi: Rebuild.
+
+2024-02-08  Tamar Christina  <[email protected]>
+
+	PR tree-optimization/113808
+	* tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
+	value cross iterations.
+
+2024-02-08  Georg-Johann Lay  <[email protected]>
+
+	* config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
+	defines __AVR_PM_BASE_ADDRESS__ if the core has it.
+
+2024-02-08  Richard Biener  <[email protected]>
+
+	* tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
+	Revert last change to dr_may_alias_p.
+
+2024-02-08  Georg-Johann Lay  <[email protected]>
+
+	* config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
+	cc1_rodata_in_ram.  Rename spec link_misc to link_rodata_in_ram.
+	Remove spec asm_misc.
+	* config/avr/specs.h: Same.
+
+2024-02-08  Pan Li  <[email protected]>
+
+	PR target/113766
+	* config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
+	sure the c.arg_num is >= 2 before checking.
+	(struct build_frm_base): Ditto.
+	(struct narrow_alu_def): Ditto.
+
+2024-02-07  Richard Biener  <[email protected]>
+
+	PR tree-optimization/113796
+	* tree-if-conv.cc (combine_blocks): Wipe range-info before
+	replacing PHIs and inserting predicates.
+
+2024-02-07  Roger Sayle  <[email protected]>
+	    Uros Bizjak  <[email protected]>
+
+	PR target/113690
+	* config/i386/i386-features.cc (timode_convert_cst): New helper
+	function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
+	CONST_VECTOR.
+	(timode_scalar_chain::convert_op): Use timode_convert_cst.
+	(timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
+	Use timode_convert_cst.
+
+2024-02-07  Victor Do Nascimento  <[email protected]>
+
+	* config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
+	* config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
+	(AARCH64_FL_DEBUGv8p9): Likewise.
+	(AARCH64_FL_FGT2): Likewise.Likewise.
+	(AARCH64_FL_ITE): Likewise.
+	(AARCH64_FL_PFAR): Likewise.
+	(AARCH64_FL_PMUv3_ICNTR): Likewise.
+	(AARCH64_FL_PMUv3_SS): Likewise.
+	(AARCH64_FL_PMUv3p9): Likewise.
+	(AARCH64_FL_RASv2): Likewise.
+	(AARCH64_FL_S1PIE): Likewise.
+	(AARCH64_FL_S1POE): Likewise.
+	(AARCH64_FL_S2PIE): Likewise.
+	(AARCH64_FL_S2POE): Likewise.
+	(AARCH64_FL_SCTLR2): Likewise.
+	(AARCH64_FL_SEBEP): Likewise.
+	(AARCH64_FL_SPE_FDS): Likewise.
+	(AARCH64_FL_TCR2): Likewise.
+
+2024-02-07  Richard Biener  <[email protected]>
+
+	* tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
+	Only check whether reads are in-bound in places that are not safe.
+	Fix dependence check.  Add missing newline.  Clarify comments.
+
+2024-02-07  Tamar Christina  <[email protected]>
+
+	PR tree-optimization/113750
+	* tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
+	for single predecessor when doing early break vect.
+	* tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
+	after labels.
+
+2024-02-07  Tamar Christina  <[email protected]>
+
+	PR tree-optimization/113731
+	* gimple-iterator.cc (gsi_move_before): Take new parameter for update
+	method.
+	* gimple-iterator.h (gsi_move_before): Default new param to
+	GSI_SAME_STMT.
+	* tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
+	GSI_NEW_STMT.
+
+2024-02-07  Jakub Jelinek  <[email protected]>
+
+	PR tree-optimization/113756
+	* range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
+	use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
+	of lh_bits value and mask.
+
+2024-02-07  Jakub Jelinek  <[email protected]>
+
+	PR tree-optimization/113753
+	* wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
+	UNSIGNED rather than SIGNED.  If high or needs_overflow and prec is
+	not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
+	so that they start with r[half_blocks_needed] lowest bit.  Fix up
+	computation of top mask for SIGNED.
+
+2024-02-07  Pan Li  <[email protected]>
+
+	PR target/113766
+	* config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
+	the signature of func.
+	* config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
+	* config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
+	overloaded func with empty args error.
+
+2024-02-06  H.J. Lu  <[email protected]>
+
+	PR target/113689
+	* config/i386/i386.cc (x86_64_select_profile_regnum): Return
+	R10_REG after sorry.
+
+2024-02-06  Andrew Carlotti  <[email protected]>
+
+	* config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
+	Move before new caller, and add ".default" suffix.
+	(get_suffixed_assembler_name): New.
+	(make_resolver_func): Use get_suffixed_assembler_name.
+	(aarch64_generate_version_dispatcher_body): Redo name mangling.
+
+2024-02-06  Jakub Jelinek  <[email protected]>
+
+	PR target/113763
+	* config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
+	element from std::pair<unsigned int, char> to an unnamed struct.
+	Adjust uses of tile range variable.
+
+2024-02-06  Juzhe-Zhong  <[email protected]>
+
+	* config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
+	(pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
+
+2024-02-06  Jakub Jelinek  <[email protected]>
+
+	PR sanitizer/110676
+	* gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
+	reset maxlen to sizetype maximum.
+
+2024-02-06  Jakub Jelinek  <[email protected]>
+
+	PR tree-optimization/113736
+	* gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
+	var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
+
+2024-02-06  Jakub Jelinek  <[email protected]>
+
+	PR tree-optimization/113759
+	* tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
+	or from_unsignedN differs from properties of typeN, update typeN
+	to build_nonstandard_integer_type.  If TREE_TYPE (rhsN) is not
+	uselessly convertible to typeN, convert it using fold_convert or
+	build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
+	(convert_plusminus_to_widen): Likewise.
+
+2024-02-06  Tejas Belagod  <[email protected]>
+
+	PR target/112577
+	* config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
+	vector structure modes correctly.
+
 2024-02-05  Christoph Müllner  <[email protected]>
 
 	* config/riscv/thead.cc (th_print_operand_address): Fix compiler

gcc/DATESTAMP

@@ -1 +1 @@
-20240206
+20240209

gcc/c/ChangeLog

@@ -1,3 +1,10 @@
+2024-02-08  Joseph Myers  <[email protected]>
+
+	PR c/113776
+	* c-typeck.cc (c_objc_common_truthvalue_conversion): Return an
+	integer constant expression for boolean conversion of floating
+	constant.
+
 2024-02-05  Jakub Jelinek  <[email protected]>
 
 	PR c/113740

gcc/c/c-typeck.cc

@@ -13572,7 +13572,17 @@ c_objc_common_truthvalue_conversion (location_t location, tree expr, tree type)
       break;
     }
 
-  int_const = (TREE_CODE (expr) == INTEGER_CST && !TREE_OVERFLOW (expr));
+  /* Conversion of a floating constant to boolean goes through here
+     and yields an integer constant expression.  Otherwise, the result
+     is only an integer constant expression if the argument is.  */
+  int_const = ((TREE_CODE (expr) == INTEGER_CST && !TREE_OVERFLOW (expr))
+	       || ((TREE_CODE (expr) == REAL_CST
+		    || TREE_CODE (expr) == COMPLEX_CST)
+		   && (TREE_CODE (type) == BOOLEAN_TYPE
+		       || (TREE_CODE (type) == ENUMERAL_TYPE
+			   && ENUM_UNDERLYING_TYPE (type) != NULL_TREE
+			   && (TREE_CODE (ENUM_UNDERLYING_TYPE (type))
+			       == BOOLEAN_TYPE)))));
   int_operands = EXPR_INT_CONST_OPERANDS (expr);
   if (int_operands && TREE_CODE (expr) != INTEGER_CST)
     {

gcc/cfgexpand.cc

@@ -3671,16 +3671,21 @@ expand_asm_stmt (gasm *stmt)
 	{
 	  edge e;
 	  edge_iterator ei;
-
+	  unsigned int cnt = EDGE_COUNT (gimple_bb (stmt)->succs);
+
 	  FOR_EACH_EDGE (e, ei, gimple_bb (stmt)->succs)
 	    {
-	      start_sequence ();
-	      for (rtx_insn *curr = after_rtl_seq;
-		   curr != NULL_RTX;
-		   curr = NEXT_INSN (curr))
-		emit_insn (copy_insn (PATTERN (curr)));
-	      rtx_insn *copy = get_insns ();
-	      end_sequence ();
+	      rtx_insn *copy;
+	      if (--cnt == 0)
+		copy = after_rtl_seq;
+	      else
+		{
+		  start_sequence ();
+		  duplicate_insn_chain (after_rtl_seq, after_rtl_end,
+					NULL, NULL);
+		  copy = get_insns ();
+		  end_sequence ();
+		}
 	      insert_insn_on_edge (copy, e);
 	    }
 	}