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Made the verilog module consistent with the Circuit simulation logic #619

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Merged
merged 2 commits into from
Aug 24, 2025
Merged

Made the verilog module consistent with the Circuit simulation logic #619

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c71af00
made the verilog module consistent with the simulation logic
092vk Jun 29, 2025
ed50302
fixed logic
092vk Aug 24, 2025
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21 changes: 11 additions & 10 deletions src/simulator/src/sequential/DflipFlop.js
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Original file line number Diff line number Diff line change
Expand Up @@ -135,17 +135,18 @@ export default class DflipFlop extends CircuitElement {
module DflipFlop(q, q_inv, clk, d, a_rst, pre, en);
parameter WIDTH = 1;
output reg [WIDTH-1:0] q, q_inv;
input clk, a_rst, pre, en;
input [WIDTH-1:0] d;
input clk, a_rst, en;
input [WIDTH-1:0] d, pre;

always @ (posedge clk or posedge a_rst)
if (a_rst) begin
q <= 'b0;
q_inv <= 'b1;
end else if (en == 0) ;
else begin
q <= d;
q_inv <= ~d;
always @ (posedge clk or posedge a_rst) begin
if (a_rst) begin
q <= pre;
q_inv <= ~pre;
end else if (en) begin
q <= d;
q_inv <= ~d;
end
// When en == 0, hold current state
end
endmodule
`
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