Added the Verilog Module for D-latch #594
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Assessment against linked issues: Out-of-scope changesNo out-of-scope changes were found. Warning There were issues while running some tools. Please review the errors and either fix the tool's configuration or disable the tool if it's a critical failure. 🔧 ESLint
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Actionable comments posted: 0
🧹 Nitpick comments (2)
v1/src/simulator/src/sequential/Dlatch.js (2)
113-114: Fix indentation of the returned template literal.The `return `` line is not indented to match the surrounding method body, which hampers readability.
Apply this diff to align it with the rest of the code:
- static moduleVerilog() { - return ` + static moduleVerilog() { + return `and indent the enclosed Verilog string by one additional level.
115-133: Use modern Verilog port and parameter syntax.Inline the
WIDTHparameter in the module declaration and declare port directions in the header for clearer, more idiomatic Verilog:-static module Dlatch(q,q_inv,clk,d); - parameter WIDTH = 1; - output reg [WIDTH-1:0]q; - output reg [WIDTH-1:0]q_inv; - input wire [WIDTH-1:0]d; - input wire clk; +module Dlatch #( + parameter WIDTH = 1 +) ( + input wire clk, + input wire [WIDTH-1:0] d, + output reg [WIDTH-1:0] q, + output reg [WIDTH-1:0] q_inv +);Additionally, for level-sensitive latches prefer a sensitivity list of
@(clk or d)and consider using blocking assignments (=) inside the always block to match common latch style.
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Actionable comments posted: 0
🧹 Nitpick comments (1)
src/simulator/src/sequential/Dlatch.js (1)
101-122: LGTM! Well-implemented D-latch Verilog module.The Verilog module correctly implements a level-triggered D-latch that aligns with the JavaScript simulation logic. The behavioral description properly captures the latch functionality where outputs follow inputs when
clkis high and preserve state whenclkis low.Minor suggestion for improved readability:
- // prev state is preserved in case of else or clk = 0 + // previous state is preserved when clk = 0
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src/simulator/src/sequential/Dlatch.js(1 hunks)
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🧠 Learnings (2)
📓 Common learnings
Learnt from: 092vk
PR: CircuitVerse/cv-frontend-vue#591
File: v1/src/simulator/src/sequential/JKflipFlop.js:159-188
Timestamp: 2025-06-10T11:26:38.102Z
Learning: In the CircuitVerse project, Verilog modules for circuit elements like JKflipFlop are designed to be consistent with the circuit simulation design, which means reset and preset signals are implemented synchronously (triggered on clock edge) rather than asynchronously, even when the signals are named as asynchronous reset/preset.
src/simulator/src/sequential/Dlatch.js (2)
Learnt from: 092vk
PR: CircuitVerse/cv-frontend-vue#593
File: v1/src/simulator/src/modules/ALU.js:191-192
Timestamp: 2025-06-10T11:55:53.137Z
Learning: The ALU Verilog module in v1/src/simulator/src/modules/ALU.js currently only supports 1-bit processing. Width parameter support will be added in the future for scalability, even though the JavaScript ALU implementation already supports variable bit widths.
Learnt from: 092vk
PR: CircuitVerse/cv-frontend-vue#591
File: v1/src/simulator/src/sequential/JKflipFlop.js:159-188
Timestamp: 2025-06-10T11:26:38.102Z
Learning: In the CircuitVerse project, Verilog modules for circuit elements like JKflipFlop are designed to be consistent with the circuit simulation design, which means reset and preset signals are implemented synchronously (triggered on clock edge) rather than asynchronously, even when the signals are named as asynchronous reset/preset.
Fixes #560
Describe the changes you have made in this PR -
Note: Please check Allow edits from maintainers. if you would like us to assist in the PR.
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