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zohourihzohourih
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Parameterize channel depth
1 parent 833403d commit d763ba1

5 files changed

+50
-29
lines changed

‎Makefile

+5
Original file line numberDiff line numberDiff line change
@@ -69,6 +69,11 @@ ifeq ($(INTEL_FPGA),1)
6969
EXTRA_CONFIG := $(EXTRA_CONFIG)_nocache
7070
endif
7171

72+
ifdef DEPTH
73+
KERNEL_FLAGS += -DDEPTH $(DEPTH)
74+
EXTRA_CONFIG := $(EXTRA_CONFIG)_depth$(DEPTH)
75+
endif
76+
7277
ifdef TFMAX
7378
KERNEL_FLAGS += $(DASH)fmax$(SPACE)$(TFMAX)
7479
EXTRA_CONFIG := $(EXTRA_CONFIG)_tfmax$(TFMAX)

‎fpga-mem-bench-kernel-chblk2d.cl

+12-8
Original file line numberDiff line numberDiff line change
@@ -13,19 +13,23 @@
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#define write_channel write_channel_intel
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#endif
1515

16+
#ifndef DEPTH
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#define DEPTH 16
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#endif
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1620
typedef struct
1721
{
1822
float data[VEC];
1923
} CHAN_WIDTH;
2024

21-
channel CHAN_WIDTH ch_R1W1 __attribute__((depth(16)));
22-
channel CHAN_WIDTH ch_R2W1_a __attribute__((depth(16)));
23-
channel CHAN_WIDTH ch_R2W1_b __attribute__((depth(16)));
24-
channel CHAN_WIDTH ch_R3W1_a __attribute__((depth(16)));
25-
channel CHAN_WIDTH ch_R3W1_b __attribute__((depth(16)));
26-
channel CHAN_WIDTH ch_R3W1_c __attribute__((depth(16)));
27-
channel CHAN_WIDTH ch_R2W2_a __attribute__((depth(16)));
28-
channel CHAN_WIDTH ch_R2W2_b __attribute__((depth(16)));
25+
channel CHAN_WIDTH ch_R1W1 __attribute__((depth(DEPTH)));
26+
channel CHAN_WIDTH ch_R2W1_a __attribute__((depth(DEPTH)));
27+
channel CHAN_WIDTH ch_R2W1_b __attribute__((depth(DEPTH)));
28+
channel CHAN_WIDTH ch_R3W1_a __attribute__((depth(DEPTH)));
29+
channel CHAN_WIDTH ch_R3W1_b __attribute__((depth(DEPTH)));
30+
channel CHAN_WIDTH ch_R3W1_c __attribute__((depth(DEPTH)));
31+
channel CHAN_WIDTH ch_R2W2_a __attribute__((depth(DEPTH)));
32+
channel CHAN_WIDTH ch_R2W2_b __attribute__((depth(DEPTH)));
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3034
//=====================================================================
3135
// NDRange Kernels

‎fpga-mem-bench-kernel-chblk3d.cl

+12-8
Original file line numberDiff line numberDiff line change
@@ -13,19 +13,23 @@
1313
#define write_channel write_channel_intel
1414
#endif
1515

16+
#ifndef DEPTH
17+
#define DEPTH 16
18+
#endif
19+
1620
typedef struct
1721
{
1822
float data[VEC];
1923
} CHAN_WIDTH;
2024

21-
channel CHAN_WIDTH ch_R1W1 __attribute__((depth(16)));
22-
channel CHAN_WIDTH ch_R2W1_a __attribute__((depth(16)));
23-
channel CHAN_WIDTH ch_R2W1_b __attribute__((depth(16)));
24-
channel CHAN_WIDTH ch_R3W1_a __attribute__((depth(16)));
25-
channel CHAN_WIDTH ch_R3W1_b __attribute__((depth(16)));
26-
channel CHAN_WIDTH ch_R3W1_c __attribute__((depth(16)));
27-
channel CHAN_WIDTH ch_R2W2_a __attribute__((depth(16)));
28-
channel CHAN_WIDTH ch_R2W2_b __attribute__((depth(16)));
25+
channel CHAN_WIDTH ch_R1W1 __attribute__((depth(DEPTH)));
26+
channel CHAN_WIDTH ch_R2W1_a __attribute__((depth(DEPTH)));
27+
channel CHAN_WIDTH ch_R2W1_b __attribute__((depth(DEPTH)));
28+
channel CHAN_WIDTH ch_R3W1_a __attribute__((depth(DEPTH)));
29+
channel CHAN_WIDTH ch_R3W1_b __attribute__((depth(DEPTH)));
30+
channel CHAN_WIDTH ch_R3W1_c __attribute__((depth(DEPTH)));
31+
channel CHAN_WIDTH ch_R2W2_a __attribute__((depth(DEPTH)));
32+
channel CHAN_WIDTH ch_R2W2_b __attribute__((depth(DEPTH)));
2933

3034
//=====================================================================
3135
// NDRange Kernels

‎fpga-mem-bench-kernel-chstd.cl

+13-9
Original file line numberDiff line numberDiff line change
@@ -13,20 +13,24 @@
1313
#define write_channel write_channel_intel
1414
#endif
1515

16+
#ifndef DEPTH
17+
#define DEPTH 16
18+
#endif
19+
1620
typedef struct
1721
{
1822
float data[VEC];
1923
} CHAN_WIDTH;
2024

21-
channel CHAN_WIDTH ch_R1W0 __attribute__((depth(16)));
22-
channel CHAN_WIDTH ch_R1W1 __attribute__((depth(16)));
23-
channel CHAN_WIDTH ch_R2W1_a __attribute__((depth(16)));
24-
channel CHAN_WIDTH ch_R2W1_b __attribute__((depth(16)));
25-
channel CHAN_WIDTH ch_R3W1_a __attribute__((depth(16)));
26-
channel CHAN_WIDTH ch_R3W1_b __attribute__((depth(16)));
27-
channel CHAN_WIDTH ch_R3W1_c __attribute__((depth(16)));
28-
channel CHAN_WIDTH ch_R2W2_a __attribute__((depth(16)));
29-
channel CHAN_WIDTH ch_R2W2_b __attribute__((depth(16)));
25+
channel CHAN_WIDTH ch_R1W0 __attribute__((depth(DEPTH)));
26+
channel CHAN_WIDTH ch_R1W1 __attribute__((depth(DEPTH)));
27+
channel CHAN_WIDTH ch_R2W1_a __attribute__((depth(DEPTH)));
28+
channel CHAN_WIDTH ch_R2W1_b __attribute__((depth(DEPTH)));
29+
channel CHAN_WIDTH ch_R3W1_a __attribute__((depth(DEPTH)));
30+
channel CHAN_WIDTH ch_R3W1_b __attribute__((depth(DEPTH)));
31+
channel CHAN_WIDTH ch_R3W1_c __attribute__((depth(DEPTH)));
32+
channel CHAN_WIDTH ch_R2W2_a __attribute__((depth(DEPTH)));
33+
channel CHAN_WIDTH ch_R2W2_b __attribute__((depth(DEPTH)));
3034

3135
//=====================================================================
3236
// NDRange Kernels

‎fpga-mem-bench-kernel-sch.cl

+8-4
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,10 @@
1313
#define write_channel write_channel_intel
1414
#endif
1515

16+
#ifndef DEPTH
17+
#define DEPTH 16
18+
#endif
19+
1620
#define HALF_VEC VEC/2
1721
#define WGS 64
1822

@@ -22,11 +26,11 @@ typedef struct
2226
} CHAN_WIDTH;
2327

2428
#ifdef FPGA_1
25-
channel CHAN_WIDTH sch_copy_out0 __attribute__((depth(16))) __attribute__((io("kernel_output_ch0" )));
26-
channel CHAN_WIDTH sch_copy_out1 __attribute__((depth(16))) __attribute__((io("kernel_output_ch1" )));
29+
channel CHAN_WIDTH sch_copy_out0 __attribute__((depth(DEPTH))) __attribute__((io("kernel_output_ch0" )));
30+
channel CHAN_WIDTH sch_copy_out1 __attribute__((depth(DEPTH))) __attribute__((io("kernel_output_ch1" )));
2731
#else
28-
channel CHAN_WIDTH sch_copy_in0 __attribute__((depth(16))) __attribute__((io("kernel_input_ch0")));
29-
channel CHAN_WIDTH sch_copy_in1 __attribute__((depth(16))) __attribute__((io("kernel_input_ch1")));
32+
channel CHAN_WIDTH sch_copy_in0 __attribute__((depth(DEPTH))) __attribute__((io("kernel_input_ch0")));
33+
channel CHAN_WIDTH sch_copy_in1 __attribute__((depth(DEPTH))) __attribute__((io("kernel_input_ch1")));
3034
#endif
3135

3236
#ifdef NDR //NDRange kernels

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