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boards: enbables support for s32z270 hse crypto
Enable test for s32z270 hash crypto. Enable samples for cipher cryptoEndable samples for EBC, CBC, CTR mode of cipher crypto. Signed-off-by: Ha Duong Quang <[email protected]>
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‎boards/nxp/s32z2xxdc2/doc/index.rst

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@@ -180,6 +180,19 @@ External Flash
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The on-board S26HS512T 512M-bit HyperFlash memory is connected to the QSPI controller
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port A1. This board configuration selects it as the default flash controller.
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CRYPTO
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======
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The Hardware Security Engine (HSE) supports cryptographic operations, including hashing and
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symmetric ciphers, with capabilities for ECB, CBC, and CTR modes using RAM-based key catalogs
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with 128-bit or 256-bit key lengths.
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.. note::
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The driver assumes that the HSE Firmware has been installed and configured (i.e the key catalogs
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has been formatted, used MU instances has been activated, etc). HSE Firmware installation and
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configuration phase documented in HSE Firmware User Manual. Please contact NXP sales person or
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NXP distributor in order to have access to that document.
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Programming and Debugging
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*************************
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‎boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml

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- i2c
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- dma
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- pwm
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- crypto
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vendor: nxp

‎boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml

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- i2c
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- dma
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- pwm
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- crypto
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vendor: nxp

‎boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml

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- i2c
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- dma
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- pwm
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- crypto
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vendor: nxp

‎boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml

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- i2c
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- dma
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- pwm
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- crypto
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vendor: nxp

‎samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.overlay

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&mub0 {
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status = "okay";
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};

‎samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.overlay

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&mub2 {
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status = "okay";
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};

‎samples/drivers/crypto/src/main.c

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#define CRYPTO_DEV_COMPAT st_stm32_aes
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#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_mcux_dcp)
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#define CRYPTO_DEV_COMPAT nxp_mcux_dcp
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#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_crypto_hse_mu)
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#define CRYPTO_DEV_COMPAT nxp_s32_crypto_hse_mu
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#elif CONFIG_CRYPTO_NRF_ECB
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#define CRYPTO_DEV_COMPAT nordic_nrf_ecb
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#elif DT_HAS_COMPAT_STATUS_OKAY(renesas_smartbond_crypto)

‎tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.overlay

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&mub0 {
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status = "okay";
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};

‎tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.overlay

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&mub2 {
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status = "okay";
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};

‎tests/crypto/crypto_hash/src/main.c

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/*
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* Copyright (c) 2022 Intel Corporation
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define CRYPTO_DRV_NAME CONFIG_CRYPTO_MBEDTLS_SHIM_DRV_NAME
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#elif DT_HAS_COMPAT_STATUS_OKAY(renesas_smartbond_crypto)
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#define CRYPTO_DEV_COMPAT renesas_smartbond_crypto
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#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_crypto_hse_mu)
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#define CRYPTO_DEV_COMPAT nxp_s32_crypto_hse_mu
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#else
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#error "You need to enable one crypto device"
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#endif

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