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drivers: pwm: sf32lb: add pwm driver support
Add pwm driver for sf32lb platform Signed-off-by: Qingsong Gou <[email protected]>
1 parent 0735cf9 commit abaa219

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‎drivers/pwm/CMakeLists.txt‎

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@@ -29,6 +29,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_MAX32 pwm_max32.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_TPM pwm_mcux_tpm.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SAM0_TCC pwm_sam0_tcc.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SAM0_TC pwm_sam0_tc.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SF32LB pwm_sf32lb.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NPCX pwm_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_XLNX_AXI_TIMER pwm_xlnx_axi_timer.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_PWT pwm_mcux_pwt.c)

‎drivers/pwm/Kconfig‎

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@@ -88,6 +88,8 @@ source "drivers/pwm/Kconfig.mcux_pwt"
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source "drivers/pwm/Kconfig.gecko"
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source "drivers/pwm/Kconfig.sf32lb"
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source "drivers/pwm/Kconfig.silabs"
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source "drivers/pwm/Kconfig.siwx91x"

‎drivers/pwm/Kconfig.sf32lb‎

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# Copyright (c) 2025, Qingsong Gou <[email protected]>
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# SPDX-License-Identifier: Apache-2.0
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config PWM_SF32LB
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bool "PWM driver for SF32LB family of MCUs"
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default y
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depends on DT_HAS_SIFLI_SF32LB_PWM_ENABLED
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select USE_SIFLI_HAL
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select USE_SIFLI_HAL_GPT
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help
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Enable PWM driver for SF32LB series of MCUs. This driver uses
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the timer peripheral to implement PWM functionality.

‎drivers/pwm/pwm_sf32lb.c‎

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/*
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* Copyright (c) 2025, Qingsong Gou <[email protected]>
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sifli_sf32lb_pwm
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/pwm.h>
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#include <zephyr/drivers/clock_control/sf32lb.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include <register.h>
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#include <bf0_hal.h>
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#include <bf0_hal_tim.h>
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#define GPT_CR1 offsetof(GPT_TypeDef, CR1)
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#define GPT_PSC offsetof(GPT_TypeDef, PSC)
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#define GPT_ARR offsetof(GPT_TypeDef, ARR)
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#define GPT_CCR1 offsetof(GPT_TypeDef, CCR1)
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#define GPT_CCER offsetof(GPT_TypeDef, CCER)
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#define GPT_CCMR1 offsetof(GPT_TypeDef, CCMR1)
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#define GPT_EGR offsetof(GPT_TypeDef, EGR)
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#define GPT_CCMRX(ch) (GPT_CCMR1 + (ch >> 1U))
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#define CCRX(ch) (GPT_CCR1 + ((ch) << 2U))
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LOG_MODULE_REGISTER(pwm_sf32lb, CONFIG_PWM_LOG_LEVEL);
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struct pwm_sf32lb_config {
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const struct pinctrl_dev_config *pcfg;
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const struct device *clock_dev;
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uint16_t clock_id;
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uintptr_t base;
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uint32_t clock_freq;
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uint16_t prescaler;
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};
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static int pwm_sf32lb_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles,
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uint32_t pulse_cycles, pwm_flags_t flags)
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{
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const struct pwm_sf32lb_config *config = dev->config;
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uint8_t pos;
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pos = channel * 4U;
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LOG_DBG("Setting PWM period_cycles: %d, pulse_cycles: %d", period_cycles, pulse_cycles);
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if (period_cycles == 0) {
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LOG_ERR("Invalid period cycles");
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return -EINVAL;
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}
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if (pulse_cycles > period_cycles) {
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LOG_ERR("Pulse cycles %d > period cycles %d", pulse_cycles, period_cycles);
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return -EINVAL;
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}
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if ((period_cycles > UINT16_MAX + 1U) || (pulse_cycles > UINT16_MAX + 1U)) {
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return -EINVAL;
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}
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sys_clear_bit(config->base + GPT_CCER, pos);
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if (flags & PWM_POLARITY_INVERTED) {
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sys_set_bits(config->base + GPT_CCER, GPT_CCER_CC1P << pos);
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}
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sys_write32(period_cycles - 1, config->base + GPT_ARR);
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sys_write32(pulse_cycles - 1, config->base + CCRX(channel));
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switch (channel) {
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case 0:
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sys_clear_bits(config->base + GPT_CCMRX(channel), GPT_CCMR1_OC1M);
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sys_set_bits(config->base + GPT_CCMRX(channel), GPT_CCMR1_OC1PE);
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sys_set_bits(config->base + GPT_CCMRX(channel), GPT_OCMODE_PWM1);
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break;
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case 1:
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sys_clear_bits(config->base + GPT_CCMRX(channel), GPT_CCMR1_OC2M);
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sys_set_bits(config->base + GPT_CCMRX(channel), GPT_CCMR1_OC2PE);
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sys_set_bits(config->base + GPT_CCMRX(channel), GPT_OCMODE_PWM1);
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break;
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case 2:
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sys_clear_bits(config->base + GPT_CCMRX(channel), GPT_CCMR2_OC3M);
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sys_set_bits(config->base + GPT_CCMRX(channel), GPT_CCMR2_OC3PE);
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sys_set_bits(config->base + GPT_CCMRX(channel), GPT_OCMODE_PWM1);
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break;
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case 3:
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sys_clear_bits(config->base + GPT_CCMRX(channel), GPT_CCMR2_OC4M);
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sys_set_bits(config->base + GPT_CCMRX(channel), GPT_CCMR2_OC4PE);
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sys_set_bits(config->base + GPT_CCMRX(channel), GPT_OCMODE_PWM1);
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break;
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default:
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break;
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}
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sys_set_bit(config->base + GPT_CCER, pos);
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return 0;
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}
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static int pwm_sf32lb_get_cycles_per_sec(const struct device *dev, uint32_t channel,
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uint64_t *cycles)
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{
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const struct pwm_sf32lb_config *config = dev->config;
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if (config->clock_freq > 0) {
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*cycles = (uint64_t)(config->clock_freq / (config->prescaler + 1U));
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return 0;
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}
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*cycles = (uint64_t)48000000UL;
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return 0;
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}
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static int pwm_sf32lb_init(const struct device *dev)
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{
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const struct pwm_sf32lb_config *config = dev->config;
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int ret;
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if (!device_is_ready(config->clock_dev)) {
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return -ENODEV;
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}
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ret = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_id);
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if (ret < 0) {
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return ret;
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}
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("Failed to configure pins");
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return ret;
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}
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sys_write32(config->prescaler, config->base + GPT_PSC);
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sys_set_bit(config->base + GPT_EGR, GPT_EGR_UG_Pos);
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sys_set_bit(config->base + GPT_CR1, GPT_CR1_CEN_Pos);
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return ret;
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}
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static DEVICE_API(pwm, pwm_sf32lb_driver_api) = {
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.set_cycles = pwm_sf32lb_set_cycles,
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.get_cycles_per_sec = pwm_sf32lb_get_cycles_per_sec,
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};
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#define PWM_SF32LB_DEFINE(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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static const struct pwm_sf32lb_config pwm_sf32lb_config_##n = { \
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.base = DT_REG_ADDR(DT_INST_PARENT(n)), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
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.clock_id = DT_CLOCKS_CELL(DT_INST_PARENT(n), id), \
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.prescaler = DT_PROP(DT_INST_PARENT(n), prescaler), \
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.clock_freq = DT_PROP_OR(DT_INST_PARENT(n), clock_frequency, {}), \
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}; \
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DEVICE_DT_INST_DEFINE(n, pwm_sf32lb_init, NULL, NULL, \
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&pwm_sf32lb_config_##n, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
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&pwm_sf32lb_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_SF32LB_DEFINE)

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