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congnguyenhuummahadevan108
congnguyenhuu
authored and
mmahadevan108
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boards: s32z270: enable support psi5
enable support psi5 Signed-off-by: Cong Nguyen Huu <[email protected]>
1 parent ade4a7b commit 13ad0fa

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‎boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,4 +21,5 @@ supported:
2121
- dma
2222
- pwm
2323
- sent
24+
- psi5
2425
vendor: nxp

‎boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,4 +21,5 @@ supported:
2121
- dma
2222
- pwm
2323
- sent
24+
- psi5
2425
vendor: nxp

‎boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,4 +21,5 @@ supported:
2121
- dma
2222
- pwm
2323
- sent
24+
- psi5
2425
vendor: nxp

‎boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,4 +21,5 @@ supported:
2121
- dma
2222
- pwm
2323
- sent
24+
- psi5
2425
vendor: nxp

‎dts/arm/nxp/nxp_s32z27x_r52.dtsi

Lines changed: 325 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1571,5 +1571,330 @@
15711571
status = "disabled";
15721572
};
15731573
};
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psi5_0: psi5@401e0000 {
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compatible = "nxp,s32-psi5";
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reg = <0x401e0000 0x1000>;
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#address-cells = <1>;
1579+
#size-cells = <0>;
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status = "disabled";
1581+
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psi5_0_ch0: ch@0 {
1583+
reg = <0>;
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interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1585+
#address-cells = <1>;
1586+
#size-cells = <0>;
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status = "disabled";
1588+
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psi5_0_ch0_rx_slot0: slot@0 {
1590+
reg = <0>;
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status = "disabled";
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};
1593+
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psi5_0_ch0_rx_slot1: slot@1 {
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reg = <1>;
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status = "disabled";
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};
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psi5_0_ch0_rx_slot2: slot@2 {
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reg = <2>;
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status = "disabled";
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};
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psi5_0_ch0_rx_slot3: slot@3 {
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reg = <3>;
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status = "disabled";
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};
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psi5_0_ch0_rx_slot4: slot@4 {
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reg = <4>;
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status = "disabled";
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};
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psi5_0_ch0_rx_slot5: slot@5 {
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reg = <5>;
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status = "disabled";
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};
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};
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psi5_0_ch1: ch@1 {
1621+
reg = <1>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1623+
#address-cells = <1>;
1624+
#size-cells = <0>;
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status = "disabled";
1626+
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psi5_0_ch1_rx_slot0: slot@0 {
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reg = <0>;
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status = "disabled";
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};
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psi5_0_ch1_rx_slot1: slot@1 {
1633+
reg = <1>;
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status = "disabled";
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};
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psi5_0_ch1_rx_slot2: slot@2 {
1638+
reg = <2>;
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status = "disabled";
1640+
};
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psi5_0_ch1_rx_slot3: slot@3 {
1643+
reg = <3>;
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status = "disabled";
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};
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psi5_0_ch1_rx_slot4: slot@4 {
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reg = <4>;
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status = "disabled";
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};
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psi5_0_ch1_rx_slot5: slot@5 {
1653+
reg = <5>;
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status = "disabled";
1655+
};
1656+
};
1657+
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psi5_0_ch2: ch@2 {
1659+
reg = <2>;
1660+
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1661+
#address-cells = <1>;
1662+
#size-cells = <0>;
1663+
status = "disabled";
1664+
1665+
psi5_0_ch2_rx_slot0: slot@0 {
1666+
reg = <0>;
1667+
status = "disabled";
1668+
};
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psi5_0_ch2_rx_slot1: slot@1 {
1671+
reg = <1>;
1672+
status = "disabled";
1673+
};
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psi5_0_ch2_rx_slot2: slot@2 {
1676+
reg = <2>;
1677+
status = "disabled";
1678+
};
1679+
1680+
psi5_0_ch2_rx_slot3: slot@3 {
1681+
reg = <3>;
1682+
status = "disabled";
1683+
};
1684+
1685+
psi5_0_ch2_rx_slot4: slot@4 {
1686+
reg = <4>;
1687+
status = "disabled";
1688+
};
1689+
1690+
psi5_0_ch2_rx_slot5: slot@5 {
1691+
reg = <5>;
1692+
status = "disabled";
1693+
};
1694+
};
1695+
1696+
psi5_0_ch3: ch@3 {
1697+
reg = <3>;
1698+
interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1699+
#address-cells = <1>;
1700+
#size-cells = <0>;
1701+
status = "disabled";
1702+
1703+
1704+
psi5_0_ch3_rx_slot0: slot@0 {
1705+
reg = <0>;
1706+
status = "disabled";
1707+
};
1708+
1709+
psi5_0_ch3_rx_slot1: slot@1 {
1710+
reg = <1>;
1711+
status = "disabled";
1712+
};
1713+
1714+
psi5_0_ch3_rx_slot2: slot@2 {
1715+
reg = <2>;
1716+
status = "disabled";
1717+
};
1718+
1719+
psi5_0_ch3_rx_slot3: slot@3 {
1720+
reg = <3>;
1721+
status = "disabled";
1722+
};
1723+
1724+
psi5_0_ch3_rx_slot4: slot@4 {
1725+
reg = <4>;
1726+
status = "disabled";
1727+
};
1728+
1729+
psi5_0_ch3_rx_slot5: slot@5 {
1730+
reg = <5>;
1731+
status = "disabled";
1732+
};
1733+
};
1734+
};
1735+
1736+
psi5_1: psi5@421e0000 {
1737+
compatible = "nxp,s32-psi5";
1738+
reg = <0x421e0000 0x1000>;
1739+
#address-cells = <1>;
1740+
#size-cells = <0>;
1741+
status = "disabled";
1742+
1743+
psi5_1_ch0: ch@0 {
1744+
reg = <0>;
1745+
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1746+
#address-cells = <1>;
1747+
#size-cells = <0>;
1748+
status = "disabled";
1749+
1750+
1751+
psi5_1_ch0_rx_slot0: slot@0 {
1752+
reg = <0>;
1753+
status = "disabled";
1754+
};
1755+
1756+
psi5_1_ch0_rx_slot1: slot@1 {
1757+
reg = <1>;
1758+
status = "disabled";
1759+
};
1760+
1761+
psi5_1_ch0_rx_slot2: slot@2 {
1762+
reg = <2>;
1763+
status = "disabled";
1764+
};
1765+
1766+
psi5_1_ch0_rx_slot3: slot@3 {
1767+
reg = <3>;
1768+
status = "disabled";
1769+
};
1770+
1771+
psi5_1_ch0_rx_slot4: slot@4 {
1772+
reg = <4>;
1773+
status = "disabled";
1774+
};
1775+
1776+
psi5_1_ch0_rx_slot5: slot@5 {
1777+
reg = <5>;
1778+
status = "disabled";
1779+
};
1780+
};
1781+
1782+
psi5_1_ch1: ch@1 {
1783+
reg = <1>;
1784+
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1785+
#address-cells = <1>;
1786+
#size-cells = <0>;
1787+
status = "disabled";
1788+
1789+
1790+
psi5_1_ch1_rx_slot0: slot@0 {
1791+
reg = <0>;
1792+
status = "disabled";
1793+
};
1794+
1795+
psi5_1_ch1_rx_slot1: slot@1 {
1796+
reg = <1>;
1797+
status = "disabled";
1798+
};
1799+
1800+
psi5_1_ch1_rx_slot2: slot@2 {
1801+
reg = <2>;
1802+
status = "disabled";
1803+
};
1804+
1805+
psi5_1_ch1_rx_slot3: slot@3 {
1806+
reg = <3>;
1807+
status = "disabled";
1808+
};
1809+
1810+
psi5_1_ch1_rx_slot4: slot@4 {
1811+
reg = <4>;
1812+
status = "disabled";
1813+
};
1814+
1815+
psi5_1_ch1_rx_slot5: slot@5 {
1816+
reg = <5>;
1817+
status = "disabled";
1818+
};
1819+
};
1820+
1821+
psi5_1_ch2: ch@2 {
1822+
reg = <2>;
1823+
interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1824+
#address-cells = <1>;
1825+
#size-cells = <0>;
1826+
status = "disabled";
1827+
1828+
1829+
psi5_1_ch2_rx_slot0: slot@0 {
1830+
reg = <0>;
1831+
status = "disabled";
1832+
};
1833+
1834+
psi5_1_ch2_rx_slot1: slot@1 {
1835+
reg = <1>;
1836+
status = "disabled";
1837+
};
1838+
1839+
psi5_1_ch2_rx_slot2: slot@2 {
1840+
reg = <2>;
1841+
status = "disabled";
1842+
};
1843+
1844+
psi5_1_ch2_rx_slot3: slot@3 {
1845+
reg = <3>;
1846+
status = "disabled";
1847+
};
1848+
1849+
psi5_1_ch2_rx_slot4: slot@4 {
1850+
reg = <4>;
1851+
status = "disabled";
1852+
};
1853+
1854+
psi5_1_ch2_rx_slot5: slot@5 {
1855+
reg = <5>;
1856+
status = "disabled";
1857+
};
1858+
};
1859+
1860+
psi5_1_ch3: ch@3 {
1861+
reg = <3>;
1862+
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1863+
#address-cells = <1>;
1864+
#size-cells = <0>;
1865+
status = "disabled";
1866+
1867+
1868+
psi5_1_ch3_rx_slot0: slot@0 {
1869+
reg = <0>;
1870+
status = "disabled";
1871+
};
1872+
1873+
psi5_1_ch3_rx_slot1: slot@1 {
1874+
reg = <1>;
1875+
status = "disabled";
1876+
};
1877+
1878+
psi5_1_ch3_rx_slot2: slot@2 {
1879+
reg = <2>;
1880+
status = "disabled";
1881+
};
1882+
1883+
psi5_1_ch3_rx_slot3: slot@3 {
1884+
reg = <3>;
1885+
status = "disabled";
1886+
};
1887+
1888+
psi5_1_ch3_rx_slot4: slot@4 {
1889+
reg = <4>;
1890+
status = "disabled";
1891+
};
1892+
1893+
psi5_1_ch3_rx_slot5: slot@5 {
1894+
reg = <5>;
1895+
status = "disabled";
1896+
};
1897+
};
1898+
};
15741899
};
15751900
};

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