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chore(ci): update toolchain to nightly-2025-08-26
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52 files changed

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apps/trivium/src/kreyvium/test.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ use tfhe::{generate_keys, ConfigBuilder, FheBool, FheUint64, FheUint8};
1010
// commit fd6828f68711276c25f55e605935028f5e843f43
1111

1212
fn get_hexadecimal_string_from_lsb_first_stream(a: Vec<bool>) -> String {
13-
assert!(a.len() % 8 == 0);
13+
assert!(a.len().is_multiple_of(8));
1414
let mut hexadecimal: String = "".to_string();
1515
for test in a.chunks(8) {
1616
// Encoding is bytes in LSB order
@@ -63,7 +63,7 @@ fn get_hexadecimal_string_from_lsb_first_stream(a: Vec<bool>) -> String {
6363
}
6464

6565
fn get_hexagonal_string_from_bytes(a: Vec<u8>) -> String {
66-
assert!(a.len() % 8 == 0);
66+
assert!(a.len().is_multiple_of(8));
6767
let mut hexadecimal: String = "".to_string();
6868
for test in a {
6969
hexadecimal.push_str(&format!("{test:02X?}"));

apps/trivium/src/trivium/test.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ use tfhe::{generate_keys, ConfigBuilder, FheBool, FheUint64, FheUint8};
1010
// file testvectors/trivium-80.80.test-vectors
1111

1212
fn get_hexadecimal_string_from_lsb_first_stream(a: Vec<bool>) -> String {
13-
assert!(a.len() % 8 == 0);
13+
assert!(a.len().is_multiple_of(8));
1414
let mut hexadecimal: String = "".to_string();
1515
for test in a.chunks(8) {
1616
// Encoding is bytes in LSB order
@@ -63,7 +63,7 @@ fn get_hexadecimal_string_from_lsb_first_stream(a: Vec<bool>) -> String {
6363
}
6464

6565
fn get_hexagonal_string_from_bytes(a: Vec<u8>) -> String {
66-
assert!(a.len() % 8 == 0);
66+
assert!(a.len().is_multiple_of(8));
6767
let mut hexadecimal: String = "".to_string();
6868
for test in a {
6969
hexadecimal.push_str(&format!("{test:02X?}"));

backends/tfhe-hpu-backend/src/asm/dop/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -438,7 +438,7 @@ pbs!(
438438
},
439439
@1 =>{
440440
|params: &DigitParameters, val| { val >> params.msg_w };
441-
|params: &DigitParameters, _deg| ((1 << (params.carry_w - 1)) - 1);
441+
|params: &DigitParameters, _deg| (1 << (params.carry_w - 1)) - 1;
442442
}
443443
]],
444444
["CmpGtMrg" => 27 [

backends/tfhe-hpu-backend/src/asm/iop/arg.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -331,9 +331,9 @@ impl std::str::FromStr for OperandBundle {
331331
};
332332
Ok(Operand::new(block, base_cid, 1, None))
333333
} else {
334-
return Err(ParsingError::Unmatch(format!(
334+
Err(ParsingError::Unmatch(format!(
335335
"Invalid argument format {s}"
336-
)));
336+
)))
337337
}
338338
})
339339
.collect::<Result<Vec<_>, ParsingError>>()?;

backends/tfhe-hpu-backend/src/ffi/sim/ipc.rs

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,6 @@ use serde::{Deserialize, Serialize};
1111
use crate::entities::HpuPBSParameters;
1212
use crate::ffi::{self, SyncMode};
1313

14-
#[derive(Debug, Serialize, Deserialize)]
15-
pub struct IpcError {}
16-
1714
/// Register request
1815
#[derive(Debug, Serialize, Deserialize)]
1916
pub enum RegisterReq {

backends/tfhe-hpu-backend/src/fw/rtl/mod.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -595,7 +595,7 @@ impl ProgManager for MulsOp {
595595
a.reg_lock()
596596
};
597597

598-
assert!((a.is_in(PosKind::REG) || a.is_cst()));
598+
assert!(a.is_in(PosKind::REG) || a.is_cst());
599599

600600
if !a.is_cst() {
601601
d.reg_alloc_mv();

backends/tfhe-hpu-backend/src/lib.rs

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,6 @@
1+
// Should be removed when we raise MSRV above 1.87
2+
#![allow(clippy::manual_is_multiple_of)]
3+
14
#[cfg(all(feature = "hw-v80", feature = "hw-xrt"))]
25
compile_error! {"hw-v80 and hw-xrt features are used to select the targeted fpga family. Only one fpga family can be used at a time thus these features are mutually exclusive. Only enable one of them at a time. "}
36

mockups/tfhe-hpu-mockup/src/lib.rs

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,6 @@
1+
// Should be removed when we raise MSRV above 1.87
2+
#![allow(clippy::manual_is_multiple_of)]
3+
14
#[cfg(feature = "isc-order-check")]
25
use hpu_asm::dop::ToAsm;
36
use hpu_asm::PbsLut;

mockups/tfhe-hpu-mockup/src/modules/memory/ddr.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ impl DdrMem {
1818
pub(crate) fn alloc_at(&mut self, paddr: u64, size_b: usize) {
1919
// Check that required chunk is in the Ddr range
2020
assert!(
21-
((paddr as usize + size_b) < DDR_SIZE_B),
21+
(paddr as usize + size_b) < DDR_SIZE_B,
2222
"Error: Required chunk @0x{paddr:x}[0x{size_b}] is out of Ddr range [0x0, 0x{DDR_SIZE_B}]"
2323
);
2424

tfhe-fft/src/fft_simd.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
use crate::c64;
2-
use core::{fmt::Debug, marker::PhantomData};
2+
use core::{f64, fmt::Debug, marker::PhantomData};
33

44
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
55
#[derive(Copy, Clone, Debug)]
@@ -276,7 +276,7 @@ pub fn sincospi64(mut a: f64) -> (f64, f64) {
276276
let s = s * t;
277277
r *= s;
278278

279-
let mut s = fma(t, 3.1415926535897931e+0, r);
279+
let mut s = fma(t, f64::consts::PI, r);
280280
// map results according to quadrant
281281

282282
if (i & 2) != 0 {

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