diff --git a/peripherals/uart/README.md b/peripherals/uart/README.md index 23038c61..7e4515cc 100644 --- a/peripherals/uart/README.md +++ b/peripherals/uart/README.md @@ -1,90 +1,311 @@ -# UART ---- - -O periférico realiza a comunicação UART com um baudrate variável (4800 até 38400). Tanto a transmissão quanto a recepção foram implementados e testados no Kit de desenvolvimento DE-10 Lite. - -Descrição de entradas e saídas do componentes: -* clk_in_1M : Clock de entrada que será utilizado para os processos das máquinas de estado Moore e para sinalização de interrupção; -* clk_baud : Clock relacionado à transmissão e recepção de dados; -* csel : Habilita que o dado seja enviado no tx da UART; -* data_in : Dado de 8 bits que será transmitido na UART; -* tx : Transmissor de dados; -* tx_cmp : Sinalizador que o pino tx está sendo utilizado; -* data_out : Dado recebido através do rx da UART; -* rx : Receptor de dados; -* rx_cmp : Sinalizador que o pino rx está recebendo algum dado; -* interrupt : Flag utilizada para sinalizar uma interrupção quando a interrupção para o periférico está habilitada; -* config_all : Vetor de 32 bits utilizados para configuração do periférico - -É importante ressaltar a síntese da PLL para gerar os clocks utilizados: - -- Output clocks: - - clk c0 em 1 MHz - - clk c1 em 0.00960000 MHz (9600 Hz) - -Pode ser configurado o baudrate e o bit de paridade par ou ímpar através dos bits de configuração. - -O periférico feito possui ainda dois pinos que não foram conectados: tx_cmp e rx_cmp. O primeiro indica o término do envio ("tx complete") e o segundo o término da leitura de um byte ("rx complete"). Eles podem ser utilizados no futuro para sincronizar o envio e recepção por pooling. - -## Getting Started (software): - -Para transmissão de um carácter basta utilizar a função UART_write(carácter). - -```C -// Testing UART - Transmission -UART_write('a'); -delay_(1000); // Necessário para não perder sincronia. -``` - -Para recepçao de um carácter utilize a função UART_read(). -```C -// Testint UART - Reception -int x; -x = UART_read(); -OUTBUS = x; -delay_(1000); // Necessário para não perder sincronia. -``` - -O controle do baudrate é feito através de múltiplas divisões do maior baudrate. - -O bit de paridade é criado, quando requisitado, na maquina de estados através da adição de um bit extra a palavra enviada. O numero de 1's é contado através de uma função separada e de acordo com as configurações se define paridade par ou impar. - -Para configurar baudrate e bit de paridade -```C -UART_setup(X, Y); -/* Onde X = 0 baud rate = 38400 - X = 1 baud rate = 19200 - X = 2 baud rate = 9600 - X = 3 baud rate = 4800 - -Onde Y = 0 paridade off - Y = 1 paridade off - Y = 2 paridade impar - Y = 3 paridade par */ -``` - -### Utilizando a interrupção - -Para utilizar interrupções externas e ler um novo dado quando este é recebido, deve-se, primeiramente, habilitar a interrupção da UART implementando trecho de código na aplicação - -```C -UART_interrupt_enable(); - -extern_interrupt_enable(true); -global_interrupt_enable(true); -``` - -Segundo, a função de callback deverá ser implementada e a função ``UART_read()`` deverá ser utilizada para ler os dados recebidos quando ocorrer a interrupção, conforme o bloco de código exemplo abaixo: - -```C -void UART_IRQHandler(void){ - uint8_t data; - - data = UART_read(); - - OUTBUS = data; - HEX0 = data; - HEX1 = data >> 4; -} -``` -Com isso, quando um novo dado é recebido na UART, imprime-se nos display de 7 segmentos e nos LEDs o byte recebido na UART. +# UART +--- + +O periférico realiza a comunicação UART com um baudrate variável (4800 até 38400). Tanto a transmissão quanto a recepção foram implementados e testados no Kit de desenvolvimento DE-10 Lite. + +Descrição de entradas e saídas do componentes: +* clk : Clock de entrada que será utilizado para os processos das máquinas de estado Moore e para sinalização de interrupção; +* rst : Reset o funcionamento da UART; +* clk_baud : Clock relacionado à transmissão e recepção de dados; +* daddress : Endereço dos dados a serem lidos ou escritos; +* ddata_w : Dado de 32 bits para a escrita na memória do periférico; +* ddata_r : Dado de 32 bits para a leitura na memória do periférico; +* d_we : Sinal para habilitar a escrita na memória; +* d_rd : Sinal para habilitar a leitura na memória; +* dcsel : Dado para a seleção do chip; +* dmask : Seleção da máscara para leitura e escrita entre Word,half word e byte; +* tx_out : Saída de transmissão de dados; +* rx_out : Entrada de recepção de dados; +* interrupts : Flag utilizada para sinalizar uma interrupção quando a interrupção para o periférico está habilitada; + +É importante ressaltar a síntese da PLL para gerar os clocks utilizados: + +- Output clocks: + - clk c0 em 1 MHz + - clk c1 em 50 MHz + - clk c2 em 0.03840000 MHz (38400 Hz) + +## Processos referentes a recepção da UART + +Primeiros processos e funções são os de configuração do funcionamento da UART, para essa configuração se tem dois vetores de registradores que tem as informações de controle e configuração desta que são o ``uart_register`` e o ``buffer_register`` onde cada um tem um tamanho de 32 bits ou uma word e traz as informações necessárias para configurar o periférico UART e o seu buffer de recebimento. Assim o primeiro parâmetro que pode ser configurado é a paridade. + +```VHDL + ----------- Function Parity Value ---------- + function parity_val(s : integer; setup : std_logic) return std_logic is + variable temp : std_logic := '0'; + begin + if ((s mod 2) = 0) and (setup = '0') then --Paridade ativada impar + temp := '0'; + elsif ((s mod 2) = 0) and (setup = '1') then --Paridade ativada par + temp := '1'; + elsif ((s mod 2) = 1) and (setup = '0') then --Paridade ativada impar + temp := '1'; + elsif ((s mod 2) = 1) and (setup = '1') then --Paridade ativada par + temp := '0'; + end if; + return temp; + end function parity_val; +``` + +O próximo passo é selecionar o baud rate, o processo que seleciona esse baud rate é demonstrado abaixo. A partir do baud rate selecionado ele pega a frequência de 38400 Hz que é o maior baud rate possível e faz uma divisão caso o baud rate selecionado seja menor que 38400 Hz. + +```VHDL + -------------- Baud Rate Select ------------- + baudselect : process(uart_register(BAUD_RATE_BIT+1 downto BAUD_RATE_BIT), baud_04800, baud_09600, baud_19200, clk_baud) is + begin + case uart_register(BAUD_RATE_BIT + 1 downto BAUD_RATE_BIT) is + when "00" => + baud_ready <= clk_baud; + when "01" => + baud_ready <= baud_19200; + when "10" => + baud_ready <= baud_09600; + when "11" => + baud_ready <= baud_04800; + when others => + baud_ready <= baud_09600; + end case; + end process; +``` + +Com esses dois parâmetros da comunicação serial definidos podemos agora partir para a configuração do buffer que é feita através de somente um processo nesse ele verifica o modo de configuração selecionado e o byte de configuração. + +```VHDL +rx_buffer_config : process(rst, clk) + begin + if rst = '1' then + buffer_mode <= '0'; + buffer_byte <= (others => '0'); + elsif rising_edge(clk) then + case uart_register(IRQ_MODE_BIT) is + when '0' => + buffer_mode <= '0'; + buffer_byte <= buffer_register(NUM_BYTES_IRQ downto NUM_BYTES_IRQ - 7); + when '1' => + buffer_mode <= '1'; + buffer_byte <= buffer_register(BYTE_FINAL downto BYTE_FINAL - 7); + when others => + + end case; + end if; + end process; +``` + +Agora um processo muito importante é o processo de recebimento de um byte e assim poder armazenar o byte completo no buffer. Basicamente o processo verifica se um bit foi recebido e armazena esse bit no from_rx que recebe do start bit e stop bit da informação e incrementa o sinal cnt_rx que representa a posição a ser armazenada. Ao receber um byte completo ele armazena o somente o valor recebido no sinal rx_register que posteriormente irá para o buffer. + +```VHDL + rx_receive : process(rst, baud_ready, byte_received) + variable from_rx : std_logic_vector(9 downto 0); + begin + if rst = '1' then + rx_register <= (others => '0'); + cnt_rx <= 0; + from_rx := (others => '0'); + else + if byte_received = '1' then + if rising_edge(baud_ready) then + from_rx(cnt_rx) := rx_out; + cnt_rx <= cnt_rx + 1; + if cnt_rx = 8 then + rx_register <= from_rx(8 downto 1); + end if; + end if; + else + cnt_rx <= 0; + end if; + end if; + end process; +``` + +Agora temos o processo de armazenamento do buffer e geração da interrupção se esse for o caso.Esse processo a cada ciclo de clock verifica se um byte inteiro foi lido pelo processo anterior se isso for verdadeiro o valor do rx_register é salvo no buffer na posição adequada e de acordo com o modo de funcionamento configurado ele faz a verificação se uma interrupção deve ser gerada ou não pelo hardware. + +```VHDL + rx_buffer_receive : process(rst, clk) + variable cnt_rx_irq : unsigned(2 downto 0); + begin + if rst = '1' then + cnt_rx_buffer <= (others => '0'); + rx_cmp_irq <= '0'; + cnt_rx_irq := (others => '0'); + for i in 0 to 7 loop + buffer_rx(i) <= (others => '0'); + end loop; + elsif rising_edge(clk) then + rx_cmp_irq <= '0'; + if byte_read = '1' then + buffer_rx(to_integer(cnt_rx_buffer)) <= rx_register; + case buffer_mode is + when '0' => if cnt_rx_irq = unsigned(buffer_byte(2 downto 0)) - 1 then + --proc irq handler + cnt_rx_irq := "111"; + rx_cmp_irq <= '1'; + end if; + when '1' => + if rx_register = buffer_byte then + --proc irq handler + rx_cmp_irq <= '1'; + end if; + when others => + end case; + cnt_rx_irq := cnt_rx_irq + 1; + cnt_rx_buffer <= cnt_rx_buffer + 1; + end if; + end if; + end process; +``` +O último processo verifica se uma interrupção foi gerada ou não e caso tenha sido gerada verifica se a recepção de dados esta habilita se a mesma for verdadeira gera a flag de interrupção para o software dar o tratamento devido a informação recebida. + +```VHDL + interrupt_proc : process(clk, rst) + begin + if rst = '1' then + interrupts <= (others => '0'); + elsif rising_edge(clk) then + interrupts(1) <= '0'; + + if input_data = '0' and rx_cmp_irq = '1' and uart_register(IRQ_RX_ENABLE_BIT) = '1' then + interrupts(0) <= '1'; + else + interrupts(0) <= '0'; + end if; + input_data <= rx_cmp_irq; + end if; + end process; +``` + +## Getting Started (software): + +Dando início agora para a parte de software começamos com a transmissão de um carácter para isso basta utilizar a função UART_write(carácter). + +```C +// Testing UART - Transmission +UART_write('a'); +delay_(1000); // Necessário para não perder sincronia. +``` + +Para recepçao de um carácter utilize a função UART_read(). +```C +// Testint UART - Reception +int x; +x = UART_read(); +OUTBUS = x; +delay_(1000); // Necessário para não perder sincronia. +``` + +O controle do baudrate é feito através de múltiplas divisões do maior baudrate. + +O bit de paridade é criado, quando requisitado, na máquina de estados através da adição de um bit extra a palavra enviada. O número de 1's é contado através de uma função separada e de acordo com as configurações se define paridade par ou ímpar. + +Para configurar baudrate e bit de paridade e usado uma enumeração para facilitar +```C +UART_setup(baud_rate_t baud, parity_t parity); + +UART_setup(_38400, NO_PARITY); +/* +Para o baud_rate + +typedef enum baud_rates_config { + _38400, + _19200, + _9600, + _4800 +} baud_rate_t; + +Para o paridade + +typedef enum parity_config { + NO_PARITY, + ODD_PARITY, + EVEN_PARITY +} parity_t; +``` +O recebimento das informações são armazenadas em um buffer circular de 8 bytes, o recebimento de dados no buffer é gerado a cada byte recebido então ele é armazenado no buffer e o recebimento dessa informação pode gerar uma interrupção de acordo com o setup feito para o buffer. Foram implementados dois modos de funcionamento o primeiro modo de setup e gerar uma interrupção por número de bytes recebidos e o segundo modo e se um byte Y for recebido pelo buffer ele gera uma interrupção um exemplo para cada modo é demonstrado abaixo + +```C +Buffer_setup(buffer_t buffer_type, uint8_t config_byte); +Buffer_setup(IRQ_LENGTH, '2'); +/* +Para o modo do buffer + +typedef enum irq_buffer_config { + IRQ_LENGTH, + IRQ_BYTE_FINAL +} buffer_t; +*/ +``` +Nesse exemplo é feita a implementação de um buffer que gera uma interrupção a cada 2 bytes recebidos. O outro modo basta trocar o tipo do buffer e colocar um caractere desejado para gerar uma interrupção ao ser recebido. + +### Utilizando a interrupção + +Para utilizar interrupções externas e ler um certa quantidade de dados quando este é recebido, deve-se, primeiramente, habilitar a interrupção da UART implementando trecho de código na aplicação + +```C +UART_reception_enable(); +UART_interrupt_enable(); + +extern_interrupt_enable(true); +global_interrupt_enable(true); +``` + +Segundo, a função de callback deverá ser implementada, e a função ``UART_buffer_read()`` deverá ser utilizada para ler a quantidade de bytes desejada do buffer quando um certo número de bytes forem recebidos ou um determinado byte que irão gerar a interrupção, a implementação do buffer foi implementado e testado somente com o baud rate de 38400 os outros não foram testados com êxito. A seguir tem o código exemplo: + +```C +volatile uint8_t leitura; +volatile uint8_t addr = 0; +uint8_t data[8]; + +void UART_IRQHandler(void){ + + UART_buffer_read(data, 8); + leitura = 1; + UART_reception_enable(); +} + +int main(){ + + //Valores inicializados com zero + int i = 0; + leitura = 0; + for(i = 0; i <8 ; i++){ + data[i] = 0; + } + // para simulação manter baudrate com 9600 ou alterar testbench + //Recebimento com Buffer testado somente com baudrate de 38400 na placa de desenvolvimento + UART_setup(_9600, NO_PARITY); + Buffer_setup(IRQ_LENGTH, '2'); + UART_reception_enable(); + UART_interrupt_enable(); + + extern_interrupt_enable(true); + global_interrupt_enable(true); + + //Envia os valores lidos do buffer pela variavel data a cada interrupção gerada + while (1){ + if(leitura == 1){ + for(i = 0; i <8 ; i++){ + UART_write(data[i]); + } + leitura = 0; + } + } + + return 0; +} +``` + +Com isso, a cada 2 bytes recebidos a interrupção é gerada, ele envia pela transmissão serial os valores da variável data. Com essa configuração feita podemos agora visualizar a simulação feita para a recepção de dados pela serial e envio pela transmissão quando a interrupção for gerada. + + +Alguns sinais podem ser observados para facilitar a entender o funcionamento da recepção. O primeiro sinal que devemos observar é o ``transmite_byte`` que é a informação transmitida pelo testbench. Outro sinal importante é ``rx_register`` que é o sinal que representa o valor do byte recebido na recepção da UART já o sinal ``RX`` é o recebimento bit a bit da recepção da UART. No modo de recepção acima na simulação é esperado que a cada dois bytes recebidos uma interrupção é gerada, o sinal que gera a interrupção é ``rx_cmp_irq`` quando é gerada uma interrupçãp esse sinal vai para nível lógico alto durante um ciclo de clock e depois vai para nível lógico baixo e quando esse sinal é acionado e se tem a recepção habilitada a flag de ``interrups`` vai para o valor de 01 que gera uma interrupção no hardware. Para acompanhar o funcionamento do buffer é possível observar o sinal ``buffer_mode`` que vai dizer qual o tipo de funcionamento o buffer terá outro sinal importante é o ``buffer_rx`` que mostra os valores recebidos e armazenados pelo buffer, o sinal ``cnt_rx_buffer`` que é a posição que o buffer irá armazenar o byte recebido. O de acordo com o modo definido de funcionamento o sinal ``buffer_byte`` representa o byte configurado para dizer qual o número de bytes a serem recebidos para gerar uma interrupção e assim um tratamento da informação recebida ou o byte a ser recebido para gerar a mesma. Assim na simulação acima é possível ver a variavel ``cnt_rx_irq`` que conta o numero de bytes recebidos e a cada vez que é recebido dois bytes ele gera uma interrupção mudando o valor da flag interrupts que sinaliza para o software realizar o tratamento da informação recebida até então. + +![simulacao_por_tamanho](./imgs/simulacao_buffer_tam_2.jpg) + + Alterando somente a função ``Buffer_setup()`` como a seguir irá gerar uma interrupção a sempre que receber o caracter 'a' + +```C + Buffer_setup(IRQ_BYTE_FINAL, 'a'); +``` + + No modo que gera uma interrupção pelo byte recebido a diferença é que ele para de observar a contagem de bytes e verifica o byte recebido tem o mesmo valor do byte configurado para gerar a interrupção ele gera a mesma, a simulação desse modo de funcionamento é demonstrado abaixo. + + ![simulacao_por_caractere](./imgs/simulacao_buffer_byte_receive_a.jpg) diff --git a/peripherals/uart/coretestbench.vhd b/peripherals/uart/coretestbench.vhd index afb44e8a..eb67aec2 100644 --- a/peripherals/uart/coretestbench.vhd +++ b/peripherals/uart/coretestbench.vhd @@ -1,341 +1,368 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -use work.decoder_types.all; - -entity uart_coretestbench is - generic( - --! Num of 32-bits memory words - IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes - DMEMORY_WORDS : integer := 1024 --!= 2k (512 * 2) bytes - ); - - port( - ----------- SEG7 ------------ - HEX0 : out std_logic_vector(7 downto 0); - HEX1 : out std_logic_vector(7 downto 0); - HEX2 : out std_logic_vector(7 downto 0); - HEX3 : out std_logic_vector(7 downto 0); - HEX4 : out std_logic_vector(7 downto 0); - HEX5 : out std_logic_vector(7 downto 0); - ----------- SW ------------ - LEDR: out std_logic_vector(9 downto 0) - ); - -end entity uart_coretestbench; - -architecture RTL of uart_coretestbench is - -- Clocks and reset - signal clk : std_logic; - signal clk_32x : std_logic; - signal clk_baud : std_logic; - signal rst : std_logic; - - -- Instruction bus and instruction memory - signal address : std_logic_vector(9 downto 0); - signal iaddress : unsigned(15 downto 0); - signal idata : std_logic_vector(31 downto 0); - - -- Data bus - signal daddress : unsigned(31 downto 0); - signal ddata_r : std_logic_vector(31 downto 0); - signal ddata_w : std_logic_vector(31 downto 0); - signal dmask : std_logic_vector(3 downto 0); - signal dcsel : std_logic_vector(1 downto 0); - signal d_we : std_logic := '0'; - signal ddata_r_mem : std_logic_vector(31 downto 0); - signal d_rd : std_logic; - signal d_sig : std_logic; - - -- Modelsim debug signals - signal cpu_state : cpu_state_t; - signal debugString : string(1 to 40) := (others => '0'); - - -- I/O signals - signal interrupts : std_logic_vector(31 downto 0); - signal ddata_r_gpio : std_logic_vector(31 downto 0); - signal gpio_input : std_logic_vector(31 downto 0); - signal gpio_output : std_logic_vector(31 downto 0); - - signal ddata_r_timer : std_logic_vector(31 downto 0); - signal timer_interrupt : std_logic_vector(5 downto 0); - signal ddata_r_periph : std_logic_vector(31 downto 0); - signal ddata_r_sdram : std_logic_vector(31 downto 0); - - signal gpio_interrupts : std_logic_vector(6 downto 0); - signal ddata_r_segments : std_logic_vector(31 downto 0); - signal ddata_r_uart : std_logic_vector(31 downto 0); - signal ddata_r_adc : std_logic_vector(31 downto 0); - signal ddata_r_i2c : std_logic_vector(31 downto 0); - - signal TX : std_logic; - signal RX : std_logic; - signal uart_interrupts : std_logic_vector(1 downto 0); - - -- UART testbench - signal transmit_byte: std_logic_vector(7 downto 0) := x"23"; - signal transmit_frame: std_logic_vector(9 downto 0) := (others => '1'); - signal clk_state: boolean := FALSE; - signal cnt_rx : integer := 0; - -begin - - clock_driver : process - constant period : time := 1000 ns; - begin - clk <= '0'; - wait for period / 2; - clk <= '1'; - wait for period / 2; - end process clock_driver; - - --! Division unit clock - clock_driver_32x : process - constant period : time := 20 ns; - begin - clk_32x <= '0'; - wait for period / 2; - clk_32x <= '1'; - wait for period / 2; - end process clock_driver_32x; - --- clock_driver_baud : process --- constant period : time := 2000 ns; --- begin --- clk_baud <= '0'; --- wait for period / 2; --- clk_baud <= '1'; --- wait for period / 2; --- end process clock_driver_baud; - - clock_baud : process - constant period : time := 2000 ns; - begin - clk_baud <= '0'; - clk_state <= FALSE; - --wait for 2 ns; - wait for period / 2; - clk_baud <= '1'; - clk_state <= TRUE; - --wait for 2 ns; - wait for period / 2; - end process clock_baud; - - - reset : process is - begin - rst <= '1'; - wait for 150 ns; - rst <= '0'; - wait; - end process reset; - - -- Connect gpio data to output hardware - LEDR <= gpio_output(9 downto 0); - - -- Connect input hardware to gpio data - gpio_test: process - begin - gpio_input <= (others => '0'); - wait for 500 us; - - -- Generate a input pulse (External IRQ 0 or pooling) - gpio_input(0) <= '1'; - wait for 1 us; - gpio_input(0) <= '0'; - - -- Generate a input pulse (External IRQ 1 or pooling) - wait for 200 us; - gpio_input(1) <= '1'; - wait for 1 us; - gpio_input(1) <= '0'; - - wait; - end process; - - -- IMem shoud be read from instruction and data buses - -- Not enough RAM ports for instruction bus, data bus and in-circuit programming - instr_mux: entity work.instructionbusmux - port map( - d_rd => d_rd, - dcsel => dcsel, - daddress => daddress, - iaddress => iaddress, - address => address - ); - - -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor - iram_quartus_inst : entity work.iram_quartus - port map( - address => address(9 downto 0), - byteena => "1111", - clock => clk, - data => (others => '0'), - wren => '0', - q => idata - ); - - -- dmemory_address <= daddress; - -- Data Memory RAM - dmem : entity work.dmemory - generic map( - MEMORY_WORDS => DMEMORY_WORDS - ) - port map( - rst => rst, - clk => clk, - data => ddata_w, - address => daddress, - we => d_we, - signal_ext => d_sig, - csel => dcsel(0), - dmask => dmask, - q => ddata_r_mem - ); - - -- Adress space mux ((check sections.ld) -> Data chip select: - -- 0x00000 -> Instruction memory - -- 0x20000 -> Data memory - -- 0x40000 -> Input/Output generic address space - -- 0x60000 -> SDRAM address space - data_bus_mux: entity work.databusmux - port map( - dcsel => dcsel, - idata => idata, - ddata_r_mem => ddata_r_mem, - ddata_r_periph => ddata_r_periph, - ddata_r_sdram => ddata_r_sdram, - ddata_r => ddata_r - ); - - io_data_bus_mux: entity work.iodatabusmux - port map( - daddress => daddress, - ddata_r_gpio => ddata_r_gpio, - ddata_r_segments => ddata_r_segments, - ddata_r_uart => ddata_r_uart, - ddata_r_adc => ddata_r_adc, - ddata_r_i2c => ddata_r_i2c, - ddata_r_timer => ddata_r_timer, - ddata_r_periph => ddata_r_periph - ); - - -- Softcore instatiation - myRiscv : entity work.core - port map( - clk => clk, - rst => rst, - clk_32x => clk_32x, - iaddress => iaddress, - idata => idata, - daddress => daddress, - ddata_r => ddata_r, - ddata_w => ddata_w, - d_we => d_we, - d_rd => d_rd, - d_sig => d_sig, - dcsel => dcsel, - dmask => dmask, - interrupts=>interrupts, - state => cpu_state - ); - - -- Group IRQ signals. - irq_signals: process(timer_interrupt,gpio_interrupts, uart_interrupts) - begin - interrupts <= (others => '0'); - interrupts(24 downto 18) <= gpio_interrupts(6 downto 0); - interrupts(30 downto 25) <= timer_interrupt; - interrupts(31) <= uart_interrupts(0); - end process; - - -- Generic GPIO module instantiation - generic_gpio: entity work.gpio - port map( - clk => clk, - rst => rst, - daddress => daddress, - ddata_w => ddata_w, - ddata_r => ddata_r_gpio, - d_we => d_we, - d_rd => d_rd, - dcsel => dcsel, - dmask => dmask, - input => gpio_input, - output => gpio_output, - gpio_interrupts => gpio_interrupts - ); - - generic_displays : entity work.led_displays - port map( - clk => clk, - rst => rst, - daddress => daddress, - ddata_w => ddata_w, - ddata_r => ddata_r_segments, - d_we => d_we, - d_rd => d_rd, - dcsel => dcsel, - dmask => dmask, - hex0 => HEX0, - hex1 => HEX1, - hex2 => HEX2, - hex3 => HEX3, - hex4 => HEX4, - hex5 => HEX5, - hex6 => open, - hex7 => open - ); - - -- UART module instantiation - generic_uart: entity work.uart - port map( - clk => clk, - rst => rst, - clk_baud => clk_baud, - daddress => daddress, - ddata_w => ddata_w, - ddata_r => ddata_r_uart, - d_we => d_we, - d_rd => d_rd, - dcsel => dcsel, - dmask => dmask, - tx_out => TX, - rx_out => RX, - interrupts => uart_interrupts - ); - - data_transmit_proc: process - begin - RX <= '1'; - wait for 2 us; - wait until clk_state; - RX <= '0'; - for i in 0 to 8 loop - RX <= (transmit_frame(cnt_rx)); - cnt_rx <= cnt_rx + 1; - wait until clk_state; - end loop; - cnt_rx <= 0; - RX <= '1'; - wait for 750 us; - end process; - - transmit_byte <= x"89", x"A5" after 50 us; - transmit_frame <= '1' & transmit_byte & '0'; - - - -- FileOutput DEBUG - debug : entity work.trace_debug - generic map( - MEMORY_WORDS => IMEMORY_WORDS - ) - port map( - pc => iaddress, - data => idata, - inst => debugString - ); - - -end architecture RTL; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.decoder_types.all; + +entity uart_coretestbench is + generic( + --! Num of 32-bits memory words + IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes + DMEMORY_WORDS : integer := 1024 --!= 2k (512 * 2) bytes + ); + + port( + ----------- SEG7 ------------ + HEX0 : out std_logic_vector(7 downto 0); + HEX1 : out std_logic_vector(7 downto 0); + HEX2 : out std_logic_vector(7 downto 0); + HEX3 : out std_logic_vector(7 downto 0); + HEX4 : out std_logic_vector(7 downto 0); + HEX5 : out std_logic_vector(7 downto 0); + ----------- SW ------------ + LEDR : out std_logic_vector(9 downto 0) + ); + +end entity uart_coretestbench; + +architecture RTL of uart_coretestbench is + -- Clocks and reset + signal clk : std_logic; + signal clk_32x : std_logic; + signal clk_baud : std_logic; + signal rst : std_logic; + + -- Instruction bus and instruction memory + signal address : std_logic_vector(9 downto 0); + signal iaddress : unsigned(15 downto 0); + signal idata : std_logic_vector(31 downto 0); + + -- Data bus + signal daddress : unsigned(31 downto 0); + signal ddata_r : std_logic_vector(31 downto 0); + signal ddata_w : std_logic_vector(31 downto 0); + signal dmask : std_logic_vector(3 downto 0); + signal dcsel : std_logic_vector(1 downto 0); + signal d_we : std_logic := '0'; + signal ddata_r_mem : std_logic_vector(31 downto 0); + signal d_rd : std_logic; + signal d_sig : std_logic; + + -- Modelsim debug signals + signal cpu_state : cpu_state_t; + signal debugString : string(1 to 40) := (others => '0'); + + -- I/O signals + signal interrupts : std_logic_vector(31 downto 0); + signal ddata_r_gpio : std_logic_vector(31 downto 0); + signal gpio_input : std_logic_vector(31 downto 0); + signal gpio_output : std_logic_vector(31 downto 0); + + signal ddata_r_timer : std_logic_vector(31 downto 0); + signal timer_interrupt : std_logic_vector(5 downto 0); + signal ddata_r_periph : std_logic_vector(31 downto 0); + signal ddata_r_sdram : std_logic_vector(31 downto 0); + + signal gpio_interrupts : std_logic_vector(6 downto 0); + signal ddata_r_segments : std_logic_vector(31 downto 0); + signal ddata_r_uart : std_logic_vector(31 downto 0); + signal ddata_r_adc : std_logic_vector(31 downto 0); + signal ddata_r_i2c : std_logic_vector(31 downto 0); + signal ddata_r_dig_fil : std_logic_vector(31 downto 0); + signal ddata_r_stepmot : std_logic_vector(31 downto 0); + signal ddata_r_lcd : std_logic_vector(31 downto 0); + signal ddata_r_nn_accelerator : std_logic_vector(31 downto 0); + signal ddata_r_fir_fil : std_logic_vector(31 downto 0); + + signal TX : std_logic; + signal RX : std_logic; + signal uart_interrupts : std_logic_vector(1 downto 0); + + -- UART testbench + signal transmit_byte : std_logic_vector(7 downto 0) := x"23"; + signal transmit_frame : std_logic_vector(9 downto 0) := (others => '1'); + signal clk_state : boolean := FALSE; + signal cnt_rx : integer := 0; + +begin + + clock_driver : process + constant period : time := 1000 ns; + begin + clk <= '0'; + wait for period / 2; + clk <= '1'; + wait for period / 2; + end process clock_driver; + + --! Division unit clock + clock_driver_32x : process + constant period : time := 20 ns; + begin + clk_32x <= '0'; + wait for period / 2; + clk_32x <= '1'; + wait for period / 2; + end process clock_driver_32x; + + -- clock_driver_baud : process + -- constant period : time := 2000 ns; + -- begin + -- clk_baud <= '0'; + -- wait for period / 2; + -- clk_baud <= '1'; + -- wait for period / 2; + -- end process clock_driver_baud; + + clock_baud : process + constant period : time := 26041 ns; + begin + clk_baud <= '0'; + --wait for 2 ns; + wait for period / 2; + clk_baud <= '1'; + --wait for 2 ns; + wait for period / 2; + end process clock_baud; + + clock_baud_9600 : process + constant period : time := 104 us; + begin + clk_state <= FALSE; + --wait for 2 ns; + wait for period / 2; + clk_state <= TRUE; + --wait for 2 ns; + wait for period / 2; + end process clock_baud_9600; + + + reset : process is + begin + rst <= '1'; + wait for 150 ns; + rst <= '0'; + wait; + end process reset; + + -- Connect gpio data to output hardware + LEDR <= gpio_output(9 downto 0); + + -- Connect input hardware to gpio data + gpio_test : process + begin + gpio_input <= (others => '0'); + wait for 500 us; + + -- Generate a input pulse (External IRQ 0 or pooling) + gpio_input(0) <= '1'; + wait for 1 us; + gpio_input(0) <= '0'; + + -- Generate a input pulse (External IRQ 1 or pooling) + wait for 200 us; + gpio_input(1) <= '1'; + wait for 1 us; + gpio_input(1) <= '0'; + + wait; + end process; + + -- IMem shoud be read from instruction and data buses + -- Not enough RAM ports for instruction bus, data bus and in-circuit programming + instr_mux : entity work.instructionbusmux + port map( + d_rd => d_rd, + dcsel => dcsel, + daddress => daddress, + iaddress => iaddress, + address => address + ); + + -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor + iram_quartus_inst : entity work.iram_quartus + port map( + address => address(9 downto 0), + byteena => "1111", + clock => clk, + data => (others => '0'), + wren => '0', + q => idata + ); + + -- dmemory_address <= daddress; + -- Data Memory RAM + dmem : entity work.dmemory + generic map( + MEMORY_WORDS => DMEMORY_WORDS + ) + port map( + rst => rst, + clk => clk, + data => ddata_w, + address => daddress, + we => d_we, + signal_ext => d_sig, + csel => dcsel(0), + dmask => dmask, + q => ddata_r_mem + ); + + -- Adress space mux ((check sections.ld) -> Data chip select: + -- 0x00000 -> Instruction memory + -- 0x20000 -> Data memory + -- 0x40000 -> Input/Output generic address space + -- 0x60000 -> SDRAM address space + data_bus_mux : entity work.databusmux + port map( + dcsel => dcsel, + idata => idata, + ddata_r_mem => ddata_r_mem, + ddata_r_periph => ddata_r_periph, + ddata_r_sdram => ddata_r_sdram, + ddata_r => ddata_r + ); + + io_data_bus_mux : entity work.iodatabusmux + port map( + daddress => daddress, + ddata_r_gpio => ddata_r_gpio, + ddata_r_segments => ddata_r_segments, + ddata_r_uart => ddata_r_uart, + ddata_r_adc => ddata_r_adc, + ddata_r_i2c => ddata_r_i2c, + ddata_r_timer => ddata_r_timer, + ddata_r_periph => ddata_r_periph, + ddata_r_dif_fil => ddata_r_dig_fil, + ddata_r_stepmot => ddata_r_stepmot, + ddata_r_lcd => ddata_r_lcd, + ddata_r_fir_fil => ddata_r_fir_fil, + ddata_r_nn_accelerator => ddata_r_nn_accelerator + ); + + -- Softcore instatiation + myRiscv : entity work.core + port map( + clk => clk, + rst => rst, + clk_32x => clk_32x, + iaddress => iaddress, + idata => idata, + daddress => daddress, + ddata_r => ddata_r, + ddata_w => ddata_w, + d_we => d_we, + d_rd => d_rd, + d_sig => d_sig, + dcsel => dcsel, + dmask => dmask, + interrupts => interrupts, + state => cpu_state + ); + + -- Group IRQ signals. + irq_signals : process(timer_interrupt, gpio_interrupts, uart_interrupts) + begin + interrupts <= (others => '0'); + interrupts(24 downto 18) <= gpio_interrupts(6 downto 0); + interrupts(30 downto 25) <= timer_interrupt; + interrupts(31) <= uart_interrupts(0); + end process; + + -- Generic GPIO module instantiation + generic_gpio : entity work.gpio + port map( + clk => clk, + rst => rst, + daddress => daddress, + ddata_w => ddata_w, + ddata_r => ddata_r_gpio, + d_we => d_we, + d_rd => d_rd, + dcsel => dcsel, + dmask => dmask, + input => gpio_input, + output => gpio_output, + gpio_interrupts => gpio_interrupts + ); + + generic_displays : entity work.led_displays + port map( + clk => clk, + rst => rst, + daddress => daddress, + ddata_w => ddata_w, + ddata_r => ddata_r_segments, + d_we => d_we, + d_rd => d_rd, + dcsel => dcsel, + dmask => dmask, + hex0 => HEX0, + hex1 => HEX1, + hex2 => HEX2, + hex3 => HEX3, + hex4 => HEX4, + hex5 => HEX5, + hex6 => open, + hex7 => open + ); + + -- UART module instantiation + generic_uart : entity work.uart + port map( + clk => clk, + rst => rst, + clk_baud => clk_baud, + daddress => daddress, + ddata_w => ddata_w, + ddata_r => ddata_r_uart, + d_we => d_we, + d_rd => d_rd, + dcsel => dcsel, + dmask => dmask, + tx_out => TX, + rx_out => RX, + interrupts => uart_interrupts + ); + + data_transmit_proc : process + begin + --RX <= '1'; + --wait for 2 us; + --wait until clk_state; + --RX <= '0'; + for i in 0 to 9 loop + RX <= (transmit_frame(i)); + --cnt_rx <= cnt_rx + 1; + wait until clk_state; + end loop; + --cnt_rx <= 0; + RX <= '1'; + wait for 1000 us; + end process; + + process + begin + transmit_byte <= x"A5"; + transmit_frame <= '1' & transmit_byte & '0'; + wait for 2000 us; + transmit_byte <= x"61"; + transmit_frame <= '1' & transmit_byte & '0'; + wait for 2000 us; + transmit_byte <= x"61"; + transmit_frame <= '1' & transmit_byte & '0'; + wait for 2000 us; + end process; + + -- FileOutput DEBUG + debug : entity work.trace_debug + generic map( + MEMORY_WORDS => IMEMORY_WORDS + ) + port map( + pc => iaddress, + data => idata, + inst => debugString + ); + +end architecture RTL; diff --git a/peripherals/uart/pll/pll_quartus.cmp b/peripherals/uart/pll/pll_quartus.cmp index 2cdac8b1..78920b70 100644 --- a/peripherals/uart/pll/pll_quartus.cmp +++ b/peripherals/uart/pll/pll_quartus.cmp @@ -1,26 +1,26 @@ ---Copyright (C) 2020 Intel Corporation. All rights reserved. ---Your use of Intel Corporation's design tools, logic functions ---and other software and tools, and any partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Intel Program License ---Subscription Agreement, the Intel Quartus Prime License Agreement, ---the Intel FPGA IP License Agreement, or other applicable license ---agreement, including, without limitation, that your use is for ---the sole purpose of programming logic devices manufactured by ---Intel and sold by Intel or its authorized distributors. Please ---refer to the applicable agreement for further details, at ---https://fpgasoftware.intel.com/eula. - - -component pll_quartus - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -end component; +--Copyright (C) 2020 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details, at +--https://fpgasoftware.intel.com/eula. + + +component pll_quartus + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/peripherals/uart/pll/pll_quartus.ppf b/peripherals/uart/pll/pll_quartus.ppf index 4d68e582..df1daeb1 100644 --- a/peripherals/uart/pll/pll_quartus.ppf +++ b/peripherals/uart/pll/pll_quartus.ppf @@ -1,12 +1,12 @@ - - - - - - - - - - - - + + + + + + + + + + + + diff --git a/peripherals/uart/pll/pll_quartus.qip b/peripherals/uart/pll/pll_quartus.qip index e586ac52..6e1889f0 100644 --- a/peripherals/uart/pll/pll_quartus.qip +++ b/peripherals/uart/pll/pll_quartus.qip @@ -1,7 +1,7 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "20.1" -set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_quartus.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus_inst.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus.cmp"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus.ppf"] +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "20.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_quartus.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus_inst.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus.ppf"] diff --git a/peripherals/uart/pll/pll_quartus.vhd b/peripherals/uart/pll/pll_quartus.vhd index 0e2e165f..1ec726ef 100644 --- a/peripherals/uart/pll/pll_quartus.vhd +++ b/peripherals/uart/pll/pll_quartus.vhd @@ -1,400 +1,400 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll_quartus.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 20.1.1 Build 720 11/11/2020 SJ Lite Edition --- ************************************************************ - - ---Copyright (C) 2020 Intel Corporation. All rights reserved. ---Your use of Intel Corporation's design tools, logic functions ---and other software and tools, and any partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Intel Program License ---Subscription Agreement, the Intel Quartus Prime License Agreement, ---the Intel FPGA IP License Agreement, or other applicable license ---agreement, including, without limitation, that your use is for ---the sole purpose of programming logic devices manufactured by ---Intel and sold by Intel or its authorized distributors. Please ---refer to the applicable agreement for further details, at ---https://fpgasoftware.intel.com/eula. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll_quartus IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -END pll_quartus; - - -ARCHITECTURE SYN OF pll_quartus IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - self_reset_on_loss_lock : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - locked : OUT STD_LOGIC - ); - END COMPONENT; - -BEGIN - sub_wire6_bv(0 DOWNTO 0) <= "0"; - sub_wire6 <= To_stdlogicvector(sub_wire6_bv); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - locked <= sub_wire3; - sub_wire4 <= inclk0; - sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 50, - clk0_duty_cycle => 50, - clk0_multiply_by => 1, - clk0_phase_shift => "0", - clk1_divide_by => 15625, - clk1_duty_cycle => 50, - clk1_multiply_by => 3, - clk1_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 20000, - intended_device_family => "MAX 10", - lpm_hint => "CBX_MODULE_PREFIX=pll_quartus", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_USED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_UNUSED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - self_reset_on_loss_lock => "OFF", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire5, - clk => sub_wire0, - locked => sub_wire3 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "50" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.009600" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.00960000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_quartus.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "15625" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.cmp TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus_inst.vhd TRUE --- Retrieval info: CBX_MODULE_PREFIX: ON +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll_quartus.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 20.1.1 Build 720 11/11/2020 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 2020 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details, at +--https://fpgasoftware.intel.com/eula. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll_quartus IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll_quartus; + + +ARCHITECTURE SYN OF pll_quartus IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + locked <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 50, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + clk1_divide_by => 15625, + clk1_duty_cycle => 50, + clk1_multiply_by => 3, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "MAX 10", + lpm_hint => "CBX_MODULE_PREFIX=pll_quartus", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire5, + clk => sub_wire0, + locked => sub_wire3 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "50" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.009600" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.00960000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_quartus.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "15625" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus_inst.vhd TRUE +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/peripherals/uart/pll/pll_quartus_inst.vhd b/peripherals/uart/pll/pll_quartus_inst.vhd index bee5a286..e535a2ac 100644 --- a/peripherals/uart/pll/pll_quartus_inst.vhd +++ b/peripherals/uart/pll/pll_quartus_inst.vhd @@ -1,7 +1,7 @@ -pll_quartus_inst : pll_quartus PORT MAP ( - areset => areset_sig, - inclk0 => inclk0_sig, - c0 => c0_sig, - c1 => c1_sig, - locked => locked_sig - ); +pll_quartus_inst : pll_quartus PORT MAP ( + areset => areset_sig, + inclk0 => inclk0_sig, + c0 => c0_sig, + c1 => c1_sig, + locked => locked_sig + ); diff --git a/peripherals/uart/sint/de10_lite/README.md b/peripherals/uart/sint/de10_lite/README.md index 784add65..3de68061 100644 --- a/peripherals/uart/sint/de10_lite/README.md +++ b/peripherals/uart/sint/de10_lite/README.md @@ -1,5 +1,5 @@ -# Projeto Quartus de10_lite - -![](./img/lucas_memory_config_quartus_15_web_edition.jpg) - +# Projeto Quartus de10_lite + +![](./img/lucas_memory_config_quartus_15_web_edition.jpg) + ![](./img/ian_memory_config_quartus_prime.jpg) \ No newline at end of file diff --git a/peripherals/uart/sint/de10_lite/de10_lite.qpf b/peripherals/uart/sint/de10_lite/de10_lite.qpf index 2e37e9d1..41ed5d0e 100644 --- a/peripherals/uart/sint/de10_lite/de10_lite.qpf +++ b/peripherals/uart/sint/de10_lite/de10_lite.qpf @@ -1,31 +1,31 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, the Altera Quartus II License Agreement, -# the Altera MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Altera and sold by Altera or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition -# Date created = 18:49:34 June 20, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "15.0" -DATE = "18:49:34 June 20, 2019" - -# Revisions - -PROJECT_REVISION = "de10_lite" +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition +# Date created = 18:49:34 June 20, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.0" +DATE = "18:49:34 June 20, 2019" + +# Revisions + +PROJECT_REVISION = "de10_lite" diff --git a/peripherals/uart/sint/de10_lite/de10_lite.qsf b/peripherals/uart/sint/de10_lite/de10_lite.qsf index 7d078027..cc154ca6 100644 --- a/peripherals/uart/sint/de10_lite/de10_lite.qsf +++ b/peripherals/uart/sint/de10_lite/de10_lite.qsf @@ -1,245 +1,245 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, the Altera Quartus II License Agreement, -# the Altera MegaCore Function License Agreement, or other -# applicable license agreement, including, without limitation, -# that your use is for the sole purpose of programming logic -# devices manufactured by Altera and sold by Altera or its -# authorized distributors. Please refer to the applicable -# agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 64-Bit -# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition -# Date created = 18:49:34 June 20, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# de10_lite_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "MAX 10" -set_global_assignment -name DEVICE 10M50DAF484C7G -set_global_assignment -name TOP_LEVEL_ENTITY de10_lite -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:49:34 JUNE 20, 2019" -set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name ENABLE_OCT_DONE ON -set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall -set_location_assignment PIN_N5 -to ADC_CLK_10 -set_location_assignment PIN_P11 -to MAX10_CLK1_50 -set_location_assignment PIN_N14 -to MAX10_CLK2_50 -set_location_assignment PIN_U17 -to DRAM_ADDR[0] -set_location_assignment PIN_W19 -to DRAM_ADDR[1] -set_location_assignment PIN_V18 -to DRAM_ADDR[2] -set_location_assignment PIN_U18 -to DRAM_ADDR[3] -set_location_assignment PIN_U19 -to DRAM_ADDR[4] -set_location_assignment PIN_T18 -to DRAM_ADDR[5] -set_location_assignment PIN_T19 -to DRAM_ADDR[6] -set_location_assignment PIN_R18 -to DRAM_ADDR[7] -set_location_assignment PIN_P18 -to DRAM_ADDR[8] -set_location_assignment PIN_P19 -to DRAM_ADDR[9] -set_location_assignment PIN_T20 -to DRAM_ADDR[10] -set_location_assignment PIN_P20 -to DRAM_ADDR[11] -set_location_assignment PIN_R20 -to DRAM_ADDR[12] -set_location_assignment PIN_T21 -to DRAM_BA[0] -set_location_assignment PIN_T22 -to DRAM_BA[1] -set_location_assignment PIN_U21 -to DRAM_CAS_N -set_location_assignment PIN_N22 -to DRAM_CKE -set_location_assignment PIN_L14 -to DRAM_CLK -set_location_assignment PIN_U20 -to DRAM_CS_N -set_location_assignment PIN_Y21 -to DRAM_DQ[0] -set_location_assignment PIN_Y20 -to DRAM_DQ[1] -set_location_assignment PIN_AA22 -to DRAM_DQ[2] -set_location_assignment PIN_AA21 -to DRAM_DQ[3] -set_location_assignment PIN_Y22 -to DRAM_DQ[4] -set_location_assignment PIN_W22 -to DRAM_DQ[5] -set_location_assignment PIN_W20 -to DRAM_DQ[6] -set_location_assignment PIN_V21 -to DRAM_DQ[7] -set_location_assignment PIN_P21 -to DRAM_DQ[8] -set_location_assignment PIN_J22 -to DRAM_DQ[9] -set_location_assignment PIN_H21 -to DRAM_DQ[10] -set_location_assignment PIN_H22 -to DRAM_DQ[11] -set_location_assignment PIN_G22 -to DRAM_DQ[12] -set_location_assignment PIN_G20 -to DRAM_DQ[13] -set_location_assignment PIN_G19 -to DRAM_DQ[14] -set_location_assignment PIN_F22 -to DRAM_DQ[15] -set_location_assignment PIN_V22 -to DRAM_LDQM -set_location_assignment PIN_U22 -to DRAM_RAS_N -set_location_assignment PIN_J21 -to DRAM_UDQM -set_location_assignment PIN_V20 -to DRAM_WE_N -set_location_assignment PIN_C14 -to HEX0[0] -set_location_assignment PIN_E15 -to HEX0[1] -set_location_assignment PIN_C15 -to HEX0[2] -set_location_assignment PIN_C16 -to HEX0[3] -set_location_assignment PIN_E16 -to HEX0[4] -set_location_assignment PIN_D17 -to HEX0[5] -set_location_assignment PIN_C17 -to HEX0[6] -set_location_assignment PIN_D15 -to HEX0[7] -set_location_assignment PIN_C18 -to HEX1[0] -set_location_assignment PIN_D18 -to HEX1[1] -set_location_assignment PIN_E18 -to HEX1[2] -set_location_assignment PIN_B16 -to HEX1[3] -set_location_assignment PIN_A17 -to HEX1[4] -set_location_assignment PIN_A18 -to HEX1[5] -set_location_assignment PIN_B17 -to HEX1[6] -set_location_assignment PIN_A16 -to HEX1[7] -set_location_assignment PIN_B20 -to HEX2[0] -set_location_assignment PIN_A20 -to HEX2[1] -set_location_assignment PIN_B19 -to HEX2[2] -set_location_assignment PIN_A21 -to HEX2[3] -set_location_assignment PIN_B21 -to HEX2[4] -set_location_assignment PIN_C22 -to HEX2[5] -set_location_assignment PIN_B22 -to HEX2[6] -set_location_assignment PIN_A19 -to HEX2[7] -set_location_assignment PIN_F21 -to HEX3[0] -set_location_assignment PIN_E22 -to HEX3[1] -set_location_assignment PIN_E21 -to HEX3[2] -set_location_assignment PIN_C19 -to HEX3[3] -set_location_assignment PIN_C20 -to HEX3[4] -set_location_assignment PIN_D19 -to HEX3[5] -set_location_assignment PIN_E17 -to HEX3[6] -set_location_assignment PIN_D22 -to HEX3[7] -set_location_assignment PIN_F18 -to HEX4[0] -set_location_assignment PIN_E20 -to HEX4[1] -set_location_assignment PIN_E19 -to HEX4[2] -set_location_assignment PIN_J18 -to HEX4[3] -set_location_assignment PIN_H19 -to HEX4[4] -set_location_assignment PIN_F19 -to HEX4[5] -set_location_assignment PIN_F20 -to HEX4[6] -set_location_assignment PIN_F17 -to HEX4[7] -set_location_assignment PIN_J20 -to HEX5[0] -set_location_assignment PIN_K20 -to HEX5[1] -set_location_assignment PIN_L18 -to HEX5[2] -set_location_assignment PIN_N18 -to HEX5[3] -set_location_assignment PIN_M20 -to HEX5[4] -set_location_assignment PIN_N19 -to HEX5[5] -set_location_assignment PIN_N20 -to HEX5[6] -set_location_assignment PIN_L19 -to HEX5[7] -set_location_assignment PIN_B8 -to KEY[0] -set_location_assignment PIN_A7 -to KEY[1] -set_location_assignment PIN_A8 -to LEDR[0] -set_location_assignment PIN_A9 -to LEDR[1] -set_location_assignment PIN_A10 -to LEDR[2] -set_location_assignment PIN_B10 -to LEDR[3] -set_location_assignment PIN_D13 -to LEDR[4] -set_location_assignment PIN_C13 -to LEDR[5] -set_location_assignment PIN_E14 -to LEDR[6] -set_location_assignment PIN_D14 -to LEDR[7] -set_location_assignment PIN_A11 -to LEDR[8] -set_location_assignment PIN_B11 -to LEDR[9] -set_location_assignment PIN_C10 -to SW[0] -set_location_assignment PIN_C11 -to SW[1] -set_location_assignment PIN_D12 -to SW[2] -set_location_assignment PIN_C12 -to SW[3] -set_location_assignment PIN_A12 -to SW[4] -set_location_assignment PIN_B12 -to SW[5] -set_location_assignment PIN_A13 -to SW[6] -set_location_assignment PIN_A14 -to SW[7] -set_location_assignment PIN_B14 -to SW[8] -set_location_assignment PIN_F15 -to SW[9] -set_location_assignment PIN_P1 -to VGA_B[0] -set_location_assignment PIN_T1 -to VGA_B[1] -set_location_assignment PIN_P4 -to VGA_B[2] -set_location_assignment PIN_N2 -to VGA_B[3] -set_location_assignment PIN_W1 -to VGA_G[0] -set_location_assignment PIN_T2 -to VGA_G[1] -set_location_assignment PIN_R2 -to VGA_G[2] -set_location_assignment PIN_R1 -to VGA_G[3] -set_location_assignment PIN_N3 -to VGA_HS -set_location_assignment PIN_AA1 -to VGA_R[0] -set_location_assignment PIN_V1 -to VGA_R[1] -set_location_assignment PIN_Y2 -to VGA_R[2] -set_location_assignment PIN_Y1 -to VGA_R[3] -set_location_assignment PIN_N1 -to VGA_VS -set_location_assignment PIN_AB16 -to GSENSOR_CS_N -set_location_assignment PIN_Y14 -to GSENSOR_INT[1] -set_location_assignment PIN_Y13 -to GSENSOR_INT[2] -set_location_assignment PIN_AB15 -to GSENSOR_SCLK -set_location_assignment PIN_V11 -to GSENSOR_SDI -set_location_assignment PIN_V12 -to GSENSOR_SDO -set_location_assignment PIN_AB5 -to ARDUINO_IO[0] -set_location_assignment PIN_AB6 -to ARDUINO_IO[1] -set_location_assignment PIN_AB7 -to ARDUINO_IO[2] -set_location_assignment PIN_AB8 -to ARDUINO_IO[3] -set_location_assignment PIN_AB9 -to ARDUINO_IO[4] -set_location_assignment PIN_Y10 -to ARDUINO_IO[5] -set_location_assignment PIN_AA11 -to ARDUINO_IO[6] -set_location_assignment PIN_AA12 -to ARDUINO_IO[7] -set_location_assignment PIN_AB17 -to ARDUINO_IO[8] -set_location_assignment PIN_AA17 -to ARDUINO_IO[9] -set_location_assignment PIN_AB19 -to ARDUINO_IO[10] -set_location_assignment PIN_AA19 -to ARDUINO_IO[11] -set_location_assignment PIN_Y19 -to ARDUINO_IO[12] -set_location_assignment PIN_AB20 -to ARDUINO_IO[13] -set_location_assignment PIN_AB21 -to ARDUINO_IO[14] -set_location_assignment PIN_AA20 -to ARDUINO_IO[15] -set_location_assignment PIN_F16 -to ARDUINO_RESET_N -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" - -set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON -set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name VHDL_FILE ../../uart.vhd -set_global_assignment -name VHDL_FILE de10_lite.vhd -set_global_assignment -name VHDL_FILE ../../../gpio/led_displays.vhd -set_global_assignment -name VHDL_FILE ../../../gpio/gpio.vhd -set_global_assignment -name VHDL_FILE ../../../../alu/m/quick_clz.vhd -set_global_assignment -name VHDL_FILE ../../../../alu/m/division_functions.vhd -set_global_assignment -name VHDL_FILE ../../../../alu/m/quick_naive.vhd -set_global_assignment -name VHDL_FILE ../../../../memory/periphdatabusmux.vhd -set_global_assignment -name VHDL_FILE ../../../timer/Timer.vhd -set_global_assignment -name VHDL_FILE ../../../../core/csr.vhd -set_global_assignment -name VHDL_FILE ../../../../registers/register_file.vhd -set_global_assignment -name VHDL_FILE ../../../../memory/instructionbusmux.vhd -set_global_assignment -name VHDL_FILE ../../../../memory/iodatabusmux.vhd -set_global_assignment -name VHDL_FILE ../../../../memory/databusmux.vhd -set_global_assignment -name QIP_FILE ../../../../memory/iram_quartus.qip -set_global_assignment -name VHDL_FILE ../../../../memory/dmemory.vhd -set_global_assignment -name VHDL_FILE ../../../../decoder/iregister.vhd -set_global_assignment -name VHDL_FILE ../../../../decoder/decoder_types.vhd -set_global_assignment -name VHDL_FILE ../../../../decoder/decoder.vhd -set_global_assignment -name VHDL_FILE ../../../../core/core.vhd -set_global_assignment -name VHDL_FILE ../../../../alu/m/M_types.vhd -set_global_assignment -name VHDL_FILE ../../../../alu/m/M.vhd -set_global_assignment -name VHDL_FILE ../../../../alu/alu_types.vhd -set_global_assignment -name VHDL_FILE ../../../../alu/alu.vhd -set_global_assignment -name QIP_FILE pll.qip -set_global_assignment -name SOURCE_FILE db/de10_lite.cmp.rdb +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition +# Date created = 18:49:34 June 20, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# de10_lite_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:49:34 JUNE 20, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name ENABLE_OCT_DONE ON +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" + +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON +set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_FILE ../../uart.vhd +set_global_assignment -name VHDL_FILE de10_lite.vhd +set_global_assignment -name VHDL_FILE ../../../gpio/led_displays.vhd +set_global_assignment -name VHDL_FILE ../../../gpio/gpio.vhd +set_global_assignment -name VHDL_FILE ../../../../alu/m/quick_clz.vhd +set_global_assignment -name VHDL_FILE ../../../../alu/m/division_functions.vhd +set_global_assignment -name VHDL_FILE ../../../../alu/m/quick_naive.vhd +set_global_assignment -name VHDL_FILE ../../../../memory/periphdatabusmux.vhd +set_global_assignment -name VHDL_FILE ../../../timer/Timer.vhd +set_global_assignment -name VHDL_FILE ../../../../core/csr.vhd +set_global_assignment -name VHDL_FILE ../../../../registers/register_file.vhd +set_global_assignment -name VHDL_FILE ../../../../memory/instructionbusmux.vhd +set_global_assignment -name VHDL_FILE ../../../../memory/iodatabusmux.vhd +set_global_assignment -name VHDL_FILE ../../../../memory/databusmux.vhd +set_global_assignment -name QIP_FILE ../../../../memory/iram_quartus.qip +set_global_assignment -name VHDL_FILE ../../../../memory/dmemory.vhd +set_global_assignment -name VHDL_FILE ../../../../decoder/iregister.vhd +set_global_assignment -name VHDL_FILE ../../../../decoder/decoder_types.vhd +set_global_assignment -name VHDL_FILE ../../../../decoder/decoder.vhd +set_global_assignment -name VHDL_FILE ../../../../core/core.vhd +set_global_assignment -name VHDL_FILE ../../../../alu/m/M_types.vhd +set_global_assignment -name VHDL_FILE ../../../../alu/m/M.vhd +set_global_assignment -name VHDL_FILE ../../../../alu/alu_types.vhd +set_global_assignment -name VHDL_FILE ../../../../alu/alu.vhd +set_global_assignment -name QIP_FILE pll.qip +set_global_assignment -name SOURCE_FILE db/de10_lite.cmp.rdb set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/peripherals/uart/sint/de10_lite/de10_lite.vhd b/peripherals/uart/sint/de10_lite/de10_lite.vhd index fdbbdaa1..ae9dfb5e 100644 --- a/peripherals/uart/sint/de10_lite/de10_lite.vhd +++ b/peripherals/uart/sint/de10_lite/de10_lite.vhd @@ -1,318 +1,328 @@ -------------------------------------------------------------------- --- Name : de0_lite.vhd --- Author : --- Version : 0.1 --- Copyright : Departamento de Eletrônica, Florianópolis, IFSC --- Description : Projeto base DE10-Lite -------------------------------------------------------------------- -LIBRARY ieee; -USE IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -use work.decoder_types.all; - -entity de10_lite is - generic ( - --! Num of 32-bits memory words - IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes - DMEMORY_WORDS : integer := 1024 --!= 2k (512 * 2) bytes - ); - port ( - ---------- CLOCK ---------- - ADC_CLK_10: in std_logic; - MAX10_CLK1_50: in std_logic; - MAX10_CLK2_50: in std_logic; - - ----------- SDRAM ------------ - DRAM_ADDR: out std_logic_vector (12 downto 0); - DRAM_BA: out std_logic_vector (1 downto 0); - DRAM_CAS_N: out std_logic; - DRAM_CKE: out std_logic; - DRAM_CLK: out std_logic; - DRAM_CS_N: out std_logic; - DRAM_DQ: inout std_logic_vector(15 downto 0); - DRAM_LDQM: out std_logic; - DRAM_RAS_N: out std_logic; - DRAM_UDQM: out std_logic; - DRAM_WE_N: out std_logic; - - ----------- SEG7 ------------ - HEX0: out std_logic_vector(7 downto 0); - HEX1: out std_logic_vector(7 downto 0); - HEX2: out std_logic_vector(7 downto 0); - HEX3: out std_logic_vector(7 downto 0); - HEX4: out std_logic_vector(7 downto 0); - HEX5: out std_logic_vector(7 downto 0); - - ----------- KEY ------------ - KEY: in std_logic_vector(1 downto 0); - - ----------- LED ------------ - LEDR: out std_logic_vector(9 downto 0); - - ----------- SW ------------ - SW: in std_logic_vector(9 downto 0); - - ----------- VGA ------------ - VGA_B: out std_logic_vector(3 downto 0); - VGA_G: out std_logic_vector(3 downto 0); - VGA_HS: out std_logic; - VGA_R: out std_logic_vector(3 downto 0); - VGA_VS: out std_logic; - - ----------- Accelerometer ------------ - GSENSOR_CS_N: out std_logic; - GSENSOR_INT: in std_logic_vector(2 downto 1); - GSENSOR_SCLK: out std_logic; - GSENSOR_SDI: inout std_logic; - GSENSOR_SDO: inout std_logic; - - ----------- Arduino ------------ - ARDUINO_IO: inout std_logic_vector(15 downto 0); - ARDUINO_RESET_N: inout std_logic - ); -end entity; - - - -architecture rtl of de10_lite is - -- Clocks and reset - signal clk : std_logic; - signal rst : std_logic; - signal clk_50MHz : std_logic; - signal clk_baud : std_logic; --! 38400 Hz - -- PLL signals - signal locked_sig : std_logic; - - -- Instruction bus signals - signal idata : std_logic_vector(31 downto 0); - signal iaddress : unsigned(15 downto 0); - signal address : std_logic_vector (9 downto 0); - - -- Data bus signals - signal daddress : unsigned(31 downto 0); - signal ddata_r : std_logic_vector(31 downto 0); - signal ddata_w : std_logic_vector(31 downto 0); - signal ddata_r_mem : std_logic_vector(31 downto 0); - signal dmask : std_logic_vector(3 downto 0); - signal dcsel : std_logic_vector(1 downto 0); - signal d_we : std_logic; - signal d_rd : std_logic; - signal d_sig : std_logic; - - -- SDRAM signals - signal ddata_r_sdram : std_logic_vector(31 downto 0); - - -- CPU state signals - signal state : cpu_state_t; - signal div_result : std_logic_vector(31 downto 0); - - -- I/O signals - signal gpio_input : std_logic_vector(31 downto 0); - signal gpio_output : std_logic_vector(31 downto 0); - - -- Peripheral data signals - signal ddata_r_gpio : std_logic_vector(31 downto 0); - signal ddata_r_timer : std_logic_vector(31 downto 0); - signal ddata_r_periph : std_logic_vector(31 downto 0); - signal ddata_r_segments : std_logic_vector(31 downto 0); - signal ddata_r_uart : std_logic_vector(31 downto 0); - signal ddata_r_adc : std_logic_vector(31 downto 0); - signal ddata_r_i2c : std_logic_vector(31 downto 0); - - -- Interrupt Signals - signal interrupts : std_logic_vector(31 downto 0); - signal gpio_interrupts : std_logic_vector(6 downto 0); - signal timer_interrupt : std_logic_vector(5 downto 0); - signal uart_interrupts : std_logic_vector(1 downto 0); - - -- I/O signals - signal input_in : std_logic_vector(31 downto 0); - - -begin - - -- Reset - rst <= SW(9); - LEDR(9) <= SW(9); - - -- Clocks - pll_inst : entity work.pll - port map( - areset => '0', - inclk0 => MAX10_CLK1_50, - c0 => clk, - c1 => clk_50MHz, - c2 => clk_baud, - locked => locked_sig - ); - - -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor - iram_quartus_inst: entity work.iram_quartus - port map( - address => address, - byteena => "1111", - clock => clk, - data => (others => '0'), - wren => '0', - q => idata - ); - - -- IMem shoud be read from instruction and data buses - -- Not enough RAM ports for instruction bus, data bus and in-circuit programming - instr_mux: entity work.instructionbusmux - port map( - d_rd => d_rd, - dcsel => dcsel, - daddress => daddress, - iaddress => iaddress, - address => address - ); - - -- Data Memory RAM - dmem: entity work.dmemory - generic map( - MEMORY_WORDS => DMEMORY_WORDS - ) - port map( - rst => rst, - clk => clk, - data => ddata_w, - address => daddress, - we => d_we, - csel => dcsel(0), - dmask => dmask, - signal_ext => d_sig, - q => ddata_r_mem - ); - - -- Adress space mux ((check sections.ld) -> Data chip select: - -- 0x00000 -> Instruction memory - -- 0x20000 -> Data memory - -- 0x40000 -> Input/Output generic address space - -- ( ... ) -> ( ... ) - datamux: entity work.databusmux - port map( - dcsel => dcsel, - idata => idata, - ddata_r_mem => ddata_r_mem, - ddata_r_periph => ddata_r_periph, - ddata_r_sdram =>ddata_r_sdram, - ddata_r => ddata_r - ); - - -- Softcore instatiation - myRiscv : entity work.core - port map( - clk => clk, - rst => rst, - clk_32x => clk_50MHz, - iaddress => iaddress, - idata => idata, - daddress => daddress, - ddata_r => ddata_r, - ddata_w => ddata_w, - d_we => d_we, - d_rd => d_rd, - d_sig => d_sig, - dcsel => dcsel, - dmask => dmask, - interrupts=>interrupts, - state => state - ); - - -- IRQ lines - interrupts(24 downto 18) <= gpio_interrupts(6 downto 0); - interrupts(30 downto 25) <= timer_interrupt; - interrupts(31) <= uart_interrupts(0); - - io_data_bus_mux: entity work.iodatabusmux - port map( - daddress => daddress, - ddata_r_gpio => ddata_r_gpio, - ddata_r_segments => ddata_r_segments, - ddata_r_uart => ddata_r_uart, - ddata_r_adc => ddata_r_adc, - ddata_r_i2c => ddata_r_i2c, - ddata_r_timer => ddata_r_timer, - ddata_r_periph => ddata_r_periph - ); - - generic_gpio: entity work.gpio - port map( - clk => clk, - rst => rst, - daddress => daddress, - ddata_w => ddata_w, - ddata_r => ddata_r_gpio, - d_we => d_we, - d_rd => d_rd, - dcsel => dcsel, - dmask => dmask, - input => gpio_input, - output => gpio_output, - gpio_interrupts => gpio_interrupts - ); - - -- Timer instantiation - timer : entity work.Timer - generic map( - prescaler_size => 16, - compare_size => 32 - ) - port map( - clock => clk, - reset => rst, - daddress => daddress, - ddata_w => ddata_w, - ddata_r => ddata_r_timer, - d_we => d_we, - d_rd => d_rd, - dcsel => dcsel, - dmask => dmask, - timer_interrupt => timer_interrupt - ); - - generic_displays : entity work.led_displays - port map( - clk => clk, - rst => rst, - daddress => daddress, - ddata_w => ddata_w, - ddata_r => ddata_r_segments, - d_we => d_we, - d_rd => d_rd, - dcsel => dcsel, - dmask => dmask, - hex0 => HEX0, - hex1 => HEX1, - hex2 => HEX2, - hex3 => HEX3, - hex4 => HEX4, - hex5 => HEX5, - hex6 => open, - hex7 => open - ); - - uart_module: entity work.uart - port map( - clk => clk, - rst => rst, - clk_baud => clk_baud, - daddress => daddress, - ddata_w => ddata_w, - ddata_r => ddata_r_uart, - d_we => d_we, - d_rd => d_rd, - dcsel => dcsel, - dmask => dmask, - tx_out => ARDUINO_IO(1), - rx_out => ARDUINO_IO(0), - interrupts => uart_interrupts - ); - - -- Connect input hardware to gpio data - gpio_input(3 downto 0) <= SW(3 downto 0); - LEDR(7 downto 0) <= gpio_output(7 downto 0); - -end; +------------------------------------------------------------------- +-- Name : de0_lite.vhd +-- Author : +-- Version : 0.1 +-- Copyright : Departamento de Eletrônica, Florianópolis, IFSC +-- Description : Projeto base DE10-Lite +------------------------------------------------------------------- +LIBRARY ieee; +USE IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +use work.decoder_types.all; + +entity de10_lite is + generic ( + --! Num of 32-bits memory words + IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes + DMEMORY_WORDS : integer := 1024 --!= 2k (512 * 2) bytes + ); + port ( + ---------- CLOCK ---------- + ADC_CLK_10: in std_logic; + MAX10_CLK1_50: in std_logic; + MAX10_CLK2_50: in std_logic; + + ----------- SDRAM ------------ + DRAM_ADDR: out std_logic_vector (12 downto 0); + DRAM_BA: out std_logic_vector (1 downto 0); + DRAM_CAS_N: out std_logic; + DRAM_CKE: out std_logic; + DRAM_CLK: out std_logic; + DRAM_CS_N: out std_logic; + DRAM_DQ: inout std_logic_vector(15 downto 0); + DRAM_LDQM: out std_logic; + DRAM_RAS_N: out std_logic; + DRAM_UDQM: out std_logic; + DRAM_WE_N: out std_logic; + + ----------- SEG7 ------------ + HEX0: out std_logic_vector(7 downto 0); + HEX1: out std_logic_vector(7 downto 0); + HEX2: out std_logic_vector(7 downto 0); + HEX3: out std_logic_vector(7 downto 0); + HEX4: out std_logic_vector(7 downto 0); + HEX5: out std_logic_vector(7 downto 0); + + ----------- KEY ------------ + KEY: in std_logic_vector(1 downto 0); + + ----------- LED ------------ + LEDR: out std_logic_vector(9 downto 0); + + ----------- SW ------------ + SW: in std_logic_vector(9 downto 0); + + ----------- VGA ------------ + VGA_B: out std_logic_vector(3 downto 0); + VGA_G: out std_logic_vector(3 downto 0); + VGA_HS: out std_logic; + VGA_R: out std_logic_vector(3 downto 0); + VGA_VS: out std_logic; + + ----------- Accelerometer ------------ + GSENSOR_CS_N: out std_logic; + GSENSOR_INT: in std_logic_vector(2 downto 1); + GSENSOR_SCLK: out std_logic; + GSENSOR_SDI: inout std_logic; + GSENSOR_SDO: inout std_logic; + + ----------- Arduino ------------ + ARDUINO_IO: inout std_logic_vector(15 downto 0); + ARDUINO_RESET_N: inout std_logic + ); +end entity; + + + +architecture rtl of de10_lite is + -- Clocks and reset + signal clk : std_logic; + signal rst : std_logic; + signal clk_50MHz : std_logic; + signal clk_baud : std_logic; --! 38400 Hz + -- PLL signals + signal locked_sig : std_logic; + + -- Instruction bus signals + signal idata : std_logic_vector(31 downto 0); + signal iaddress : unsigned(15 downto 0); + signal address : std_logic_vector (9 downto 0); + + -- Data bus signals + signal daddress : unsigned(31 downto 0); + signal ddata_r : std_logic_vector(31 downto 0); + signal ddata_w : std_logic_vector(31 downto 0); + signal ddata_r_mem : std_logic_vector(31 downto 0); + signal dmask : std_logic_vector(3 downto 0); + signal dcsel : std_logic_vector(1 downto 0); + signal d_we : std_logic; + signal d_rd : std_logic; + signal d_sig : std_logic; + + -- SDRAM signals + signal ddata_r_sdram : std_logic_vector(31 downto 0); + + -- CPU state signals + signal state : cpu_state_t; + signal div_result : std_logic_vector(31 downto 0); + + -- I/O signals + signal gpio_input : std_logic_vector(31 downto 0); + signal gpio_output : std_logic_vector(31 downto 0); + + -- Peripheral data signals + signal ddata_r_gpio : std_logic_vector(31 downto 0); + signal ddata_r_timer : std_logic_vector(31 downto 0); + signal ddata_r_periph : std_logic_vector(31 downto 0); + signal ddata_r_segments : std_logic_vector(31 downto 0); + signal ddata_r_uart : std_logic_vector(31 downto 0); + signal ddata_r_adc : std_logic_vector(31 downto 0); + signal ddata_r_i2c : std_logic_vector(31 downto 0); + signal ddata_r_dig_fil : std_logic_vector(31 downto 0); + signal ddata_r_stepmot : std_logic_vector(31 downto 0); + signal ddata_r_lcd : std_logic_vector(31 downto 0); + signal ddata_r_nn_accelerator : std_logic_vector(31 downto 0); + signal ddata_r_fir_fil : std_logic_vector(31 downto 0); + + -- Interrupt Signals + signal interrupts : std_logic_vector(31 downto 0); + signal gpio_interrupts : std_logic_vector(6 downto 0); + signal timer_interrupt : std_logic_vector(5 downto 0); + signal uart_interrupts : std_logic_vector(1 downto 0); + + -- I/O signals + signal input_in : std_logic_vector(31 downto 0); + + +begin + + -- Reset + rst <= SW(9); + LEDR(9) <= SW(9); + + -- Clocks + pll_inst : entity work.pll + port map( + areset => '0', + inclk0 => MAX10_CLK1_50, + c0 => clk, + c1 => clk_50MHz, + c2 => clk_baud, + locked => locked_sig + ); + + -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor + iram_quartus_inst: entity work.iram_quartus + port map( + address => address, + byteena => "1111", + clock => clk, + data => (others => '0'), + wren => '0', + q => idata + ); + + -- IMem shoud be read from instruction and data buses + -- Not enough RAM ports for instruction bus, data bus and in-circuit programming + instr_mux: entity work.instructionbusmux + port map( + d_rd => d_rd, + dcsel => dcsel, + daddress => daddress, + iaddress => iaddress, + address => address + ); + + -- Data Memory RAM + dmem: entity work.dmemory + generic map( + MEMORY_WORDS => DMEMORY_WORDS + ) + port map( + rst => rst, + clk => clk, + data => ddata_w, + address => daddress, + we => d_we, + csel => dcsel(0), + dmask => dmask, + signal_ext => d_sig, + q => ddata_r_mem + ); + + -- Adress space mux ((check sections.ld) -> Data chip select: + -- 0x00000 -> Instruction memory + -- 0x20000 -> Data memory + -- 0x40000 -> Input/Output generic address space + -- ( ... ) -> ( ... ) + datamux: entity work.databusmux + port map( + dcsel => dcsel, + idata => idata, + ddata_r_mem => ddata_r_mem, + ddata_r_periph => ddata_r_periph, + ddata_r_sdram =>ddata_r_sdram, + ddata_r => ddata_r + ); + + -- Softcore instatiation + myRiscv : entity work.core + port map( + clk => clk, + rst => rst, + clk_32x => clk_50MHz, + iaddress => iaddress, + idata => idata, + daddress => daddress, + ddata_r => ddata_r, + ddata_w => ddata_w, + d_we => d_we, + d_rd => d_rd, + d_sig => d_sig, + dcsel => dcsel, + dmask => dmask, + interrupts=>interrupts, + state => state + ); + + -- IRQ lines + interrupts(24 downto 18) <= gpio_interrupts(6 downto 0); + interrupts(30 downto 25) <= timer_interrupt; + interrupts(31) <= uart_interrupts(0); + + io_data_bus_mux: entity work.iodatabusmux + port map( + daddress => daddress, + ddata_r_gpio => ddata_r_gpio, + ddata_r_segments => ddata_r_segments, + ddata_r_uart => ddata_r_uart, + ddata_r_adc => ddata_r_adc, + ddata_r_i2c => ddata_r_i2c, + ddata_r_timer => ddata_r_timer, + ddata_r_periph => ddata_r_periph, + ddata_r_dif_fil => ddata_r_dig_fil, + ddata_r_stepmot => ddata_r_stepmot, + ddata_r_lcd => ddata_r_lcd, + ddata_r_fir_fil => ddata_r_fir_fil, + ddata_r_nn_accelerator => ddata_r_nn_accelerator + ); + + generic_gpio: entity work.gpio + port map( + clk => clk, + rst => rst, + daddress => daddress, + ddata_w => ddata_w, + ddata_r => ddata_r_gpio, + d_we => d_we, + d_rd => d_rd, + dcsel => dcsel, + dmask => dmask, + input => gpio_input, + output => gpio_output, + gpio_interrupts => gpio_interrupts + ); + + -- Timer instantiation + timer : entity work.Timer + generic map( + prescaler_size => 16, + compare_size => 32 + ) + port map( + clock => clk, + reset => rst, + daddress => daddress, + ddata_w => ddata_w, + ddata_r => ddata_r_timer, + d_we => d_we, + d_rd => d_rd, + dcsel => dcsel, + dmask => dmask, + timer_interrupt => timer_interrupt + ); + + generic_displays : entity work.led_displays + port map( + clk => clk, + rst => rst, + daddress => daddress, + ddata_w => ddata_w, + ddata_r => ddata_r_segments, + d_we => d_we, + d_rd => d_rd, + dcsel => dcsel, + dmask => dmask, + hex0 => HEX0, + hex1 => HEX1, + hex2 => HEX2, + hex3 => HEX3, + hex4 => HEX4, + hex5 => HEX5, + hex6 => open, + hex7 => open + ); + + uart_module: entity work.uart + port map( + clk => clk, + rst => rst, + clk_baud => clk_baud, + daddress => daddress, + ddata_w => ddata_w, + ddata_r => ddata_r_uart, + d_we => d_we, + d_rd => d_rd, + dcsel => dcsel, + dmask => dmask, + tx_out => ARDUINO_IO(1), + rx_out => ARDUINO_IO(0), + interrupts => uart_interrupts + ); + + -- Connect input hardware to gpio data + gpio_input(3 downto 0) <= SW(3 downto 0); + LEDR(7 downto 0) <= gpio_output(7 downto 0); + +end; diff --git a/peripherals/uart/sint/de10_lite/pll.ppf b/peripherals/uart/sint/de10_lite/pll.ppf index 87d735b4..d1df02de 100644 --- a/peripherals/uart/sint/de10_lite/pll.ppf +++ b/peripherals/uart/sint/de10_lite/pll.ppf @@ -1,13 +1,13 @@ - - - - - - - - - - - - - + + + + + + + + + + + + + diff --git a/peripherals/uart/sint/de10_lite/pll.qip b/peripherals/uart/sint/de10_lite/pll.qip index c3650c47..d3d6b9d6 100644 --- a/peripherals/uart/sint/de10_lite/pll.qip +++ b/peripherals/uart/sint/de10_lite/pll.qip @@ -1,5 +1,5 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "20.1" -set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" -set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "22.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/peripherals/uart/sint/de10_lite/pll.vhd b/peripherals/uart/sint/de10_lite/pll.vhd index 674e8bad..27040de2 100644 --- a/peripherals/uart/sint/de10_lite/pll.vhd +++ b/peripherals/uart/sint/de10_lite/pll.vhd @@ -1,432 +1,431 @@ --- megafunction wizard: %ALTPLL% --- GENERATION: STANDARD --- VERSION: WM1.0 --- MODULE: altpll - --- ============================================================ --- File Name: pll.vhd --- Megafunction Name(s): --- altpll --- --- Simulation Library Files(s): --- altera_mf --- ============================================================ --- ************************************************************ --- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! --- --- 20.1.1 Build 720 11/11/2020 SJ Lite Edition --- ************************************************************ - - ---Copyright (C) 2020 Intel Corporation. All rights reserved. ---Your use of Intel Corporation's design tools, logic functions ---and other software and tools, and any partner logic ---functions, and any output files from any of the foregoing ---(including device programming or simulation files), and any ---associated documentation or information are expressly subject ---to the terms and conditions of the Intel Program License ---Subscription Agreement, the Intel Quartus Prime License Agreement, ---the Intel FPGA IP License Agreement, or other applicable license ---agreement, including, without limitation, that your use is for ---the sole purpose of programming logic devices manufactured by ---Intel and sold by Intel or its authorized distributors. Please ---refer to the applicable agreement for further details, at ---https://fpgasoftware.intel.com/eula. - - -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY pll IS - PORT - ( - areset : IN STD_LOGIC := '0'; - inclk0 : IN STD_LOGIC := '0'; - c0 : OUT STD_LOGIC ; - c1 : OUT STD_LOGIC ; - c2 : OUT STD_LOGIC ; - locked : OUT STD_LOGIC - ); -END pll; - - -ARCHITECTURE SYN OF pll IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); - SIGNAL sub_wire1 : STD_LOGIC ; - SIGNAL sub_wire2 : STD_LOGIC ; - SIGNAL sub_wire3 : STD_LOGIC ; - SIGNAL sub_wire4 : STD_LOGIC ; - SIGNAL sub_wire5 : STD_LOGIC ; - SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0); - SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0); - SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0); - - - - COMPONENT altpll - GENERIC ( - bandwidth_type : STRING; - clk0_divide_by : NATURAL; - clk0_duty_cycle : NATURAL; - clk0_multiply_by : NATURAL; - clk0_phase_shift : STRING; - clk1_divide_by : NATURAL; - clk1_duty_cycle : NATURAL; - clk1_multiply_by : NATURAL; - clk1_phase_shift : STRING; - clk2_divide_by : NATURAL; - clk2_duty_cycle : NATURAL; - clk2_multiply_by : NATURAL; - clk2_phase_shift : STRING; - compensate_clock : STRING; - inclk0_input_frequency : NATURAL; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - operation_mode : STRING; - pll_type : STRING; - port_activeclock : STRING; - port_areset : STRING; - port_clkbad0 : STRING; - port_clkbad1 : STRING; - port_clkloss : STRING; - port_clkswitch : STRING; - port_configupdate : STRING; - port_fbin : STRING; - port_inclk0 : STRING; - port_inclk1 : STRING; - port_locked : STRING; - port_pfdena : STRING; - port_phasecounterselect : STRING; - port_phasedone : STRING; - port_phasestep : STRING; - port_phaseupdown : STRING; - port_pllena : STRING; - port_scanaclr : STRING; - port_scanclk : STRING; - port_scanclkena : STRING; - port_scandata : STRING; - port_scandataout : STRING; - port_scandone : STRING; - port_scanread : STRING; - port_scanwrite : STRING; - port_clk0 : STRING; - port_clk1 : STRING; - port_clk2 : STRING; - port_clk3 : STRING; - port_clk4 : STRING; - port_clk5 : STRING; - port_clkena0 : STRING; - port_clkena1 : STRING; - port_clkena2 : STRING; - port_clkena3 : STRING; - port_clkena4 : STRING; - port_clkena5 : STRING; - port_extclk0 : STRING; - port_extclk1 : STRING; - port_extclk2 : STRING; - port_extclk3 : STRING; - self_reset_on_loss_lock : STRING; - width_clock : NATURAL - ); - PORT ( - areset : IN STD_LOGIC ; - inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); - locked : OUT STD_LOGIC - ); - END COMPONENT; - -BEGIN - sub_wire7_bv(0 DOWNTO 0) <= "0"; - sub_wire7 <= To_stdlogicvector(sub_wire7_bv); - sub_wire3 <= sub_wire0(2); - sub_wire2 <= sub_wire0(1); - sub_wire1 <= sub_wire0(0); - c0 <= sub_wire1; - c1 <= sub_wire2; - c2 <= sub_wire3; - locked <= sub_wire4; - sub_wire5 <= inclk0; - sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5; - - altpll_component : altpll - GENERIC MAP ( - bandwidth_type => "AUTO", - clk0_divide_by => 50, - clk0_duty_cycle => 50, - clk0_multiply_by => 1, - clk0_phase_shift => "0", - clk1_divide_by => 1, - clk1_duty_cycle => 50, - clk1_multiply_by => 1, - clk1_phase_shift => "0", - clk2_divide_by => 15625, - clk2_duty_cycle => 50, - clk2_multiply_by => 12, - clk2_phase_shift => "0", - compensate_clock => "CLK0", - inclk0_input_frequency => 20000, - intended_device_family => "MAX 10", - lpm_hint => "CBX_MODULE_PREFIX=pll", - lpm_type => "altpll", - operation_mode => "NORMAL", - pll_type => "AUTO", - port_activeclock => "PORT_UNUSED", - port_areset => "PORT_USED", - port_clkbad0 => "PORT_UNUSED", - port_clkbad1 => "PORT_UNUSED", - port_clkloss => "PORT_UNUSED", - port_clkswitch => "PORT_UNUSED", - port_configupdate => "PORT_UNUSED", - port_fbin => "PORT_UNUSED", - port_inclk0 => "PORT_USED", - port_inclk1 => "PORT_UNUSED", - port_locked => "PORT_USED", - port_pfdena => "PORT_UNUSED", - port_phasecounterselect => "PORT_UNUSED", - port_phasedone => "PORT_UNUSED", - port_phasestep => "PORT_UNUSED", - port_phaseupdown => "PORT_UNUSED", - port_pllena => "PORT_UNUSED", - port_scanaclr => "PORT_UNUSED", - port_scanclk => "PORT_UNUSED", - port_scanclkena => "PORT_UNUSED", - port_scandata => "PORT_UNUSED", - port_scandataout => "PORT_UNUSED", - port_scandone => "PORT_UNUSED", - port_scanread => "PORT_UNUSED", - port_scanwrite => "PORT_UNUSED", - port_clk0 => "PORT_USED", - port_clk1 => "PORT_USED", - port_clk2 => "PORT_USED", - port_clk3 => "PORT_UNUSED", - port_clk4 => "PORT_UNUSED", - port_clk5 => "PORT_UNUSED", - port_clkena0 => "PORT_UNUSED", - port_clkena1 => "PORT_UNUSED", - port_clkena2 => "PORT_UNUSED", - port_clkena3 => "PORT_UNUSED", - port_clkena4 => "PORT_UNUSED", - port_clkena5 => "PORT_UNUSED", - port_extclk0 => "PORT_UNUSED", - port_extclk1 => "PORT_UNUSED", - port_extclk2 => "PORT_UNUSED", - port_extclk3 => "PORT_UNUSED", - self_reset_on_loss_lock => "OFF", - width_clock => 5 - ) - PORT MAP ( - areset => areset, - inclk => sub_wire6, - clk => sub_wire0, - locked => sub_wire4 - ); - - - -END SYN; - --- ============================================================ --- CNX file retrieval info --- ============================================================ --- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" --- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" --- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" --- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" --- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" --- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" --- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" --- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" --- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" --- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" --- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" --- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" --- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" --- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" --- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" --- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.038400" --- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" --- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" --- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" --- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" --- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" --- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" --- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" --- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" --- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" --- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" --- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" --- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" --- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" --- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" --- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" --- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" --- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" --- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" --- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.03840000" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" --- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" --- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" --- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" --- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" --- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" --- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" --- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" --- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" --- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" --- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" --- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" --- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" --- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" --- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" --- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" --- Retrieval info: PRIVATE: SPREAD_USE STRING "0" --- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" --- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" --- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" --- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" --- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" --- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: USE_CLK0 STRING "1" --- Retrieval info: PRIVATE: USE_CLK1 STRING "1" --- Retrieval info: PRIVATE: USE_CLK2 STRING "1" --- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" --- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" --- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" --- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" --- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all --- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "15625" --- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12" --- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" --- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" --- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" --- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" --- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" --- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" --- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" --- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" --- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" --- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" --- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" --- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" --- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" --- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" --- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" --- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" --- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" --- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" --- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" --- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 --- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 --- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 --- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 --- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 --- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE --- Retrieval info: LIB_FILE: altera_mf --- Retrieval info: CBX_MODULE_PREFIX: ON +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 22.1std.0 Build 915 10/25/2022 SC Lite Edition +-- ************************************************************ + + +--Copyright (C) 2022 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details, at +--https://fpgasoftware.intel.com/eula. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC ; + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire2_bv(0 DOWNTO 0) <= "0"; + sub_wire2 <= To_stdlogicvector(sub_wire2_bv); + sub_wire0 <= inclk0; + sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0; + sub_wire6 <= sub_wire3(2); + sub_wire5 <= sub_wire3(1); + sub_wire4 <= sub_wire3(0); + c0 <= sub_wire4; + c1 <= sub_wire5; + c2 <= sub_wire6; + locked <= sub_wire7; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 50, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + clk1_divide_by => 1, + clk1_duty_cycle => 50, + clk1_multiply_by => 1, + clk1_phase_shift => "0", + clk2_divide_by => 15625, + clk2_duty_cycle => 50, + clk2_multiply_by => 12, + clk2_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "MAX 10", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire1, + clk => sub_wire3, + locked => sub_wire7 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.038400" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.03840000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "15625" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/peripherals/uart/tb_uart.do b/peripherals/uart/tb_uart.do index 31da9546..50aad045 100644 --- a/peripherals/uart/tb_uart.do +++ b/peripherals/uart/tb_uart.do @@ -1,54 +1,54 @@ -# ============================================================================ -# Name : tb_uart.do -# Author : Renan Augusto Starke -# Version : 0.1 -# Copyright : Renan, Departamento de Eletr�nica, Florian�polis, IFSC -# Description : Exemplo de script de compila��o ModelSim -# ============================================================================ - - -#Cria biblioteca do projeto -vlib work - -#compila projeto: todos os aquivo. Ordem � importante -vcom uart.vhd tb_uart.vhd - -#Simula -vsim -t ns work.tb_uart - -#Mosta forma de onda -view wave - -#Adiciona ondas espec�ficas -# -radix: binary, hex, dec -# -label: nome da forma de onda - -add wave -height 15 -divider "Clocks and Chip Sel." -#add wave -radix binary -label clk_in_1M /clk_in_1M -add wave -radix binary -label clk_baud /clk_baud -add wave -radix binary -label csel /csel - -add wave -height 15 -divider "TX" -add wave -radix hex -label data_in /data_in -add wave -radix binary -label to_tx /dut/to_tx -add wave -radix binary -label tx /tx -add wave -radix dec -label cnt_tx /dut/cnt_tx -add wave -radix binary -label tx_cmp /tx_cmp -add wave -radix binary -label state_tx /dut/state_tx - -add wave -height 15 -divider "RX" -#add wave -radix binary -label clk_in_1M /clk_in_1M -add wave -radix binary -label clk_baud /clk_baud -add wave -radix binary -label state_rx /dut/state_rx -add wave -radix binary -label to_rx /to_rx -add wave -radix binary -label rx /rx -add wave -radix binary -label from_rx /dut/from_rx -add wave -radix dec -label cnt_rx /dut/cnt_rx -add wave -radix binary -label rx_cmp /rx_cmp -add wave -radix hex -label data_out /data_out - -#Simula at� 60ns -run 10000 us - -wave zoomfull -write wave wave.ps +# ============================================================================ +# Name : tb_uart.do +# Author : Renan Augusto Starke +# Version : 0.1 +# Copyright : Renan, Departamento de Eletr nica, Florian polis, IFSC +# Description : Exemplo de script de compila o ModelSim +# ============================================================================ + + +#Cria biblioteca do projeto +vlib work + +#compila projeto: todos os aquivo. Ordem importante +vcom uart.vhd coretestbench.vhd + +#Simula +vsim -t ns work.tb_uart + +#Mosta forma de onda +view wave + +#Adiciona ondas espec ficas +# -radix: binary, hex, dec +# -label: nome da forma de onda + +add wave -height 15 -divider "Clocks and Chip Sel." +#add wave -radix binary -label clk_in_1M /clk_in_1M +add wave -radix binary -label clk_baud /clk_baud +add wave -radix binary -label csel /csel + +add wave -height 15 -divider "TX" +add wave -radix hex -label data_in /data_in +add wave -radix binary -label to_tx /dut/to_tx +add wave -radix binary -label tx /tx +add wave -radix dec -label cnt_tx /dut/cnt_tx +add wave -radix binary -label tx_cmp /tx_cmp +add wave -radix binary -label state_tx /dut/state_tx + +add wave -height 15 -divider "RX" +#add wave -radix binary -label clk_in_1M /clk_in_1M +add wave -radix binary -label clk_baud /clk_baud +add wave -radix binary -label state_rx /dut/state_rx +add wave -radix binary -label to_rx /to_rx +add wave -radix binary -label rx /rx +add wave -radix binary -label from_rx /dut/from_rx +add wave -radix dec -label cnt_rx /dut/cnt_rx +add wave -radix binary -label rx_cmp /rx_cmp +add wave -radix hex -label data_out /data_out + +#Simula at 60ns +run 10000 us + +wave zoomfull +write wave wave.ps diff --git a/peripherals/uart/testbench.do b/peripherals/uart/testbench.do index c2b9022a..5c29a3cd 100644 --- a/peripherals/uart/testbench.do +++ b/peripherals/uart/testbench.do @@ -1,174 +1,186 @@ -#****************************************************************************** -# * -# Copyright (C) 2019 IFSC * -# * -# * -# All information provided herein is provided on an "as is" basis, * -# without warranty of any kind. * -# * -# File Name: testbench.do * -# * -# Function: riscv muticycle simulation script * -# * -# REVISION HISTORY: * -# Revision 0.1.0 08/01/2018 - Initial Revision * -# Revision 0.2.0 04/06/2021 - Update UART module * -#****************************************************************************** - -vlib work -vcom ./uart.vhd -vcom ../../memory/iram_quartus.vhd -vcom ../../memory/dmemory.vhd -vcom ../../memory/instructionbusmux.vhd -vcom ../../memory/databusmux.vhd -vcom ../../memory/iodatabusmux.vhd -vcom ../../alu/alu_types.vhd -vcom ../../alu/alu.vhd -vcom ../../alu/m/division_functions.vhd -vcom ../../alu/m/quick_naive.vhd -vcom ../../alu/m/M_types.vhd -vcom ../../alu/m/M.vhd -vcom ../../decoder/decoder_types.vhd -vcom ../../decoder/iregister.vhd -vcom ../../decoder/decoder.vhd -vcom ../../registers/register_file.vhd -vcom ../../peripherals/gpio/gpio.vhd -vcom ../../peripherals/gpio/led_displays.vhd -vcom ../../peripherals/timer/Timer.vhd -vcom ../../core/csr.vhd -vcom ../../core/core.vhd -vcom ../../core/txt_util.vhdl -vcom ../../core/trace_debug.vhd -vcom coretestbench.vhd - -vsim -t ns work.uart_coretestbench - -view wave -add wave -radix binary -label clk /clk -add wave -radix binary -label rst /rst -add wave -height 15 -divider "Instruction Memory" -add wave -label iAddr -radix hex /address -add wave -label iWord -radix hex idata -add wave -label decoded -radix ASCII /debugString -# add wave /debugString -# add wave -radix hex /imem/RAM -# add wave -radix hex /q - -add wave -height 15 -divider "PC and Ctrl Targers" -add wave -radix hex -label pc /myRiscv/pc -add wave -radix hex -label jal_target /myRiscv/jal_target -add wave -radix hex -label jalr_target /myRiscv/jalr_target -add wave -label branch_cmp /myRiscv/branch_cmp -add wave -radix hex -label jumps /myRiscv/jumps - - -add wave -height 15 -divider "Iregister debug" -add wave -label opcode /myRiscv/opcodes -add wave -label rd /myRiscv/rd -add wave -label rs1 /myRiscv/rs1 -add wave -label rs2 /myRiscv/rs2 -add wave -label imm_i /myRiscv/imm_i -add wave -label imm_s /myRiscv/imm_s -add wave -label imm_b /myRiscv/imm_b -add wave -label imm_u /myRiscv/imm_u -add wave -label imm_j /myRiscv/imm_j - - -add wave -height 15 -divider "Register file debug" - add wave -label registers -radix hex /myRiscv/registers/ram - add wave -label w_ena /myRiscv/rf_w_ena - add wave -label w_data -radix hex /myRiscv/rw_data - add wave -label r1_data -radix hex /myRiscv/rs1_data - add wave -label r2_data -radix hex /myRiscv/rs2_data - -# decoder debug -add wave -label states /myRiscv/decoder0/state - -add wave -height 15 -divider "GPIO" -add wave -label enable_exti_mask -radix hex /generic_gpio/enable_exti_mask -add wave -label edge_exti_mask -radix hex /generic_gpio/edge_exti_mask -add wave -label output_reg -radix hex /generic_gpio/output_reg - -add wave -height 15 -divider "CSR" -add wave -label interrupts -radix hex /myRiscv/interrupts -add wave -label pending_interrupts -radix hex /myRiscv/ins_csr/pending_interrupts -add wave -label mret -radix hex /myRiscv/ins_csr/mret -add wave -label pending /myRiscv/pending -add wave -label csr_write /myRiscv/csr_write -add wave -label csr_addr /myRiscv/imm_i -add wave -label csr_value -radix hex /myRiscv/csr_value -add wave -label load_mepc -radix hex /myRiscv/load_mepc -# add wave -label load_mepc_holder -radix hex /myRiscv/ins_csr/load_mepc_holder -add wave -label mepc -radix hex /myRiscv/mepc -add wave -label mretpc -radix hex /myRiscv/mretpc -add wave -label csr_new -radix hex /myRiscv/rs1_data -# add wave -label mreg -radix hex /myRiscv/ins_csr/mreg - - -add wave -height 15 -divider "Alu debug" -add wave -radix dec -label aluData /myRiscv/alu_data -add wave -radix dec -label aluOut /myRiscv/alu_out - -add wave -height 15 -divider "M Extension debug" -add wave -label clock_32x /myRiscv/clk_32x -add wave -label code_operator /myRiscv/M_data.code -add wave -radix dec -label a_integer /myRiscv/M_data.a -add wave -radix dec -label b_integer /myRiscv/M_data.b -add wave -radix dec -label M_out /myRiscv/M_out - -add wave -height 15 -divider "Data memory debug" -add wave -label daddr -radix hex /myRiscv/memAddrTypeSBlock/addr -add wave -label fsm_data -radix hex /dmem/fsm_data -add wave -label ram_data -radix hex /dmem/ram_data -add wave -label mState /dmem/state -add wave -label fsm_we /dmem/fsm_we -add wave -label ddata_r_mem -radix hex /dmem/q -add wave -label datamemory -radix hex /dmem/ram_block - - -add wave -height 15 -divider "Data bus" -add wave -label daddress -radix hex /daddress -add wave -label ddata_r -radix hex /ddata_r -add wave -label ddata_w -radix hex /ddata_w -add wave -label dmask -radix bin /dmask -add wave -label dcsel /dcsel -add wave -label d_we /d_we -add wave -label d_rd /d_rd -add wave -label d_sig /d_sig - -add wave -height 15 -divider "Peripheral Data bus" -add wave -label daddress -radix hex /daddress -add wave -label ddata_r_periph -radix hex /ddata_r_periph -add wave -label ddata_r_gpio -radix hex /ddata_r_gpio - -add wave -label gpio_interrupts -radix hex /gpio_interrupts -add wave -label gpio_input -radix hex /gpio_input - -add wave -height 15 -divider "UART" -add wave -label clk /generic_uart/clk -add wave -label clk_baud /generic_uart/clk_baud -add wave -label transmit_byte -radix hex /transmit_byte -add wave -label transmit_frame /transmit_frame -add wave -label config /generic_uart/config_register -add wave -label uart_register -radix hex /generic_uart/uart_register -add wave -label ddata_w -radix hex /generic_uart/ddata_w -add wave -label tx_register -radix hex /generic_uart/tx_register -add wave -label rx_register -radix hex /generic_uart/rx_register -add wave -label from_rx -radix bin /generic_uart/rx_receive/from_rx - -add wave -label tx_done /generic_uart/tx_done -add wave -label rx_done /generic_uart/rx_done -add wave -label TX -radix hex /TX -add wave -label RX -radix hex /RX -add wave -label rx_state /generic_uart/state_rx -add wave -label tx_state /generic_uart/state_tx -add wave -label interrupts /generic_uart/interrupts - - - -add wave -height 15 -divider "Input/Output SIM" -add wave -label LEDR -radix hex /LEDR -add wave -label HEX0 -radix hex /HEX0 - -run 2000 us -wave zoomfull +#****************************************************************************** +# * +# Copyright (C) 2019 IFSC * +# * +# * +# All information provided herein is provided on an "as is" basis, * +# without warranty of any kind. * +# * +# File Name: testbench.do * +# * +# Function: riscv muticycle simulation script * +# * +# REVISION HISTORY: * +# Revision 0.1.0 08/01/2018 - Initial Revision * +# Revision 0.2.0 04/06/2021 - Update UART module * +#****************************************************************************** + +vlib work +vcom ./uart.vhd +vcom ../../memory/iram_quartus.vhd +vcom ../../memory/dmemory.vhd +vcom ../../memory/instructionbusmux.vhd +vcom ../../memory/databusmux.vhd +vcom ../../memory/iodatabusmux.vhd +vcom ../../alu/alu_types.vhd +vcom ../../alu/alu.vhd +vcom ../../alu/m/division_functions.vhd +vcom ../../alu/m/quick_naive.vhd +vcom ../../alu/m/M_types.vhd +vcom ../../alu/m/M.vhd +vcom ../../decoder/decoder_types.vhd +vcom ../../decoder/iregister.vhd +vcom ../../decoder/decoder.vhd +vcom ../../registers/register_file.vhd +vcom ../../peripherals/gpio/gpio.vhd +vcom ../../peripherals/gpio/led_displays.vhd +vcom ../../peripherals/timer/Timer.vhd +vcom ../../core/csr.vhd +vcom ../../core/core.vhd +vcom ../../core/txt_util.vhdl +vcom ../../core/trace_debug.vhd +vcom coretestbench.vhd + +vsim -t ns work.uart_coretestbench + +view wave +add wave -radix binary -label clk /clk +add wave -radix binary -label rst /rst +add wave -height 15 -divider "Instruction Memory" +add wave -label iAddr -radix hex /address +add wave -label iWord -radix hex idata +add wave -label decoded -radix ASCII /debugString +# add wave /debugString +# add wave -radix hex /imem/RAM +# add wave -radix hex /q + +add wave -height 15 -divider "PC and Ctrl Targers" +add wave -radix hex -label pc /myRiscv/pc +add wave -radix hex -label jal_target /myRiscv/jal_target +add wave -radix hex -label jalr_target /myRiscv/jalr_target +add wave -label branch_cmp /myRiscv/branch_cmp +add wave -radix hex -label jumps /myRiscv/jumps + + +add wave -height 15 -divider "Iregister debug" +add wave -label opcode /myRiscv/opcodes +add wave -label rd /myRiscv/rd +add wave -label rs1 /myRiscv/rs1 +add wave -label rs2 /myRiscv/rs2 +add wave -label imm_i /myRiscv/imm_i +add wave -label imm_s /myRiscv/imm_s +add wave -label imm_b /myRiscv/imm_b +add wave -label imm_u /myRiscv/imm_u +add wave -label imm_j /myRiscv/imm_j + + +add wave -height 15 -divider "Register file debug" + add wave -label registers -radix hex /myRiscv/registers/ram + add wave -label w_ena /myRiscv/rf_w_ena + add wave -label w_data -radix hex /myRiscv/rw_data + add wave -label r1_data -radix hex /myRiscv/rs1_data + add wave -label r2_data -radix hex /myRiscv/rs2_data + +# decoder debug +add wave -label states /myRiscv/decoder0/state + +add wave -height 15 -divider "GPIO" +add wave -label enable_exti_mask -radix hex /generic_gpio/enable_exti_mask +add wave -label edge_exti_mask -radix hex /generic_gpio/edge_exti_mask +add wave -label output_reg -radix hex /generic_gpio/output_reg + +add wave -height 15 -divider "CSR" +add wave -label interrupts -radix hex /myRiscv/interrupts +add wave -label pending_interrupts -radix hex /myRiscv/ins_csr/pending_interrupts +add wave -label mret -radix hex /myRiscv/ins_csr/mret +add wave -label pending /myRiscv/pending +add wave -label csr_write /myRiscv/csr_write +add wave -label csr_addr /myRiscv/imm_i +add wave -label csr_value -radix hex /myRiscv/csr_value +add wave -label load_mepc -radix hex /myRiscv/load_mepc +# add wave -label load_mepc_holder -radix hex /myRiscv/ins_csr/load_mepc_holder +add wave -label mepc -radix hex /myRiscv/mepc +add wave -label mretpc -radix hex /myRiscv/mretpc +add wave -label csr_new -radix hex /myRiscv/rs1_data +# add wave -label mreg -radix hex /myRiscv/ins_csr/mreg + + +add wave -height 15 -divider "Alu debug" +add wave -radix dec -label aluData /myRiscv/alu_data +add wave -radix dec -label aluOut /myRiscv/alu_out + +add wave -height 15 -divider "M Extension debug" +add wave -label clock_32x /myRiscv/clk_32x +add wave -label code_operator /myRiscv/M_data.code +add wave -radix dec -label a_integer /myRiscv/M_data.a +add wave -radix dec -label b_integer /myRiscv/M_data.b +add wave -radix dec -label M_out /myRiscv/M_out + +add wave -height 15 -divider "Data memory debug" +add wave -label daddr -radix hex /myRiscv/memAddrTypeSBlock/addr +add wave -label fsm_data -radix hex /dmem/fsm_data +add wave -label ram_data -radix hex /dmem/ram_data +add wave -label mState /dmem/state +add wave -label fsm_we /dmem/fsm_we +add wave -label ddata_r_mem -radix hex /dmem/q +add wave -label datamemory -radix hex /dmem/ram_block + + +add wave -height 15 -divider "Data bus" +add wave -label daddress -radix hex /daddress +add wave -label ddata_r -radix hex /ddata_r +add wave -label ddata_w -radix hex /ddata_w +add wave -label dmask -radix bin /dmask +add wave -label dcsel /dcsel +add wave -label d_we /d_we +add wave -label d_rd /d_rd +add wave -label d_sig /d_sig + +add wave -height 15 -divider "Peripheral Data bus" +add wave -label daddress -radix hex /daddress +add wave -label ddata_r_periph -radix hex /ddata_r_periph +add wave -label ddata_r_gpio -radix hex /ddata_r_gpio + +add wave -label gpio_interrupts -radix hex /gpio_interrupts +add wave -label gpio_input -radix hex /gpio_input + +add wave -height 21 -divider "UART" +add wave -label clk /generic_uart/clk +add wave -label clk_baud /generic_uart/clk_baud +add wave -label transmit_byte -radix hex /transmit_byte +add wave -label transmit_frame /transmit_frame +add wave -label config /generic_uart/config_register +add wave -label uart_register -radix hex /generic_uart/uart_register +add wave -label ddata_w -radix hex /generic_uart/ddata_w +add wave -label ddata_r -radix hex /generic_uart/ddata_r +add wave -label tx_register -radix hex /generic_uart/tx_register +add wave -label rx_register -radix hex /generic_uart/rx_register +add wave -label from_rx -radix bin /generic_uart/rx_receive/from_rx +add wave -label baud_ready -radix bin /generic_uart/baud_ready +add wave -label byte_received -radix bin /generic_uart/byte_received +add wave -label byte_read -radix bin /generic_uart/byte_read +add wave -label tx_done /generic_uart/tx_done +add wave -label rx_done /generic_uart/rx_done +add wave -label TX -radix hex /TX +add wave -label RX -radix hex /RX +add wave -label rx_state /generic_uart/state_rx +add wave -label tx_state /generic_uart/state_tx +add wave -label interrupts /generic_uart/interrupts +add wave -label interrupts /generic_uart/interrupts +add wave -label rx_cmp_irq /generic_uart/rx_cmp_irq +add wave -label rx_done /generic_uart/rx_done + +add wave -height 6 -divider "BUFFER_UART" +add wave -label buffer_rx -radix hex /generic_uart/buffer_rx +add wave -label buffer_byte -radix hex /generic_uart/buffer_byte +add wave -label cnt_rx_buffer -radix hex /generic_uart/cnt_rx_buffer +add wave -label cnt_rx_irq -radix hex /generic_uart/rx_buffer_receive/cnt_rx_irq +add wave -label buffer_mode -radix hex /generic_uart/buffer_mode +add wave -label buffer_register -radix hex /generic_uart/buffer_register + +add wave -height 15 -divider "Input/Output SIM" +add wave -label LEDR -radix hex /LEDR +add wave -label HEX0 -radix hex /HEX0 + +run 20000 us +wave zoomfull diff --git a/peripherals/uart/uart.vhd b/peripherals/uart/uart.vhd index 88ea11e5..0251b60a 100644 --- a/peripherals/uart/uart.vhd +++ b/peripherals/uart/uart.vhd @@ -1,454 +1,572 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity uart is - generic ( - --! Chip selec - MY_CHIPSELECT : std_logic_vector(1 downto 0) := "10"; - MY_WORD_ADDRESS : unsigned(15 downto 0) := x"0020"; - DADDRESS_BUS_SIZE : integer := 32 - ); - - port( - clk : in std_logic; - rst : in std_logic; - - clk_baud : in std_logic; - - -- Core data bus signals - daddress : in unsigned(DADDRESS_BUS_SIZE-1 downto 0); - ddata_w : in std_logic_vector(31 downto 0); - ddata_r : out std_logic_vector(31 downto 0); - d_we : in std_logic; - d_rd : in std_logic; - dcsel : in std_logic_vector(1 downto 0); --! Chip select - -- ToDo: Module should mask bytes (Word, half word and byte access) - dmask : in std_logic_vector(3 downto 0); --! Byte enable mask - - -- hardware input/output signals - tx_out : out std_logic; - rx_out : in std_logic; - interrupts : out std_logic_vector(1 downto 0) - ); -end entity uart; - -architecture RTL of uart is - - --! UART TX TYPE bit maps (See uart.h) - constant TX_START_BIT : integer := 16; - constant TX_DONE_BIT : integer := 17; - - --! UART RX TYPE bit maps (See uart.h) - constant RX_DONE_BIT : integer := 18; - - --! UART CONFIG TYPE bit maps (See uart.h) - constant RX_ENABLE_BIT : integer := 23; - constant IRQ_RX_ENABLE_BIT : integer := 24; - - constant BAUD_RATE_BIT : integer := 19; --! Bits 19 and 20 - constant PARITY_BIT : integer := 21; --! Bits 21 and 22 - - -- Signals for TX - type state_tx_type is (IDLE, MOUNT_BYTE, TRANSMIT, MOUNT_BYTE_PARITY, TRANSMIT_PARITY, DONE); - signal state_tx : state_tx_type := IDLE; - signal cnt_tx : integer := 0; - signal to_tx : std_logic_vector(10 downto 0) := (others => '1'); - signal to_tx_p : std_logic_vector(11 downto 0) := (others => '1'); - signal send_byte : std_logic; - signal send_byte_p : std_logic; - - -- Interal registers - signal config_register : std_logic_vector (31 downto 0); - signal rx_register : std_logic_vector(7 downto 0); - signal tx_register : std_logic_vector(7 downto 0); - - signal uart_register : std_logic_vector(31 downto 0); - - signal tx : std_logic; - - signal tx_done : std_logic; - signal rx_done : std_logic; - - -- Signals for RX - type state_rx_type is (IDLE, READ_BYTE, DONE); - signal state_rx : state_rx_type := IDLE; - signal cnt_rx : integer := 0; - signal byte_received : std_logic; - - -- Signals for baud rates - signal baud_19200 : std_logic := '0'; - signal baud_09600 : std_logic := '0'; - signal baud_04800 : std_logic := '0'; - signal baud_ready : std_logic := '0'; - - -- Signals for parity - signal parity : std_logic := '0'; - signal number : integer := 0; - - -- Interrupt signal - signal input_data : std_logic; - signal rx_cmp_irq : std_logic; - signal interrupt_en : std_logic := '0'; - - ------------ Function Count Ones ----------- - function count_ones(s : std_logic_vector) return integer is - variable temp : natural := 0; - begin - for i in s'range loop - if s(i) = '1' then temp := temp + 1; - end if; - end loop; - return temp; - end function count_ones; - - ----------- Function Parity Value ---------- - function parity_val(s : integer; setup : std_logic) return std_logic is - variable temp : std_logic := '0'; - begin - if ((s mod 2) = 0) and (setup = '0') then --Paridade ativada impar - temp := '0'; - elsif ((s mod 2) = 0) and (setup = '1') then --Paridade ativada par - temp := '1'; - elsif ((s mod 2) = 1) and (setup = '0') then --Paridade ativada impar - temp := '1'; - elsif ((s mod 2) = 1) and (setup = '1') then --Paridade ativada par - temp := '0'; - end if; - return temp; - end function parity_val; - -begin --Baud Entrada = 38400 - - ------------- Baud Rate 19200 -------------- - baud19200: process(clk_baud, baud_19200) is - begin - if rising_edge(clk_baud) and (baud_19200='0') then - baud_19200 <= '1'; - elsif rising_edge(clk_baud) and (baud_19200='1') then - baud_19200 <= '0'; - end if; - end process; - - -------------- Baud Rate 9600 -------------- - baud9600: process(baud_19200, baud_09600) is - begin - if rising_edge(baud_19200) and (baud_09600='0') then - baud_09600 <= '1'; - elsif rising_edge(baud_19200) and (baud_09600='1') then - baud_09600 <= '0'; - end if; - end process; - - -------------- Baud Rate 4800 -------------- - baud4800: process(baud_09600, baud_04800) is - begin - if rising_edge(baud_09600) and (baud_04800='0') then - baud_04800 <= '1'; - elsif rising_edge(baud_09600) and (baud_04800='1') then - baud_04800 <= '0'; - end if; - end process; - - -------------- Baud Rate Select ------------- - baudselect: process(uart_register(BAUD_RATE_BIT+1 downto BAUD_RATE_BIT), baud_04800, baud_09600, baud_19200, clk_baud) is - begin - case uart_register(BAUD_RATE_BIT+1 downto BAUD_RATE_BIT) is - when "00" => - baud_ready <= clk_baud; - when "01" => - baud_ready <= baud_19200; - when "10" => - baud_ready <= baud_09600; - when "11" => - baud_ready <= baud_04800; - when others => - baud_ready <= baud_09600; - end case; - end process; - - - -- Input register - process(clk, rst) - begin - if rst = '1' then - ddata_r <= (others => '0'); - else - if rising_edge(clk) then - if (d_rd = '1') and (dcsel = MY_CHIPSELECT) then - --! Tx register: supports byte read - if daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0000") then - ddata_r <= (others => '0'); - case dmask is - when "1111" => ddata_r <= uart_register; - when "0011" => ddata_r(15 downto 0) <= uart_register(15 downto 0); - when "1100" => ddata_r(15 downto 0) <= uart_register(31 downto 16); - when "0001" => ddata_r(7 downto 0) <= uart_register(7 downto 0); - when "0010" => ddata_r(7 downto 0) <= uart_register(15 downto 8); - when "0100" => ddata_r(7 downto 0) <= uart_register(23 downto 16); - when "1000" => ddata_r(7 downto 0) <= uart_register(31 downto 24); - when others => - end case; - - elsif daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0001") then - ddata_r(7 downto 0) <= rx_register; - elsif daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0003") then - ddata_r(0) <= tx_done; - ddata_r(1) <= rx_done; - end if; - end if; - end if; - end if; - end process; - - tx_register(7 downto 0) <= uart_register(7 downto 0); --! Byte to transmit - - -- Output register - process(clk, rst) - begin - if rst = '1' then - -- tx_register <= (others => '0'); - uart_register <= (others => '0'); - elsif rising_edge(clk) then - - -- Set/Reset register to detect writes in TX_START_BIT - uart_register(TX_START_BIT) <= not tx_done; - uart_register(15 downto 8) <= rx_register; - uart_register(RX_DONE_BIT) <= rx_done; - uart_register(RX_ENABLE_BIT) <= not rx_done; - - if (d_we = '1') and (dcsel = MY_CHIPSELECT) then - - --! Tx register supports byte write - if daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0000") then - case dmask is - when "1111" => - uart_register <= ddata_w(31 downto 0); - when "0011" => - uart_register(15 downto 0) <= ddata_w(15 downto 0); - when "1100" => - uart_register(31 downto 16) <= ddata_w(15 downto 0); - when "0001" => - uart_register(7 downto 0) <= ddata_w(7 downto 0); - when "0010" => - uart_register(15 downto 8) <= ddata_w(7 downto 0); - when "0100" => - uart_register(23 downto 16) <= ddata_w(7 downto 0); - when "1000" => - uart_register(31 downto 24) <= ddata_w(7 downto 0); - when others => - end case; - end if; - end if; - - -- Keep Done flag - uart_register(TX_DONE_BIT) <= tx_done; - - end if; - end process; - - - ---------------- Parity Setup --------------- - parity_set: process(uart_register(PARITY_BIT+1 downto PARITY_BIT), number, tx_register) is - begin - number <= 0; - parity <= '0'; - - if uart_register(PARITY_BIT + 1) = '1' then - number <= count_ones(tx_register(7 downto 0)); - parity <= parity_val(number, uart_register(PARITY_BIT)); - end if; - end process; - - -------------------- TX -------------------- - - -- Maquina de estado TX: Moore - estado_tx: process(clk,rst) is - begin - if rst = '1' then - state_tx <= IDLE; - elsif rising_edge(clk) then - case state_tx is - when IDLE => - -- Start transmission bit - if uart_register(TX_START_BIT) = '1' then - - if uart_register(PARITY_BIT + 1) = '1' then - state_tx <= MOUNT_BYTE_PARITY; - elsif uart_register(PARITY_BIT + 1) = '0' then - state_tx <= MOUNT_BYTE; - else - state_tx <= IDLE; - end if; - end if; - when MOUNT_BYTE => - state_tx <= TRANSMIT; - when MOUNT_BYTE_PARITY => - state_tx <= TRANSMIT_PARITY; - when TRANSMIT => - if (cnt_tx < 10) then - state_tx <= TRANSMIT; - else - state_tx <= DONE; - end if; - when TRANSMIT_PARITY => - if (cnt_tx < 11) then - state_tx <= TRANSMIT_PARITY; - else - state_tx <= DONE; - end if; - - when DONE => - state_tx <= IDLE; - end case; - end if; - end process; - - -- MEALY: transmission - tx_proc: process(state_tx, tx_register, parity) - begin - - tx_done <= '0'; - send_byte <= '0'; - send_byte_p <= '0'; - - to_tx <= (others => '1'); - to_tx_p <= (others => '1'); - - case state_tx is - when IDLE => - to_tx <= (others => '1'); - send_byte <= '0'; - tx_done <= '1'; - when MOUNT_BYTE => - to_tx <= "11" & tx_register(7 downto 0) & '0'; - tx_done <= '0'; - send_byte <= '0'; - - when MOUNT_BYTE_PARITY => - to_tx_p <= "11" & tx_register(7 downto 0) & parity & '0'; - tx_done <= '0'; - send_byte_p <= '0'; - - when TRANSMIT => - send_byte <= '1'; - to_tx <= "11" & tx_register(7 downto 0) & '0'; - - when TRANSMIT_PARITY => - send_byte_p <= '1'; - to_tx_p <= "11" & tx_register(7 downto 0) & parity & '0'; - - when DONE => - tx_done <= '1'; - - end case; - - end process; - - tx_send: process(baud_ready) - begin - if rising_edge(baud_ready) then - if send_byte = '1' then - tx <= to_tx(cnt_tx); - cnt_tx <= cnt_tx + 1; - elsif send_byte_p = '1' then - tx <= to_tx_p(cnt_tx); - cnt_tx <= cnt_tx + 1; - else - tx <= '1'; - cnt_tx <= 0; - end if; - end if; - end process; - - - -------------------- RX -------------------- - -- Maquina de estado RX: Moore - estado_rx: process(clk,rst) is - begin - if rst = '1' then - state_rx <= IDLE; - elsif rising_edge(clk) then - case state_rx is - when IDLE => - if uart_register(RX_ENABLE_BIT) = '1' then - if rx_out = '0' then - state_rx <= READ_BYTE; - else - state_rx <= IDLE; - end if; - end if; - when READ_BYTE => - if (cnt_rx < 10) then - state_rx <= READ_BYTE; - else - state_rx <= DONE; - end if; - when DONE => - state_rx <= IDLE; - - end case; - end if; - end process; - - -- Maquina MEALY: transmission - rx_proc: process(state_rx, uart_register(RX_ENABLE_BIT)) - begin - byte_received <= '0'; - rx_done <= '0'; - rx_cmp_irq <= '0'; - case state_rx is - when IDLE => - rx_done <= not uart_register(RX_ENABLE_BIT); - rx_cmp_irq <= '1'; - byte_received <= '0'; - when READ_BYTE => - rx_done <= '0'; - rx_cmp_irq <= '0'; - byte_received <= '1'; - when DONE => - rx_done <= '1'; - end case; - end process; - - rx_receive: process(rst, baud_ready, byte_received) - variable from_rx : std_logic_vector(9 downto 0); - begin - if rst = '1' then - rx_register <= (others => '0'); - cnt_rx <= 0; - from_rx := (others => '0'); - else - if byte_received = '1' then - if rising_edge(baud_ready) then - from_rx(cnt_rx) := rx_out; - cnt_rx <= cnt_rx + 1; - if cnt_rx = 8 then - rx_register <= from_rx(8 downto 1); - end if; - end if; - else - cnt_rx <= 0; - end if; - end if; - end process; - - interrupt_proc: process(clk, rst) - begin - if rst = '1' then - interrupts <= (others => '0'); - elsif rising_edge(clk) then - interrupts(1) <= '0'; - - if input_data = '0' and rx_cmp_irq = '1' and uart_register(IRQ_RX_ENABLE_BIT) = '1' then - interrupts(0) <= '1'; - else - interrupts(0) <= '0'; - end if; - input_data <= rx_cmp_irq; - end if; - end process; - - tx_out <= tx; - -end architecture RTL; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity uart is + generic( + --! Chip selec + MY_CHIPSELECT : std_logic_vector(1 downto 0) := "10"; + MY_WORD_ADDRESS : unsigned(15 downto 0) := x"0020"; + DADDRESS_BUS_SIZE : integer := 32 + ); + + port( + clk : in std_logic; + rst : in std_logic; + clk_baud : in std_logic; + -- Core data bus signals + daddress : in unsigned(DADDRESS_BUS_SIZE - 1 downto 0); + ddata_w : in std_logic_vector(31 downto 0); + ddata_r : out std_logic_vector(31 downto 0); + d_we : in std_logic; + d_rd : in std_logic; + dcsel : in std_logic_vector(1 downto 0); --! Chip select + -- ToDo: Module should mask bytes (Word, half word and byte access) + dmask : in std_logic_vector(3 downto 0); --! Byte enable mask + + -- hardware input/output signals + tx_out : out std_logic; + rx_out : in std_logic; + interrupts : out std_logic_vector(1 downto 0) + ); +end entity uart; + +architecture RTL of uart is + + --! UART TX TYPE bit maps (See uart.h) + constant TX_START_BIT : integer := 16; + constant TX_DONE_BIT : integer := 17; + + --! UART RX TYPE bit maps (See uart.h) + constant RX_DONE_BIT : integer := 18; + + --! UART CONFIG TYPE bit maps (See uart.h) + constant RX_ENABLE_BIT : integer := 23; + constant IRQ_RX_ENABLE_BIT : integer := 24; + + constant BAUD_RATE_BIT : integer := 19; --! Bits 19 and 20 + constant PARITY_BIT : integer := 21; --! Bits 21 and 22 + + --! BUFFER CONFIG TYPE bit maps (See uart.h) + constant IRQ_MODE_BIT : integer := 31; --! Bit 31 + constant NUM_BYTES_IRQ : integer := 7; --! Bits 7 a 0 + constant BYTE_FINAL : integer := 15; --! Bits 15 and 8 + + -- Signals for TX + type state_tx_type is (IDLE, MOUNT_BYTE, TRANSMIT, MOUNT_BYTE_PARITY, TRANSMIT_PARITY, DONE); + signal state_tx : state_tx_type := IDLE; + signal cnt_tx : integer := 0; + signal to_tx : std_logic_vector(10 downto 0) := (others => '1'); + signal to_tx_p : std_logic_vector(11 downto 0) := (others => '1'); + signal send_byte : std_logic; + signal send_byte_p : std_logic; + + -- Interal registers + signal config_register : std_logic_vector(31 downto 0); + signal rx_register : std_logic_vector(7 downto 0); + signal tx_register : std_logic_vector(7 downto 0); + + signal uart_register : std_logic_vector(31 downto 0); + + signal buffer_register : std_logic_vector(31 downto 0); + signal buffer_mode : std_logic; + signal buffer_byte : std_logic_vector(7 downto 0); + + signal tx : std_logic; + + signal tx_done : std_logic; + signal rx_done : std_logic; + + -- Signals for RX + type state_rx_type is (IDLE, READ_BYTE, DONE); + signal state_rx : state_rx_type := IDLE; + signal cnt_rx : integer := 0; + signal byte_received : std_logic; + -- Signal for Buffer RX + signal byte_read : std_logic; + signal cnt_rx_buffer : unsigned(2 downto 0); + + -- Signals for baud rates + signal baud_19200 : std_logic := '0'; + signal baud_09600 : std_logic := '0'; + signal baud_04800 : std_logic := '0'; + signal baud_ready : std_logic := '0'; + + -- Signals for parity + signal parity : std_logic := '0'; + signal number : integer := 0; + + -- Interrupt signal + signal input_data : std_logic; + signal rx_cmp_irq : std_logic; + signal interrupt_en : std_logic := '0'; + + --Declaracao do vetor de buffer RX + type buffer_in is array (0 to 7) of std_logic_vector(7 downto 0); + signal buffer_rx : buffer_in := ( + x"00", x"00", x"00", x"00", + x"00", x"00", x"00", x"00"); + + ------------ Function Count Ones ----------- + function count_ones(s : std_logic_vector) return integer is + variable temp : natural := 0; + begin + for i in s'range loop + if s(i) = '1' then + temp := temp + 1; + end if; + end loop; + return temp; + end function count_ones; + + ----------- Function Parity Value ---------- + function parity_val(s : integer; setup : std_logic) return std_logic is + variable temp : std_logic := '0'; + begin + if ((s mod 2) = 0) and (setup = '0') then --Paridade ativada impar + temp := '0'; + elsif ((s mod 2) = 0) and (setup = '1') then --Paridade ativada par + temp := '1'; + elsif ((s mod 2) = 1) and (setup = '0') then --Paridade ativada impar + temp := '1'; + elsif ((s mod 2) = 1) and (setup = '1') then --Paridade ativada par + temp := '0'; + end if; + return temp; + end function parity_val; + +begin --Baud Entrada = 38400 + + ------------- Baud Rate 19200 -------------- + baud19200 : process(clk_baud, baud_19200) is + begin + if rising_edge(clk_baud) and (baud_19200 = '0') then + baud_19200 <= '1'; + elsif rising_edge(clk_baud) and (baud_19200 = '1') then + baud_19200 <= '0'; + end if; + end process; + + -------------- Baud Rate 9600 -------------- + baud9600 : process(baud_19200, baud_09600) is + begin + if rising_edge(baud_19200) and (baud_09600 = '0') then + baud_09600 <= '1'; + elsif rising_edge(baud_19200) and (baud_09600 = '1') then + baud_09600 <= '0'; + end if; + end process; + + -------------- Baud Rate 4800 -------------- + baud4800 : process(baud_09600, baud_04800) is + begin + if rising_edge(baud_09600) and (baud_04800 = '0') then + baud_04800 <= '1'; + elsif rising_edge(baud_09600) and (baud_04800 = '1') then + baud_04800 <= '0'; + end if; + end process; + + -------------- Baud Rate Select ------------- + baudselect : process(uart_register(BAUD_RATE_BIT+1 downto BAUD_RATE_BIT), baud_04800, baud_09600, baud_19200, clk_baud) is + begin + case uart_register(BAUD_RATE_BIT + 1 downto BAUD_RATE_BIT) is + when "00" => + baud_ready <= clk_baud; + when "01" => + baud_ready <= baud_19200; + when "10" => + baud_ready <= baud_09600; + when "11" => + baud_ready <= baud_04800; + when others => + baud_ready <= baud_09600; + end case; + end process; + + -- Input register + process(clk, rst) + begin + if rst = '1' then + ddata_r <= (others => '0'); + else + if rising_edge(clk) then + if (d_rd = '1') and (dcsel = MY_CHIPSELECT) then + --! Tx register: supports byte read + if daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0000") then + ddata_r <= (others => '0'); + case dmask is + when "1111" => ddata_r <= uart_register; + when "0011" => ddata_r(15 downto 0) <= uart_register(15 downto 0); + when "1100" => ddata_r(15 downto 0) <= uart_register(31 downto 16); + when "0001" => ddata_r(7 downto 0) <= uart_register(7 downto 0); + when "0010" => ddata_r(7 downto 0) <= uart_register(15 downto 8); + when "0100" => ddata_r(7 downto 0) <= uart_register(23 downto 16); + when "1000" => ddata_r(7 downto 0) <= uart_register(31 downto 24); + when others => + end case; + + elsif daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0001") then + ddata_r <= (others => '0'); + case dmask is + when "1111" => ddata_r <= buffer_rx(3) & buffer_rx(2) & buffer_rx(1) & buffer_rx(0); + when "0011" => ddata_r(15 downto 0) <= buffer_rx(1) & buffer_rx(0); + when "1100" => ddata_r(15 downto 0) <= buffer_rx(3) & buffer_rx(2); + when "0001" => ddata_r(7 downto 0) <= buffer_rx(0); + when "0010" => ddata_r(7 downto 0) <= buffer_rx(1); + when "0100" => ddata_r(7 downto 0) <= buffer_rx(2); + when "1000" => ddata_r(7 downto 0) <= buffer_rx(3); + when others => + end case; + + elsif daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0002") then + ddata_r <= (others => '0'); + case dmask is + when "1111" => ddata_r <= buffer_rx(7) & buffer_rx(6) & buffer_rx(5) & buffer_rx(4); + when "0011" => ddata_r(15 downto 0) <= buffer_rx(5) & buffer_rx(4); + when "1100" => ddata_r(15 downto 0) <= buffer_rx(7) & buffer_rx(6); + when "0001" => ddata_r(7 downto 0) <= buffer_rx(4); + when "0010" => ddata_r(7 downto 0) <= buffer_rx(5); + when "0100" => ddata_r(7 downto 0) <= buffer_rx(6); + when "1000" => ddata_r(7 downto 0) <= buffer_rx(7); + when others => + end case; + + elsif daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0003") then + ddata_r <= (others => '0'); + case dmask is + when "1111" => ddata_r <= buffer_register; + when "0011" => ddata_r(15 downto 0) <= buffer_register(15 downto 0); + when "1100" => ddata_r(15 downto 0) <= buffer_register(31 downto 16); + when "0001" => ddata_r(7 downto 0) <= buffer_register(7 downto 0); + when "0010" => ddata_r(7 downto 0) <= buffer_register(15 downto 8); + when "0100" => ddata_r(7 downto 0) <= buffer_register(23 downto 16); + when "1000" => ddata_r(7 downto 0) <= buffer_register(31 downto 24); + when others => + end case; + end if; + end if; + end if; + end if; + end process; + + tx_register(7 downto 0) <= uart_register(7 downto 0); --! Byte to transmit + + -- Output register + process(clk, rst) + begin + if rst = '1' then + -- tx_register <= (others => '0'); + uart_register <= (others => '0'); + buffer_register <= (others => '0'); + elsif rising_edge(clk) then + + -- Set/Reset register to detect writes in TX_START_BIT + uart_register(TX_START_BIT) <= not tx_done; + uart_register(15 downto 8) <= rx_register; + uart_register(RX_DONE_BIT) <= rx_done; + + if (d_we = '1') and (dcsel = MY_CHIPSELECT) then + + --! Tx register supports byte write + if daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0000") then + case dmask is + when "1111" => + uart_register <= ddata_w(31 downto 0); + when "0011" => + uart_register(15 downto 0) <= ddata_w(15 downto 0); + when "1100" => + uart_register(31 downto 16) <= ddata_w(15 downto 0); + when "0001" => + uart_register(7 downto 0) <= ddata_w(7 downto 0); + when "0010" => + uart_register(15 downto 8) <= ddata_w(7 downto 0); + when "0100" => + uart_register(23 downto 16) <= ddata_w(7 downto 0); + when "1000" => + uart_register(31 downto 24) <= ddata_w(7 downto 0); + when others => + end case; + + elsif daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0003") then + case dmask is + when "1111" => + buffer_register <= ddata_w(31 downto 0); + when "0011" => + buffer_register(15 downto 0) <= ddata_w(15 downto 0); + when "1100" => + buffer_register(31 downto 16) <= ddata_w(15 downto 0); + when "0001" => + buffer_register(7 downto 0) <= ddata_w(7 downto 0); + when "0010" => + buffer_register(15 downto 8) <= ddata_w(7 downto 0); + when "0100" => + buffer_register(23 downto 16) <= ddata_w(7 downto 0); + when "1000" => + buffer_register(31 downto 24) <= ddata_w(7 downto 0); + when others => + end case; + end if; + end if; + + -- Keep Done flag + uart_register(TX_DONE_BIT) <= tx_done; + + end if; + end process; + + ---------------- Parity Setup --------------- + parity_set : process(uart_register(PARITY_BIT+1 downto PARITY_BIT), number, tx_register) is + begin + number <= 0; + parity <= '0'; + + if uart_register(PARITY_BIT + 1) = '1' then + number <= count_ones(tx_register(7 downto 0)); + parity <= parity_val(number, uart_register(PARITY_BIT)); + end if; + end process; + + -------------------- TX -------------------- + + -- Maquina de estado TX: Moore + estado_tx : process(clk, rst) is + begin + if rst = '1' then + state_tx <= IDLE; + elsif rising_edge(clk) then + case state_tx is + when IDLE => + -- Start transmission bit + if uart_register(TX_START_BIT) = '1' then + + if uart_register(PARITY_BIT + 1) = '1' then + state_tx <= MOUNT_BYTE_PARITY; + elsif uart_register(PARITY_BIT + 1) = '0' then + state_tx <= MOUNT_BYTE; + else + state_tx <= IDLE; + end if; + end if; + when MOUNT_BYTE => + state_tx <= TRANSMIT; + when MOUNT_BYTE_PARITY => + state_tx <= TRANSMIT_PARITY; + when TRANSMIT => + if (cnt_tx < 10) then + state_tx <= TRANSMIT; + else + state_tx <= DONE; + end if; + when TRANSMIT_PARITY => + if (cnt_tx < 11) then + state_tx <= TRANSMIT_PARITY; + else + state_tx <= DONE; + end if; + + when DONE => + state_tx <= IDLE; + end case; + end if; + end process; + + -- MEALY: transmission + tx_proc : process(state_tx, tx_register, parity) + begin + tx_done <= '0'; + send_byte <= '0'; + send_byte_p <= '0'; + + to_tx <= (others => '1'); + to_tx_p <= (others => '1'); + + case state_tx is + when IDLE => + to_tx <= (others => '1'); + send_byte <= '0'; + tx_done <= '1'; + when MOUNT_BYTE => + to_tx <= "11" & tx_register(7 downto 0) & '0'; + tx_done <= '0'; + send_byte <= '0'; + + when MOUNT_BYTE_PARITY => + to_tx_p <= "11" & tx_register(7 downto 0) & parity & '0'; + tx_done <= '0'; + send_byte_p <= '0'; + + when TRANSMIT => + send_byte <= '1'; + to_tx <= "11" & tx_register(7 downto 0) & '0'; + + when TRANSMIT_PARITY => + send_byte_p <= '1'; + to_tx_p <= "11" & tx_register(7 downto 0) & parity & '0'; + + when DONE => + tx_done <= '1'; + + end case; + + end process; + + tx_send : process(baud_ready) + begin + if rising_edge(baud_ready) then + if send_byte = '1' then + tx <= to_tx(cnt_tx); + cnt_tx <= cnt_tx + 1; + elsif send_byte_p = '1' then + tx <= to_tx_p(cnt_tx); + cnt_tx <= cnt_tx + 1; + else + tx <= '1'; + cnt_tx <= 0; + end if; + end if; + end process; + + -------------------- RX -------------------- + -- Maquina de estado RX: Moore + estado_rx : process(clk, rst) is + begin + if rst = '1' then + state_rx <= IDLE; + elsif rising_edge(clk) then + case state_rx is + when IDLE => + if uart_register(RX_ENABLE_BIT) = '1' then + if rx_out = '0' then + state_rx <= READ_BYTE; + else + state_rx <= IDLE; + end if; + end if; + when READ_BYTE => + if (cnt_rx < 10) then + state_rx <= READ_BYTE; + else + state_rx <= DONE; + end if; + when DONE => + state_rx <= IDLE; + + end case; + end if; + end process; + + -- Maquina MEALY: transmission + rx_proc : process(state_rx, uart_register(RX_ENABLE_BIT)) + begin + byte_received <= '0'; + rx_done <= '0'; + byte_read <= '0'; + case state_rx is + when IDLE => + rx_done <= not uart_register(RX_ENABLE_BIT); + byte_received <= '0'; + byte_read <= '0'; + when READ_BYTE => + rx_done <= '0'; + byte_received <= '1'; + byte_read <= '0'; + when DONE => + rx_done <= '1'; + byte_read <= '1'; + end case; + end process; + + rx_buffer_config : process(rst, clk) + begin + if rst = '1' then + buffer_mode <= '0'; + buffer_byte <= (others => '0'); + elsif rising_edge(clk) then + case uart_register(IRQ_MODE_BIT) is + when '0' => + buffer_mode <= '0'; + buffer_byte <= buffer_register(NUM_BYTES_IRQ downto NUM_BYTES_IRQ - 7); + when '1' => + buffer_mode <= '1'; + buffer_byte <= buffer_register(BYTE_FINAL downto BYTE_FINAL - 7); + when others => + + end case; + end if; + end process; + + rx_buffer_receive : process(rst, clk) + variable cnt_rx_irq : unsigned(2 downto 0); + begin + if rst = '1' then + cnt_rx_buffer <= (others => '0'); + rx_cmp_irq <= '0'; + cnt_rx_irq := (others => '0'); + for i in 0 to 7 loop + buffer_rx(i) <= (others => '0'); + end loop; + elsif rising_edge(clk) then + rx_cmp_irq <= '0'; + if byte_read = '1' then + buffer_rx(to_integer(cnt_rx_buffer)) <= rx_register; + case buffer_mode is + when '0' => if cnt_rx_irq = unsigned(buffer_byte(2 downto 0)) - 1 then + --proc irq handler + cnt_rx_irq := "111"; + rx_cmp_irq <= '1'; + end if; + when '1' => + if rx_register = buffer_byte then + --proc irq handler + rx_cmp_irq <= '1'; + end if; + when others => + end case; + cnt_rx_irq := cnt_rx_irq + 1; + cnt_rx_buffer <= cnt_rx_buffer + 1; + end if; + end if; + end process; + + rx_receive : process(rst, baud_ready, byte_received) + variable from_rx : std_logic_vector(9 downto 0); + begin + if rst = '1' then + rx_register <= (others => '0'); + cnt_rx <= 0; + from_rx := (others => '0'); + else + if byte_received = '1' then + if rising_edge(baud_ready) then + from_rx(cnt_rx) := rx_out; + cnt_rx <= cnt_rx + 1; + if cnt_rx = 8 then + rx_register <= from_rx(8 downto 1); + end if; + end if; + else + cnt_rx <= 0; + end if; + end if; + end process; + + interrupt_proc : process(clk, rst) + begin + if rst = '1' then + interrupts <= (others => '0'); + elsif rising_edge(clk) then + interrupts(1) <= '0'; + + if input_data = '0' and rx_cmp_irq = '1' and uart_register(IRQ_RX_ENABLE_BIT) = '1' then + interrupts(0) <= '1'; + else + interrupts(0) <= '0'; + end if; + input_data <= rx_cmp_irq; + end if; + end process; + + tx_out <= tx; + +end architecture RTL; diff --git a/software/uart/Makefile b/software/uart/Makefile index bb567c78..50773634 100644 --- a/software/uart/Makefile +++ b/software/uart/Makefile @@ -1,56 +1,51 @@ -ifndef RISCV_TOOLS_PREFIX -RISCV_TOOLS_PREFIX=~/Data/Apps/riscv/xpack-riscv-none-embed-gcc-10.1.0-1.1/bin/riscv-none-embed- -# Para usar no LSC -#RISCV_TOOLS_PREFIX = ~/opt/xPacks/@gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2.1/.content/bin/riscv-none-embed- -endif - - -QUARTUS_DIR=/opt/intelFPGA/19.1/quartus/bin/ -CXX = $(RISCV_TOOLS_PREFIX)g++ -march=rv32im -CC = $(RISCV_TOOLS_PREFIX)gcc -march=rv32im -O1 -fpack-struct -AS = $(RISCV_TOOLS_PREFIX)gcc -march=rv32im -#CXXFLAGS = -MD -O1 -Wall -std=c++11 -#CCFLAGS = -MD -O1 -Wall -#LDFLAGS = -Wl,--gc-sections,--no-relax -LDFLAGS = -Wl -LDLIBS = -MAIN = main_irq - -#test: testbench.vvp $(MAIN)32.hex -# # vvp -l testbench.log -N testbench.vvp - -#testbench.vvp: testbench.v ../../picorv32.v $(MAIN)_dbg.v -# #iverilog -o testbench.vvp testbench.v ../../picorv32.v -# #chmod -x testbench.vvp - -quartus_$(MAIN).hex: $(MAIN)32.hex - python3 ../hex8tointel.py $(MAIN).tmp > quartus_$(MAIN).hex - rm $(MAIN)32.hex - -$(MAIN)32.hex: $(MAIN).elf ../hex8tohex32.py - $(RISCV_TOOLS_PREFIX)objcopy -O verilog $(MAIN).elf $(MAIN).tmp - $(RISCV_TOOLS_PREFIX)objdump -h -S $(MAIN).elf > "$(MAIN).lss" - python3 ../hex8tohex32.py $(MAIN).tmp > $(MAIN)32.hex - -start.o: ../_core/start.S - $(CC) -c -nostdlib ../_core/start.S $(LDLIBS) - -$(MAIN).elf: $(MAIN).o start.o ../_core/syscalls.o ../_core/utils.o uart.o ../gpio/gpio.o ../irq/interrupt.o - $(CC) $(LDFLAGS),-Map=$(MAIN).map -o $@ $^ -T ../_core/sections.ld $(LDLIBS) - chmod -x $(MAIN).elf - -sint: - $(QUARTUS_DIR)quartus_sh --flow compile ../peripherals/gpio/sint/de10_lite/de10_lite.cdf - -fpga: - $(QUARTUS_DIR)quartus_pgm -z -m JTAG -o "p;../peripherals/gpio/sint/de10_lite/output_files/de10_lite.sof" - -flash: - $(QUARTUS_DIR)quartus_stp_tcl -t "flash.tcl" - -clean: - rm -f ../*/*.o *.o *.d *.tmp start.elf *.lss *.map - rm -f $(MAIN).elf $(MAIN).hex $(MAIN)32.hex quartus_$(MAIN).hex - --include *.d -.PHONY: test clean +RISCV_TOOLS_PREFIX= /home/bentohq/xpack-riscv-none-elf-gcc-11.3.0-1/bin/riscv-none-elf- + +QUARTUS_DIR=/opt/intelFPGA/19.1/quartus/bin/ +CXX = $(RISCV_TOOLS_PREFIX)g++ -march=rv32im +CC = $(RISCV_TOOLS_PREFIX)gcc -march=rv32im -O1 -fpack-struct +AS = $(RISCV_TOOLS_PREFIX)gcc -march=rv32im +#CXXFLAGS = -MD -O1 -Wall -std=c++11 +#CCFLAGS = -MD -O1 -Wall +#LDFLAGS = -Wl,--gc-sections,--no-relax +LDFLAGS = -Wl +LDLIBS = +MAIN = main_irq + +#test: testbench.vvp $(MAIN)32.hex +# # vvp -l testbench.log -N testbench.vvp + +#testbench.vvp: testbench.v ../../picorv32.v $(MAIN)_dbg.v +# #iverilog -o testbench.vvp testbench.v ../../picorv32.v +# #chmod -x testbench.vvp + +quartus_$(MAIN).hex: $(MAIN)32.hex + python3 ../hex8tointel.py $(MAIN).tmp > quartus_$(MAIN).hex + rm $(MAIN)32.hex + +$(MAIN)32.hex: $(MAIN).elf ../hex8tohex32.py + $(RISCV_TOOLS_PREFIX)objcopy -O verilog $(MAIN).elf $(MAIN).tmp + $(RISCV_TOOLS_PREFIX)objdump -h -S $(MAIN).elf > "$(MAIN).lss" + python3 ../hex8tohex32.py $(MAIN).tmp > $(MAIN)32.hex + +start.o: ../_core/start.S + $(CC) -c -nostdlib ../_core/start.S $(LDLIBS) + +$(MAIN).elf: $(MAIN).o start.o ../_core/syscalls.o ../_core/utils.o uart.o ../gpio/gpio.o ../irq/interrupt.o + $(CC) $(LDFLAGS),-Map=$(MAIN).map -o $@ $^ -T ../_core/sections.ld $(LDLIBS) + chmod -x $(MAIN).elf + +sint: + $(QUARTUS_DIR)quartus_sh --flow compile ../peripherals/gpio/sint/de10_lite/de10_lite.cdf + +fpga: + $(QUARTUS_DIR)quartus_pgm -z -m JTAG -o "p;../peripherals/gpio/sint/de10_lite/output_files/de10_lite.sof" + +flash: + $(QUARTUS_DIR)quartus_stp_tcl -t "flash.tcl" + +clean: + rm -f ../*/*.o *.o *.d *.tmp start.elf *.lss *.map + rm -f $(MAIN).elf $(MAIN).hex $(MAIN)32.hex quartus_$(MAIN).hex + +-include *.d +.PHONY: test clean diff --git a/software/uart/main.c b/software/uart/main.c index 786c8655..59c97257 100644 --- a/software/uart/main.c +++ b/software/uart/main.c @@ -1,42 +1,44 @@ -/* - * main.c - * - * Created on: Jan 20, 2019 - * Author: Marcos Vinicius Leal Da Silva e Daniel Pereira - * Instituto Federal de Santa Catarina - * - * Modified: Renan Augusto Starke - * - * Simple pooling UART TX example. - * ----------------------------------------- - */ - - - #include - #include "uart.h" - #include "../_core/utils.h" - #include "../_core/hardware.h" - - -int main(){ - - uint8_t data = 10; - volatile uint8_t x; - - UART_setup(_38400, NO_PARITY); - UART_reception_enable(); - - while (1){ - - // Testint UART - Reception - x = UART_read(); - - // Testing UART - Transmission - UART_write(x); - - // Display data in IO bus - SEGMENTS_BASE_ADDRESS = x; - } - - return 0; -} +/* + * main.c + * + * Created on: Jan 20, 2019 + * Author: Marcos Vinicius Leal Da Silva e Daniel Pereira + * Instituto Federal de Santa Catarina + * + * Modified: Renan Augusto Starke + * + * Simple pooling UART TX example. + * ----------------------------------------- + */ + + + #include + #include "uart.h" + #include "../_core/utils.h" + #include "../_core/hardware.h" + + +int main(){ + + uint8_t data = 10; + volatile uint8_t x = 0; + + UART_setup(_9600, NO_PARITY); + UART_reception_enable(); + + while (1){ + + // Testint UART - Reception + x = UART_read(); + + // Testing UART - Transmission + UART_write(x); + + // Display data in IO bus + SEGMENTS_BASE_ADDRESS = x; + + + } + + return 0; +} diff --git a/software/uart/main_irq.c b/software/uart/main_irq.c index 5cffb92c..28d91657 100644 --- a/software/uart/main_irq.c +++ b/software/uart/main_irq.c @@ -1,46 +1,52 @@ -/* - * firmware.c - * - * Created on: Jan 20, 2019 - * Author: Marcos Vinicius Leal Da Silva e Daniel Pereira - * Instituto Federal de Santa Catarina - * - * - * Simple LED blink example. - * ----------------------------------------- - */ - -#include -#include "uart.h" -#include "../_core/utils.h" -#include "../_core/hardware.h" -#include "../gpio/gpio.h" -#include "../irq/interrupt.h" - - -void UART_IRQHandler(void){ - uint8_t data; - data = UART_unblocked_read(); - - SEGMENTS_BASE_ADDRESS = data; - - UART_reception_enable(); -} - - -int main(){ - - UART_setup(_38400, NO_PARITY); - - UART_reception_enable(); - UART_interrupt_enable(); - - extern_interrupt_enable(true); - global_interrupt_enable(true); - - while (1){ - - } - - return 0; -} +#include +#include "uart.h" +#include "../_core/utils.h" +#include "../_core/hardware.h" +#include "../gpio/gpio.h" +#include "../irq/interrupt.h" +#include + +volatile uint8_t leitura; +volatile uint8_t addr = 4; +uint8_t data[8]; + +void UART_IRQHandler(void){ + + UART_buffer_read(data, 8); + + leitura = 1; + UART_reception_enable(); + +} + + +int main(){ + + int i = 0; + leitura = 0; + for(i = 0; i <8 ; i++){ + data[i] = 0; + } + // Para simulação manter 9600 para manter ou alterar baudrate do testbench geração dos sinais + UART_setup(_9600, NO_PARITY); + //Configuração do Buffer em relação ao modo de recebimento + Buffer_setup(IRQ_BYTE_FINAL, 'a'); + //Habilitando as interrupções da UART + UART_reception_enable(); + UART_interrupt_enable(); + //Habilitando as interrupções globais + extern_interrupt_enable(true); + global_interrupt_enable(true); + + while (1){ + //Tratameno da flag que é ativada na função UART IRQ HANDLER + if(leitura == 1){ + for(i = 0; i <8 ; i++){ + UART_write(data[i]); + } + leitura = 0; + } + } + + return 0; +} \ No newline at end of file diff --git a/software/uart/uart.c b/software/uart/uart.c index 78d5e341..376b8953 100644 --- a/software/uart/uart.c +++ b/software/uart/uart.c @@ -1,71 +1,101 @@ -/* - * uart.h - * - * Created on: July 1, 2019 - * Author: Marcos Vinícius Leal da Silva e - * Modified: Daniel Pereira -* Modified: Renan Augusto Starke - * - * Instituto Federal de Santa Catarina - * - * UART functions - * - write - * - send - * - read - * - (...) - * - */ - -#include -#include "uart.h" -#include "../_core/hardware.h" - -void UART_write(uint8_t data){ - /* Slow assembly - while (!UART_REGISTER->tx_done); - UART_REGISTER->tx_byte = data; - UART_REGISTER->tx_start = 1; */ - - while (!UART_REGISTER->tx_done); - - /* Fast assembly: less instructions */ - UART_REGISTER->tx_byte = 0; - *((_IO32 *)UART_REGISTER) |= (1 << 16) | data; -} - -void UART_setup(baud_rate_t baud, parity_t parity){ - /* Slow assembly - UART_SETUP_REG->baud_rate = baud; - UART_SETUP_REG->parity = parity; */ - - /* Fast assembly: less instructions */ - *((_IO32 *)UART_REGISTER) &= (~0x0f) << 19; - *((_IO32 *)UART_REGISTER) |= ((baud & 0x03) << 19) | ((0x03 & parity) << 21); -} - -inline void UART_reception_enable(void){ - UART_REGISTER->rx_enable = 1; -} - -inline void UART_interrupt_enable(void){ - UART_REGISTER->rx_irq_enable = 1; -} - -uint8_t UART_read(void){ - uint8_t byte; - - /*Wait for a new byte */ - while (!UART_REGISTER->rx_done); - - /* Read byte */ - byte = UART_REGISTER->rx_byte; - - /* Reenable receiver */ - UART_REGISTER->rx_enable = 1; - - return byte; -} - -inline uint8_t UART_unblocked_read(void){ - return UART_REGISTER->rx_byte; -} +/* + * uart.h + * + * Created on: July 1, 2019 + * Author: Marcos Vinícius Leal da Silva e + * Modified: Daniel Pereira +* Modified: Renan Augusto Starke + * + * Instituto Federal de Santa Catarina + * + * UART functions + * - write + * - send + * - read + * - (...) + * + */ + +#include +#include "uart.h" +#include "../_core/hardware.h" + +void UART_write(uint8_t data){ + /* Slow assembly + while (!UART_REGISTER->tx_done); + UART_REGISTER->tx_byte = data; + UART_REGISTER->tx_start = 1; */ + + while (!UART_REGISTER->tx_done); + + /* Fast assembly: less instructions */ + UART_REGISTER->tx_byte = 0; + *((_IO32 *)UART_REGISTER) |= (1 << 16) | data; +} + +void UART_setup(baud_rate_t baud, parity_t parity){ + /* Slow assembly + UART_SETUP_REG->baud_rate = baud; + UART_SETUP_REG->parity = parity; */ + + /* Fast assembly: less instructions */ + *((_IO32 *)UART_REGISTER) &= (~0x0f) << 19; + *((_IO32 *)UART_REGISTER) |= ((baud & 0x03) << 19) | ((0x03 & parity) << 21); +} + +void Buffer_setup(buffer_t buffer_type, uint8_t config_byte){ + if(buffer_type == 0){ + if(0 < config_byte < 8){ + UART_REGISTER->num_bytes_irq = config_byte; + UART_REGISTER->byte_final = 0; + }else{ + UART_REGISTER->num_bytes_irq = 1; + UART_REGISTER->byte_final = 0; + } + }else{ + UART_REGISTER->byte_final = config_byte; + UART_REGISTER->num_bytes_irq = 0; + } + UART_REGISTER->irq_mode = buffer_type; +} + +void UART_buffer_read(uint8_t* vetor, uint8_t size){ + // tamanho maximo do buffer é de 8 bytes + size = size & 0x07; + for(uint8_t i = 0; i < size; i++){ + vetor[i] = UART_REGISTER->buffer_rx[i]; + } + +} + +inline void UART_reception_enable(void){ + UART_REGISTER->rx_enable = 1; +} + +inline void UART_interrupt_enable(void){ + UART_REGISTER->rx_irq_enable = 1; +} + +inline void UART_reception_disable(void){ + UART_REGISTER->rx_enable = 0; +} + +uint8_t UART_read(void){ + uint8_t byte; + + /*Wait for a new byte */ + while (!UART_REGISTER->rx_done); + + /* Read byte */ + byte = UART_REGISTER->rx_byte; + + /* Reenable receiver */ + UART_REGISTER->rx_enable = 1; + + return byte; +} + +inline uint8_t UART_unblocked_read(void){ + return UART_REGISTER->rx_byte; +} + diff --git a/software/uart/uart.h b/software/uart/uart.h index e98a601d..a3f0771c 100644 --- a/software/uart/uart.h +++ b/software/uart/uart.h @@ -1,59 +1,72 @@ -/* - * uart.h - * - * Created on: July 1, 2019 - * Author: Marcos Vinícius Leal da Silva e Daniel Pereira - * Modified: Renan Augusto Starke - * - * Instituto Federal de Santa Catarina - * - * UART functions - * - write - * - setup - * - read - * - (...) - * - */ - -#ifndef __UART_H -#define __UART_H - -#include -#include "../_core/hardware.h" - -typedef enum baud_rates_config { - _38400, - _19200, - _9600, - _4800 -} baud_rate_t; - -typedef enum parity_config { - NO_PARITY, - ODD_PARITY, - EVEN_PARITY -} parity_t; - -void UART_write(uint8_t data); -void UART_setup(baud_rate_t baud, parity_t parity); -void UART_interrupt_enable(void); -void UART_reception_enable(void); -uint8_t UART_read(void); -uint8_t UART_unblocked_read(void); - -typedef struct { - _IO8 tx_byte; /*!< Data to transfer. */ - _IO8 rx_byte; /*!< Data received. */ - _IO32 tx_start : 1; /*!< Start Transmission. Bit 16. */ - _IO32 tx_done : 1; /*!< Transmission done flag. Bit 17. */ - _IO32 rx_done : 1; /*!< Reception done flag. Bit 18 */ - _IO32 baud_rate : 2; /*!< Baud rate config. Bits 19 e 20. */ - _IO32 parity : 2; /*!< Parity config. Bit 21 and 22. */ - _IO32 rx_enable : 1; /*!< Reception transceiver enable. Bit 23. */ - _IO32 rx_irq_enable : 1; /*!< Reception interrupt enable. Bit 24. */ - _IO32 tx_irq_enable : 1; /*!< Transmission done interrupt enable. Bit 25 */ -} UART_REG_TYPE; - -#define UART_REGISTER ((UART_REG_TYPE *) &UART_BASE_ADDRESS) - -#endif // __UART_H +/* + * uart.h + * + * Created on: July 1, 2019 + * Author: Marcos Vinícius Leal da Silva e Daniel Pereira + * Modified: Renan Augusto Starke + * + * Instituto Federal de Santa Catarina + * + * UART functions + * - write + * - setup + * - read + * - (...) + * + */ + +#ifndef __UART_H +#define __UART_H + +#include +#include "../_core/hardware.h" + +typedef enum baud_rates_config { + _38400, + _19200, + _9600, + _4800 +} baud_rate_t; + +typedef enum parity_config { + NO_PARITY, + ODD_PARITY, + EVEN_PARITY +} parity_t; + +typedef enum irq_buffer_config { + IRQ_LENGTH, + IRQ_BYTE_FINAL +} buffer_t; + +void UART_write(uint8_t data); +void UART_setup(baud_rate_t baud, parity_t parity); +void Buffer_setup(buffer_t buffer_type, uint8_t config_byte); +void UART_interrupt_enable(void); +void UART_reception_enable(void); +void UART_reception_disable(void); +uint8_t UART_read(void); +uint8_t UART_unblocked_read(void); +void UART_buffer_read(uint8_t* vetor, uint8_t size); + +typedef struct { + _IO8 tx_byte; /*!< Data to transfer. */ + _IO8 rx_byte; /*!< Data received. */ + _IO32 tx_start : 1; /*!< Start Transmission. Bit 16. */ + _IO32 tx_done : 1; /*!< Transmission done flag. Bit 17. */ + _IO32 rx_done : 1; /*!< Reception done flag. Bit 18 */ + _IO32 baud_rate : 2; /*!< Baud rate config. Bits 19 e 20. */ + _IO32 parity : 2; /*!< Parity config. Bit 21 and 22. */ + _IO32 rx_enable : 1; /*!< Reception transceiver enable. Bit 23. */ + _IO32 rx_irq_enable : 1; /*!< Reception interrupt enable. Bit 24. */ + _IO32 tx_irq_enable : 1; /*!< Transmission done interrupt enable. Bit 25 */ + _IO32 _padding : 5; /*Ajuste de variavel para alinhar a memoria Bit 26 ao 30*/ + _IO32 irq_mode : 1; /*Configuração para o modo de recepção Bit 31*/ + _IO8 buffer_rx[8]; /*Definição do Buffer para recepção. Duas words 1 e 2*/ + _IO8 num_bytes_irq; /*Numero de bytes para gerar uma interrupção. Bit 0 a 7 word 3*/ + _IO8 byte_final; /*É o byte que determina o final do pacote serial. Bit 8 a 15 word 3*/ +} UART_REG_TYPE; + +#define UART_REGISTER ((UART_REG_TYPE *) &UART_BASE_ADDRESS) + +#endif // __UART_H