diff --git a/memory/iodatabusmux.vhd b/memory/iodatabusmux.vhd
index d2cc3c22..5504cb24 100644
--- a/memory/iodatabusmux.vhd
+++ b/memory/iodatabusmux.vhd
@@ -21,15 +21,15 @@ entity iodatabusmux is
         ddata_r_adc             : in  std_logic_vector(31 downto 0);
         ddata_r_i2c             : in  std_logic_vector(31 downto 0);
         ddata_r_timer           : in  std_logic_vector(31 downto 0);
-        ddata_r_dif_fil          : in  std_logic_vector(31 downto 0);
+        ddata_r_dif_fil         : in  std_logic_vector(31 downto 0);
         ddata_r_stepmot         : in  std_logic_vector(31 downto 0);
         ddata_r_lcd             : in  std_logic_vector(31 downto 0);
         ddata_r_nn_accelerator  : in   std_logic_vector(31 downto 0);
-        ddata_r_fir_fil           :   in   std_logic_vector(31 downto 0);
-        ddata_r_spwm           :   in   std_logic_vector(31 downto 0);
-        ddata_r_crc		         : in  std_logic_vector(31 downto 0);
-        ddata_r_key        :   in   std_logic_vector(31 downto 0);
-        ddata_r_deb_gpio            : in  std_logic_vector(31 downto 0);
+        ddata_r_fir_fil         : in   std_logic_vector(31 downto 0);
+        ddata_r_spwm            : in   std_logic_vector(31 downto 0);
+        ddata_r_crc		        : in  std_logic_vector(31 downto 0);
+        ddata_r_key             : in   std_logic_vector(31 downto 0);
+        ddata_r_accelerometer   : in  std_logic_vector(31 downto 0);
         -- Mux 
         ddata_r_periph   : out std_logic_vector(31 downto 0) --! Connect to data bus mux
     );
@@ -55,7 +55,7 @@ begin
         ddata_r_key when x"000E",
         ddata_r_crc when x"000F",
         ddata_r_spwm  when x"0011",
-        ddata_r_deb_gpio when x"0012",
+        ddata_r_accelerometer when x"0012",
         -- Add new io peripherals here
         (others => '0') when others;
 end architecture RTL;
diff --git a/memory/iram_quartus.vhd b/memory/iram_quartus.vhd
index 277f6319..d4e23f9a 100644
--- a/memory/iram_quartus.vhd
+++ b/memory/iram_quartus.vhd
@@ -68,7 +68,7 @@ BEGIN
 		intended_device_family => "MAX 10",
     
 		-- Specify here core software binary
-		init_file => "../../software/quartus_blink.hex",
+		init_file => "./software/quartus_blink.hex",
 		-- init_file => "./software/irq/quartus_irq_example.hex",
 		-- init_file => "./software/irq/quartus_irq_example.hex",
 
diff --git a/peripherals/accelerometer/sint_core_no/de10_lite.qsf b/peripherals/accelerometer/sint_core_no/de10_lite.qsf
index 1fbe6143..3daab869 100644
--- a/peripherals/accelerometer/sint_core_no/de10_lite.qsf
+++ b/peripherals/accelerometer/sint_core_no/de10_lite.qsf
@@ -4,9 +4,9 @@
 #============================================================
 set_global_assignment -name FAMILY "MAX 10"
 set_global_assignment -name DEVICE 10M50DAF484C7G
-set_global_assignment -name TOP_LEVEL_ENTITY de10_lite
+set_global_assignment -name TOP_LEVEL_ENTITY de10_lite_acc_no_core
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
-set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:41:06  APRIL 06, 2020"
 
 
@@ -27,15 +27,11 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 
 
 # CLOCK
 #============================================================
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 -disable
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50
 set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 -disable
 set_location_assignment PIN_N5 -to ADC_CLK_10 -disable
 set_location_assignment PIN_P11 -to MAX10_CLK1_50
@@ -126,54 +122,6 @@ set_location_assignment PIN_V20 -to DRAM_WE_N -disable
 
 # SEG7
 #============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
 set_location_assignment PIN_C14 -to HEX0[0]
 set_location_assignment PIN_E15 -to HEX0[1]
 set_location_assignment PIN_C15 -to HEX0[2]
@@ -226,7 +174,6 @@ set_location_assignment PIN_L19 -to HEX5[7]
 
 # KEY
 #============================================================
-set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]
 set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1] -disable
 set_location_assignment PIN_B8 -to KEY[0]
 set_location_assignment PIN_A7 -to KEY[1] -disable
@@ -234,16 +181,6 @@ set_location_assignment PIN_A7 -to KEY[1] -disable
 
 # LED
 #============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
 set_location_assignment PIN_A8 -to LEDR[0]
 set_location_assignment PIN_A9 -to LEDR[1]
 set_location_assignment PIN_A10 -to LEDR[2]
@@ -314,12 +251,6 @@ set_location_assignment PIN_N1 -to VGA_VS -disable
 
 # Accelerometer
 #============================================================
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2]
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI
-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO
 set_location_assignment PIN_AB16 -to GSENSOR_CS_N
 set_location_assignment PIN_Y14 -to GSENSOR_INT[1]
 set_location_assignment PIN_Y13 -to GSENSOR_INT[2]
@@ -375,4 +306,73 @@ set_global_assignment -name VHDL_FILE ../spi_master.vhd
 set_global_assignment -name VHDL_FILE ../accelerometer_adxl345.vhd
 set_global_assignment -name VHDL_FILE de10_lite.vhd
 set_global_assignment -name SDC_FILE de10_lite.sdc
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/peripherals/accelerometer/sint_core_no/de10_lite.sdc b/peripherals/accelerometer/sint_core_no/de10_lite.sdc
index 970e0f20..2a4c5969 100644
--- a/peripherals/accelerometer/sint_core_no/de10_lite.sdc
+++ b/peripherals/accelerometer/sint_core_no/de10_lite.sdc
@@ -6,7 +6,6 @@
 #**************************************************************
 # Create Clock
 #**************************************************************
-create_clock -period "10.0 MHz" [get_ports ADC_CLK_10]
 create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]
 create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50]
 
diff --git a/peripherals/accelerometer/sint_core_no/de10_lite.vhd b/peripherals/accelerometer/sint_core_no/de10_lite.vhd
index d2d009e3..b526aaec 100644
--- a/peripherals/accelerometer/sint_core_no/de10_lite.vhd
+++ b/peripherals/accelerometer/sint_core_no/de10_lite.vhd
@@ -1,96 +1,96 @@
 -- -- bibliotecas -- -- 
 library ieee;
-   use ieee.std_logic_1164.all;
-   use ieee.numeric_std.all; -- unsigned()
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all; -- unsigned()
 
 -- -- interfaces de10_lite (entradas, saidas) -- --
-entity de10_lite is
-   port (
-     MAX10_CLK1_50 :  in std_logic;
+entity de10_lite_acc_no_core is
+    port (
+        MAX10_CLK1_50 :  in std_logic;
         KEY :  in std_logic_vector(0 downto 0);
-    GSENSOR_SDO :  in std_logic;
-   GSENSOR_CS_N : out std_logic;
-   GSENSOR_SCLK : out std_logic;
-    GSENSOR_SDI : out std_logic;
-         HEX0 : out std_logic_vector(7 downto 0); 
-       HEX1 : out std_logic_vector(7 downto 0);
-       HEX2 : out std_logic_vector(7 downto 0);
-       HEX3 : out std_logic_vector(7 downto 0);
-       HEX4 : out std_logic_vector(7 downto 0);
-       HEX5 : out std_logic_vector(7 downto 0)
-   );
-end de10_lite;
+        GSENSOR_SDO :  in std_logic;
+        GSENSOR_CS_N : out std_logic;
+        GSENSOR_SCLK : out std_logic;
+        GSENSOR_SDI : out std_logic;
+        HEX0 : out std_logic_vector(7 downto 0);
+        HEX1 : out std_logic_vector(7 downto 0);
+        HEX2 : out std_logic_vector(7 downto 0);
+        HEX3 : out std_logic_vector(7 downto 0);
+        HEX4 : out std_logic_vector(7 downto 0);
+        HEX5 : out std_logic_vector(7 downto 0)
+    );
+end de10_lite_acc_no_core;
 
 
 -- -- interligacoes (entidade e componentes) -- --
-architecture rtl of de10_lite is
-   component source_and_probe is
-      port (         
-         source : out std_logic_vector(39 downto 0);
-         probe  : in  std_logic_vector(39 downto 0) := (others => 'X')
-      );
-   end component source_and_probe;
+architecture rtl of de10_lite_acc_no_core is
+    component source_and_probe is
+        port (
+            source : out std_logic_vector(39 downto 0);
+            probe  : in  std_logic_vector(39 downto 0) := (others => 'X')
+        );
+    end component source_and_probe;
+
+    signal data_bcd_x : unsigned(15 downto 0);
+    signal data_bcd_y : unsigned(15 downto 0);
+
+    signal source : std_logic_vector(39 downto 0);
+    signal probe  : std_logic_vector(39 downto 0);
 
-  signal data_bcd_x : unsigned(15 downto 0);
-  signal data_bcd_y : unsigned(15 downto 0);  
-  
-  signal source : std_logic_vector(39 downto 0);
-  signal probe  : std_logic_vector(39 downto 0);
-  
-  signal axi_x : STD_LOGIC_VECTOR(15 DOWNTO 0);
-  signal axi_y : STD_LOGIC_VECTOR(15 DOWNTO 0);
-  signal axi_z : STD_LOGIC_VECTOR(15 DOWNTO 0);
+    signal axi_x : STD_LOGIC_VECTOR(15 DOWNTO 0);
+    signal axi_y : STD_LOGIC_VECTOR(15 DOWNTO 0);
+    signal axi_z : STD_LOGIC_VECTOR(15 DOWNTO 0);
 
 begin
 
-   -- -- -- instanciar componente -- -- --
-   --sp_external : component source_and_probe
-   --port map(
-   --   source => source, --sources.source
-   --   probe  => probe   --probes.probe
-   --);
+    -- -- -- instanciar componente -- -- --
+    --sp_external : component source_and_probe
+    --port map(
+    --   source => source, --sources.source
+    --   probe  => probe   --probes.probe
+    --);
 
-  -- instatiation: accelerometer
-  e_accelerometer : entity work.accelerometer_adxl345
-    port map(
-      clk     => MAX10_CLK1_50, 
-      rst     => NOT(KEY(0)),
-      miso    => GSENSOR_SDO, 	
-      sclk    => GSENSOR_SCLK,		
-      ss_n(0) => GSENSOR_CS_N, 		
-      mosi    => GSENSOR_SDI, 
-      axi_x   => axi_x, 
-      axi_y   => axi_y, 
-      axi_z   => axi_z
-    );
+    -- instatiation: accelerometer
+    e_accelerometer : entity work.accelerometer_adxl345
+        port map(
+            clk     => MAX10_CLK1_50,
+            rst     => NOT(KEY(0)),
+            miso    => GSENSOR_SDO,
+            sclk    => GSENSOR_SCLK,
+            ss_n(0) => GSENSOR_CS_N,
+            mosi    => GSENSOR_SDI,
+            axi_x   => axi_x,
+            axi_y   => axi_y,
+            axi_z   => axi_z
+        );
+
+    -- bin to bcd
+    -- x
+    bcd_x : entity work.bin_to_bcd
+        port map( num_bin => "0000000" & axi_x(8 downto 2) & "00", num_signal => axi_x(15), num_bcd  => data_bcd_x );
+    -- y
+    bcd_y : entity work.bin_to_bcd
+        port map( num_bin => "0000000" & axi_y(8 downto 2) & "00", num_signal => axi_y(15), num_bcd  => data_bcd_y );
 
-  -- bin to bcd
-  -- x
-  bcd_x : entity work.bin_to_bcd    
-    port map( num_bin => "0000000" & axi_x(8 downto 2) & "00", num_signal => axi_x(15), num_bcd  => data_bcd_x );  
-  -- y
-  bcd_y : entity work.bin_to_bcd 
-    port map( num_bin => "0000000" & axi_y(8 downto 2) & "00", num_signal => axi_y(15), num_bcd  => data_bcd_y );  
 
+    -- bcd to display 7 seg.
+    -- X
+    seg7_hex0 : entity work.bcd_to_7seg
+        port map( input => data_bcd_x( 3 downto  0), num_signal => '0'               , seg7  => HEX0 );
+    seg7_hex1 : entity work.bcd_to_7seg
+        port map( input => data_bcd_x( 7 downto  4), num_signal => '0'               , seg7  => HEX1 );
+    seg7_hex2 : entity work.bcd_to_7seg
+        port map( input => data_bcd_x(11 downto  8), num_signal => axi_x(15), seg7  => HEX2 );
 
-  -- bcd to display 7 seg.
-  -- X
-  seg7_hex0 : entity work.bcd_to_7seg 
-    port map( input => data_bcd_x( 3 downto  0), num_signal => '0'               , seg7  => HEX0 );  
-  seg7_hex1 : entity work.bcd_to_7seg 
-    port map( input => data_bcd_x( 7 downto  4), num_signal => '0'               , seg7  => HEX1 );
-  seg7_hex2 : entity work.bcd_to_7seg 
-    port map( input => data_bcd_x(11 downto  8), num_signal => axi_x(15), seg7  => HEX2 );
+    -- Y
+    seg7_hex3 : entity work.bcd_to_7seg
+        port map( input => data_bcd_y( 3 downto  0), num_signal => '0'               , seg7  => HEX3 );
+    seg7_hex4 : entity work.bcd_to_7seg
+        port map( input => data_bcd_y( 7 downto  4), num_signal => '0'               , seg7  => HEX4 );
+    seg7_hex5_p : entity work.bcd_to_7seg
+        port map( input => data_bcd_y(11 downto  8), num_signal => axi_y(15), seg7  => HEX5 );
 
-  -- Y
-  seg7_hex3 : entity work.bcd_to_7seg 
-    port map( input => data_bcd_y( 3 downto  0), num_signal => '0'               , seg7  => HEX3 );
-  seg7_hex4 : entity work.bcd_to_7seg 
-    port map( input => data_bcd_y( 7 downto  4), num_signal => '0'               , seg7  => HEX4 );  
-  seg7_hex5_p : entity work.bcd_to_7seg 
-    port map( input => data_bcd_y(11 downto  8), num_signal => axi_y(15), seg7  => HEX5 );  
-	 
-	 probe(0) <= KEY(0);
-	 probe(16 downto 1) <= axi_z;
+    probe(0) <= KEY(0);
+    probe(16 downto 1) <= axi_z;
 
 end;
\ No newline at end of file
diff --git a/peripherals/accelerometer/sint_core_yes/de10_lite.qsf b/peripherals/accelerometer/sint_core_yes/de10_lite.qsf
index 0e2f6738..b0738690 100644
--- a/peripherals/accelerometer/sint_core_yes/de10_lite.qsf
+++ b/peripherals/accelerometer/sint_core_yes/de10_lite.qsf
@@ -4,9 +4,9 @@
 #============================================================
 set_global_assignment -name FAMILY "MAX 10"
 set_global_assignment -name DEVICE 10M50DAF484C7G
-set_global_assignment -name TOP_LEVEL_ENTITY de10_lite
+set_global_assignment -name TOP_LEVEL_ENTITY de10_lite_acc_core
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
-set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:49:34  JUNE 20, 2019"
 
 
@@ -223,9 +223,6 @@ set_location_assignment PIN_F16 -to ARDUINO_RESET_N
 # OTHERS
 #============================================================
 set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name VHDL_FILE ../../gpio/led_displays.vhd
 set_global_assignment -name VHDL_FILE ../../../memory/iodatabusmux.vhd
 set_global_assignment -name VHDL_FILE ../../gpio/gpio.vhd
@@ -257,4 +254,7 @@ set_global_assignment -name VHDL_FILE ../../../alu/m/M.vhd
 set_global_assignment -name VHDL_FILE ../../../alu/alu_types.vhd
 set_global_assignment -name VHDL_FILE ../../../alu/alu.vhd
 set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/peripherals/accelerometer/sint_core_yes/de10_lite.vhd b/peripherals/accelerometer/sint_core_yes/de10_lite.vhd
index a07f7659..9770c014 100644
--- a/peripherals/accelerometer/sint_core_yes/de10_lite.vhd
+++ b/peripherals/accelerometer/sint_core_yes/de10_lite.vhd
@@ -1,10 +1,17 @@
+-------------------------------------------------------------------
+-- Name        : de0_lite.vhd
+-- Author      :
+-- Version     : 0.1
+-- Copyright   : Departamento de Eletrônica, Florianópolis, IFSC
+-- Description : Projeto base DE10-Lite
+-------------------------------------------------------------------
 
 library ieee;
     use ieee.std_logic_1164.all;
     use ieee.numeric_std.all;
     use work.decoder_types.all;
 
-entity de10_lite is
+entity de10_lite_acc_core is
       generic (
         --! Num of 32-bits memory words
         IMEMORY_WORDS : integer := 1024;  --!= 4K (1024 * 4) bytes
@@ -64,9 +71,9 @@ entity de10_lite is
         ARDUINO_IO: inout std_logic_vector(15 downto 0);
         ARDUINO_RESET_N: inout std_logic
     );
-end de10_lite;
+end de10_lite_acc_core;
 
-architecture rtl of de10_lite is
+architecture rtl of de10_lite_acc_core is
   -- chip select
   constant MY_CHIPSELECT   : std_logic_vector(1 downto 0) := "10";
   constant MY_ACCELEROMETER_ADDRESS : unsigned(15 downto 0) := x"0120";
diff --git a/peripherals/gpio/debouncer.vhd.bak b/peripherals/gpio/debouncer.vhd.bak
deleted file mode 100644
index 567ef6e1..00000000
--- a/peripherals/gpio/debouncer.vhd.bak
+++ /dev/null
@@ -1,81 +0,0 @@
--------------------------------------------------------
---! @file
---! @brief RISCV Simple GPIO module
---         RAM mapped general purpose I/O
-
---! @Todo: Module should mask bytes (Word, half word and byte access)
---         Daddress shoud be unsgined
---        
--------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity debouncer is
-
-    generic (
-        --! Chip selec	
-        SYS_FREQ 		: integer := 1; 			-- em megahertz
-        COUNT 			: integer := 5				--
-    );
-
-    port(
-        clk : in std_logic;
-        rst : in std_logic;
-
-        -- hardware input/output signals
-        input  : in std_logic;
-        output  : out std_logic
-
-    );
-
-
-end entity debouncer;
-
-architecture RTL_gpio of debouncer is
-    signal max_v : unsigned(31 downto 0);
-begin
-    debouncer: process(clk, rst)
-        variable count: unsigned(31 downto 0);
-    begin
-        if rst = '1' then
-            output <= '0';
-            --max_v <= to_unsigned(SYS_FREQ*COUNT, max_v'length);
-        else
-            if rising_edge(clk) then
-                if (input = '1') then
-                    if max_v = "00000000000000000000000000000000" then
-                    --output <= '1';
-                    else
-                        max_v <= max_v - 1;
-                    end if;
-                else
-                    --max_v <= to_unsigned(SYS_FREQ*COUNT, max_v'length);
-                    --output <= '0';
-                end if;
-            end if;
-        end if;
-    end process;
-    debouncer2: process(clk, rst)
-        variable count: unsigned(11 downto 0);
-        variable vetor: unsigned(11 downto 0);
-    begin
-        if rst = '1' then
-            output <= '0';
-            count := to_unsigned(0, count'length);
-        else
-            if rising_edge(clk) then
-                count := count sll 1;
-                vetor := (vetor and (not count));
-                if input = '1' then
-                    vetor := vetor or count;
-                end if;
-                if ((vetor = "111111111111") or (vetor = "000000000000")) then -- se os ultimos 12 sao iguais
-                    output <= input;
-                end if;
-            end if;
-        end if;
-    end process;
-
-end architecture RTL_gpio;
diff --git a/peripherals/gpio/sint/de10_lite/de0_lite.vhd b/peripherals/gpio/sint/de10_lite/de0_lite.vhd
index 9837387c..1e46d0be 100644
--- a/peripherals/gpio/sint/de10_lite/de0_lite.vhd
+++ b/peripherals/gpio/sint/de10_lite/de0_lite.vhd
@@ -11,7 +11,7 @@ use ieee.numeric_std.all;
 
 use work.decoder_types.all;
 
-entity de0_lite is
+entity de0_lite_gpio is
     generic (
         --! Num of 32-bits memory words
         IMEMORY_WORDS : integer := 1024;	--!= 4K (1024 * 4) bytes
@@ -75,7 +75,7 @@ end entity;
 
 
 
-architecture rtl of de0_lite is
+architecture rtl of de0_lite_gpio is
     -- Clocks and reset
     signal clk : std_logic;
     signal rst : std_logic;
@@ -123,10 +123,10 @@ architecture rtl of de0_lite is
     signal ddata_r_lcd : std_logic_vector(31 downto 0);
     signal ddata_r_nn_accelerator : std_logic_vector(31 downto 0);
     signal ddata_r_fir_fil : std_logic_vector(31 downto 0);
-    signal ddata_r_spwm           :      std_logic_vector(31 downto 0);
-    signal  ddata_r_crc		         :   std_logic_vector(31 downto 0);
-    signal  ddata_r_key        :      std_logic_vector(31 downto 0);
-    signal ddata_r_deb_gpio : std_logic_vector(31 downto 0);
+    signal ddata_r_spwm : std_logic_vector(31 downto 0);
+    signal ddata_r_crc : std_logic_vector(31 downto 0);
+    signal ddata_r_key : std_logic_vector(31 downto 0);
+    signal ddata_r_accelerometer : std_logic_vector(31 downto 0);
 
     -- Interrupt Signals
     signal interrupts : std_logic_vector(31 downto 0);
@@ -251,24 +251,10 @@ begin
             ddata_r_spwm  		=> ddata_r_spwm,
             ddata_r_crc			=> ddata_r_crc,
             ddata_r_key       => ddata_r_key,
-            ddata_r_deb_gpio     => ddata_r_deb_gpio
+            ddata_r_accelerometer     => ddata_r_accelerometer
         );
-
-    deb_gpio: entity work.gpio_deb
-        port map(
-            clk      => clk,
-            rst      => rst,
-            daddress => daddress,
-            ddata_w  => ddata_w,
-            ddata_r  => ddata_r_deb_gpio, 
-            d_we     => d_we,
-            d_rd     => d_rd,
-            dcsel    => dcsel,
-            dmask    => dmask,
-            input    => gpio_input,
-            output   => gpio_output 
-        );
-    generic_gpio: entity work.gpio
+
+	  generic_gpio: entity work.gpio	    
         port map(
             clk      => clk,
             rst      => rst,
@@ -280,15 +266,15 @@ begin
             dcsel    => dcsel,
             dmask    => dmask,
             input    => gpio_input,
-            --output   => gpio_output, -- deixar esse comentado para utilizar o deb gpio
+            output   => gpio_output,
             gpio_interrupts => gpio_interrupts
         );
 
     -- Timer instantiation
     timer : entity work.Timer
         generic map(
-            prescaler_size => 16,
-            compare_size   => 32
+            PRESCALER_SIZE => 16,
+            COMPARE_SIZE   => 32
         )
         port map(
             clock       => clk,
diff --git a/peripherals/gpio/sint/de10_lite/de10_lite.qsf b/peripherals/gpio/sint/de10_lite/de10_lite.qsf
index 49098bbd..66263784 100644
--- a/peripherals/gpio/sint/de10_lite/de10_lite.qsf
+++ b/peripherals/gpio/sint/de10_lite/de10_lite.qsf
@@ -39,18 +39,15 @@
 
 set_global_assignment -name FAMILY "MAX 10"
 set_global_assignment -name DEVICE 10M50DAF484C7G
-set_global_assignment -name TOP_LEVEL_ENTITY de0_lite
+set_global_assignment -name TOP_LEVEL_ENTITY de0_lite_gpio
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:49:34  JUNE 20, 2019"
-set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Standard Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
 set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name ENABLE_OCT_DONE ON
@@ -240,4 +237,7 @@ set_global_assignment -name VHDL_FILE ../../../../alu/alu.vhd
 set_global_assignment -name VHDL_FILE de0_lite.vhd
 set_global_assignment -name QIP_FILE pll.qip
 set_global_assignment -name SOURCE_FILE db/de10_lite.cmp.rdb
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/software/accelerometer/Makefile b/software/accelerometer/Makefile
index 980e1547..57b0e5ff 100644
--- a/software/accelerometer/Makefile
+++ b/software/accelerometer/Makefile
@@ -1,5 +1,5 @@
 ifndef RISCV_TOOLS_PREFIX
-RISCV_TOOLS_PREFIX= ../../../gcc/bin/riscv-none-elf-
+RISCV_TOOLS_PREFIX= ../../compiler/gcc/bin/riscv-none-elf-
 
 # Para usar no LSC
 #RISCV_TOOLS_PREFIX = ~/opt/xPacks/@xpack-dev-tools/riscv-none-embed-gcc/10.1.0-1.1.1/.content/bin/riscv-none-embed-
diff --git a/testbench.vhd b/testbench.vhd
index 7d60e4d6..30bb2234 100644
--- a/testbench.vhd
+++ b/testbench.vhd
@@ -90,9 +90,11 @@ architecture RTL of core_main_testbench is
 	signal ddata_r_spwm  :   std_logic_vector(31 downto 0);
 	signal ddata_r_crc : std_logic_vector(31 downto 0);
 	signal ddata_r_key : std_logic_vector(31 downto 0);
+	signal ddata_r_accelerometer : std_logic_vector(31 downto 0);
 
 	-- Timer
 	signal ifcap : std_logic;
+	
 
 begin
 
@@ -218,6 +220,7 @@ begin
             ddata_r_spwm => ddata_r_spwm,
             ddata_r_crc => ddata_r_crc,
             ddata_r_key => ddata_r_key,
+            ddata_r_accelerometer => ddata_r_accelerometer,
             ddata_r_periph   => ddata_r_periph
         );