From c00b34fd868a78a9bde48f0e565c1cb057d4fde1 Mon Sep 17 00:00:00 2001 From: RamonSerafim <64420659+RamonSerafim@users.noreply.github.com> Date: Tue, 10 Sep 2024 15:56:36 -0300 Subject: [PATCH] =?UTF-8?q?Complemento=20para=20perif=C3=A9rico=20SPWM=20(?= =?UTF-8?q?#74)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Add files via upload * Delete peripherals/spwm/testbench_spwm.vdh.vhd * Add files via upload * Complementando periférico SPWM * Complementando periférico SPWM * Complementando periférico SPWM * Complementando periférico SPWM --- peripherals/spwm/README.md | 52 +- peripherals/spwm/sine_values.txt | 102 ++ peripherals/spwm/sint/de10_lite/de10_lite.qsf | 3 +- peripherals/spwm/sint/de10_lite/de10_lite.vhd | 33 +- peripherals/spwm/spwm.vhd | 193 +++- peripherals/spwm/spwm_example_unipolar.png | Bin 0 -> 70556 bytes peripherals/spwm/table_sine.mif | 1025 +++++++++++++++++ peripherals/spwm/table_sine_offset.mif | 1025 +++++++++++++++++ peripherals/spwm/tb_spwm.do | 5 +- peripherals/spwm/tb_spwm.vhd | 37 +- software/spwm/Makefile | 2 +- software/spwm/main_spwm.c | 18 +- 12 files changed, 2446 insertions(+), 49 deletions(-) create mode 100644 peripherals/spwm/spwm_example_unipolar.png create mode 100644 peripherals/spwm/table_sine.mif create mode 100644 peripherals/spwm/table_sine_offset.mif diff --git a/peripherals/spwm/README.md b/peripherals/spwm/README.md index b814a8be..352706e9 100644 --- a/peripherals/spwm/README.md +++ b/peripherals/spwm/README.md @@ -9,7 +9,15 @@ Implementação de um componente VHDL gerador de PWM senoidal a partir da compar - `reset`: sinal de reset do periférico, deve ser conectado ao barramento do `reset` do _core_. -- `sine_spwm`: Saída do pwm senoidal gerado pelo hardware +- `sel_modulation`: Seleciona qual modulação será apresentada na saída. + +- `sine_spwm1`: Saída 1 do pwm senoidal gerado pelo hardware. + +- `sine_spwm2`: Saída 2 do pwm senoidal gerado pelo hardware. + +- `sine_spwm3`: Saída 3 do pwm senoidal gerado pelo hardware. + +- `sine_spwm4`: Saída 4 do pwm senoidal gerado pelo hardware. ## Funcionamento @@ -19,14 +27,48 @@ Os valores da portadora são atualizados a partir de uma tabela de valores da se O valor da moduladora segue a lógica de uma onda triangular de acordo com o valor de contagem máxima e uma variável de fator de multiplicação para que possa ser implementada modulação de amplitude. -É feita a comparaçao entre portadora e moduladora e o sinal pwm é gerado na saída sine_spwm. Observe abaixo a lógica implementada e o exemplo simulado via PSIM. +É feita a comparaçao entre portadora e moduladora e o sinal pwm é gerado nas saídas sine_spwm. É possível selecionar qual modulação será escolhida, Bipolar ou Unipolar. + +Observe abaixo a lógica implementada e o exemplo simulado via PSIM. + +## Modulação Bipolar -- sine_spwm = 1 quando Vseno > Vtriangular -- sine_spwm = 0 quando Vseno < Vtriangular +- sine_spwm1 = 1 quando Vseno > Vtriangular +- sine_spwm1 = 0 quando Vseno < Vtriangular
+Em uma aplicação para inversores monofásicos utilizamos 4 chaves, precisamos apenas de 1 sinal comparado com a tabela e seu complementar. A disposição das chaves ficam exemplificados abaixo:
+
+
+- Chave 1 = Chave 3 = sine_spwm1 = sine_spwm3
+- Chave 2 = Chave 4 = sine_spwm2 = sine_spwm4
+
+## Modulação Unipolar
+
+O modelo de chaveamento segue da mesma forma que a modulação bipolar, porém agora com um sinal defasado.
+
+- sine_spwm1 = 1 quando Vseno > Vtriangular
+- sine_spwm1 = 0 quando Vseno < Vtriangular
+- sine_spwm2 = 1 quando Vseno_offset > Vtriangular
+- sine_spwm2 = 0 quando Vseno_offset < Vtriangular
+
+
+
+
+
+
+Em uma aplicação para inversores monofásicos utilizamos 4 chaves, precisamos de 2 sinais comparado com a tabela e seus complementares. A primeira tabela disponibilizando 1 sinal e seu complementar e a outra tabela sendo defasada 180º da primeira, tendo como resposta 1 sinal e seu complementar A disposição das chaves ficam exemplificados abaixo:
+
+
+
+
+- Chave 1 = sine_spwm1 = a partir de table_sine
+- Chave 2 = sine_spwm2 = a partir de table_sine_offset
+- Chave 3 = sine_spwm3 = complementar de sine_spwm1
+- Chave 4 = sine_spwm4 = complementar de sine_spwm2
+
## Simulação
Os valores a seguir foram gerados no Questa utilizando os arquivos de testbench e também o exemplo de software main_spwm.c encontrado nesse repositório, no caminho software/spwm/.
@@ -44,4 +86,4 @@ Foi aplicado um zoom para mostrar os valores das ondas de referência e portador
## Sugestões
- Testar lógica de modulação de amplitude
- Adequar o componente para N saídas e com a lógica de chaveamento para - aplicação. Exemplos: conversor B6, inversor monofásico
-- Gerar a tabela de valores da senoide em tempo de compilação
\ No newline at end of file
+- Gerar a tabela de valores da senoide em tempo de compilação
diff --git a/peripherals/spwm/sine_values.txt b/peripherals/spwm/sine_values.txt
index c818ef7d..c834048c 100644
--- a/peripherals/spwm/sine_values.txt
+++ b/peripherals/spwm/sine_values.txt
@@ -98,3 +98,105 @@
-6140, -5938, -5735, -5532, -5329, -5126, -4922, -4719, -4515, -4311,
-4107, -3902, -3698, -3493, -3289, -3084, -2879, -2673, -2468, -2263,
-2057, -1852, -1646, -1441, -1235, -1029, -823, -618, -412, -206]
+
+ Tabela defasada 90 graus
+ [ 0, -206, -412, -618, -823, -1029, -1235, -1441, -1646, -1852,
+ -2057, -2263, -2468, -2673, -2879, -3084, -3289, -3493, -3698, -3902,
+ -4107, -4311, -4515, -4719, -4922, -5126, -5329, -5532, -5735, -5938,
+ -6140, -6342, -6544, -6746, -6947, -7148, -7349, -7549, -7749, -7949,
+ -8149, -8348, -8547, -8746, -8944, -9142, -9339, -9536, -9733, -9930,
+ -10126,-10321,-10516,-10711,-10905,-11099,-11293,-11486,-11679,-11871,
+ -12062,-12254,-12444,-12634,-12824,-13013,-13202,-13390,-13578,-13765,
+ -13952,-14138,-14323,-14508,-14692,-14876,-15059,-15242,-15424,-15605,
+ -15786,-15966,-16145,-16324,-16502,-16680,-16857,-17033,-17208,-17383,
+ -17557,-17731,-17904,-18076,-18247,-18418,-18588,-18757,-18925,-19093,
+ -19260,-19426,-19592,-19756,-19920,-20083,-20245,-20407,-20568,-20727,
+ -20886,-21045,-21202,-21359,-21514,-21669,-21823,-21976,-22129,-22280,
+ -22431,-22580,-22729,-22877,-23024,-23170,-23315,-23459,-23602,-23745,
+ -23886,-24027,-24166,-24305,-24442,-24579,-24715,-24849,-24983,-25116,
+ -25247,-25378,-25508,-25637,-25764,-25891,-26017,-26141,-26265,-26388,
+ -26509,-26630,-26749,-26867,-26985,-27101,-27216,-27330,-27443,-27555,
+ -27666,-27776,-27885,-27992,-28099,-28204,-28308,-28411,-28513,-28614,
+ -28714,-28813,-28910,-29006,-29102,-29196,-29289,-29380,-29471,-29560,
+ -29648,-29736,-29821,-29906,-29990,-30072,-30153,-30233,-30312,-30390,
+ -30466,-30541,-30615,-30688,-30759,-30830,-30899,-30967,-31034,-31099,
+ -31163,-31226,-31288,-31349,-31408,-31466,-31523,-31578,-31633,-31686,
+ -31738,-31788,-31837,-31886,-31932,-31978,-32022,-32065,-32107,-32147,
+ -32187,-32225,-32261,-32297,-32331,-32364,-32395,-32425,-32454,-32482,
+ -32509,-32534,-32558,-32580,-32602,-32622,-32640,-32658,-32674,-32689,
+ -32702,-32715,-32726,-32735,-32744,-32751,-32757,-32761,-32764,-32766,
+ -32767,-32766,-32764,-32761,-32757,-32751,-32744,-32735,-32726,-32715,
+ -32702,-32689,-32674,-32658,-32640,-32622,-32602,-32580,-32558,-32534,
+ -32509,-32482,-32454,-32425,-32395,-32364,-32331,-32297,-32261,-32225,
+ -32187,-32147,-32107,-32065,-32022,-31978,-31932,-31886,-31837,-31788,
+ -31738,-31686,-31633,-31578,-31523,-31466,-31408,-31349,-31288,-31226,
+ -31163,-31099,-31034,-30967,-30899,-30830,-30759,-30688,-30615,-30541,
+ -30466,-30390,-30312,-30233,-30153,-30072,-29990,-29906,-29821,-29736,
+ -29648,-29560,-29471,-29380,-29289,-29196,-29102,-29006,-28910,-28813,
+ -28714,-28614,-28513,-28411,-28308,-28204,-28099,-27992,-27885,-27776,
+ -27666,-27555,-27443,-27330,-27216,-27101,-26985,-26867,-26749,-26630,
+ -26509,-26388,-26265,-26141,-26017,-25891,-25764,-25637,-25508,-25378,
+ -25247,-25116,-24983,-24849,-24715,-24579,-24442,-24305,-24166,-24027,
+ -23886,-23745,-23602,-23459,-23315,-23170,-23024,-22877,-22729,-22580,
+ -22431,-22280,-22129,-21976,-21823,-21669,-21514,-21359,-21202,-21045,
+ -20886,-20727,-20568,-20407,-20245,-20083,-19920,-19756,-19592,-19426,
+ -19260,-19093,-18925,-18757,-18588,-18418,-18247,-18076,-17904,-17731,
+ -17557,-17383,-17208,-17033,-16857,-16680,-16502,-16324,-16145,-15966,
+ -15786,-15605,-15424,-15242,-15059,-14876,-14692,-14508,-14323,-14138,
+ -13952,-13765,-13578,-13390,-13202,-13013,-12824,-12634,-12444,-12254,
+ -12062,-11871,-11679,-11486,-11293,-11099,-10905,-10711,-10516,-10321,
+ -10126, -9930, -9733, -9536, -9339, -9142, -8944, -8746, -8547, -8348,
+ -8149, -7949, -7749, -7549, -7349, -7148, -6947, -6746, -6544, -6342,
+ -6140, -5938, -5735, -5532, -5329, -5126, -4922, -4719, -4515, -4311,
+ -4107, -3902, -3698, -3493, -3289, -3084, -2879, -2673, -2468, -2263,
+ -2057, -1852, -1646, -1441, -1235, -1029, -823, -618, -412, -206,
+ 0, 206, 412, 618, 823, 1029, 1235, 1441, 1646, 1852,
+ 2057, 2263, 2468, 2673, 2879, 3084, 3289, 3493, 3698, 3902,
+ 4107, 4311, 4515, 4719, 4922, 5126, 5329, 5532, 5735, 5938,
+ 6140, 6342, 6544, 6746, 6947, 7148, 7349, 7549, 7749, 7949,
+ 8149, 8348, 8547, 8746, 8944, 9142, 9339, 9536, 9733, 9930,
+ 10126, 10321, 10516, 10711, 10905, 11099, 11293, 11486, 11679, 11871,
+ 12062, 12254, 12444, 12634, 12824, 13013, 13202, 13390, 13578, 13765,
+ 13952, 14138, 14323, 14508, 14692, 14876, 15059, 15242, 15424, 15605,
+ 15786, 15966, 16145, 16324, 16502, 16680, 16857, 17033, 17208, 17383,
+ 17557, 17731, 17904, 18076, 18247, 18418, 18588, 18757, 18925, 19093,
+ 19260, 19426, 19592, 19756, 19920, 20083, 20245, 20407, 20568, 20727,
+ 20886, 21045, 21202, 21359, 21514, 21669, 21823, 21976, 22129, 22280,
+ 22431, 22580, 22729, 22877, 23024, 23170, 23315, 23459, 23602, 23745,
+ 23886, 24027, 24166, 24305, 24442, 24579, 24715, 24849, 24983, 25116,
+ 25247, 25378, 25508, 25637, 25764, 25891, 26017, 26141, 26265, 26388,
+ 26509, 26630, 26749, 26867, 26985, 27101, 27216, 27330, 27443, 27555,
+ 27666, 27776, 27885, 27992, 28099, 28204, 28308, 28411, 28513, 28614,
+ 28714, 28813, 28910, 29006, 29102, 29196, 29289, 29380, 29471, 29560,
+ 29648, 29736, 29821, 29906, 29990, 30072, 30153, 30233, 30312, 30390,
+ 30466, 30541, 30615, 30688, 30759, 30830, 30899, 30967, 31034, 31099,
+ 31163, 31226, 31288, 31349, 31408, 31466, 31523, 31578, 31633, 31686,
+ 31738, 31788, 31837, 31886, 31932, 31978, 32022, 32065, 32107, 32147,
+ 32187, 32225, 32261, 32297, 32331, 32364, 32395, 32425, 32454, 32482,
+ 32509, 32534, 32558, 32580, 32602, 32622, 32640, 32658, 32674, 32689,
+ 32702, 32715, 32726, 32735, 32744, 32751, 32757, 32761, 32764, 32766,
+ 32767, 32766, 32764, 32761, 32757, 32751, 32744, 32735, 32726, 32715,
+ 32702, 32689, 32674, 32658, 32640, 32622, 32602, 32580, 32558, 32534,
+ 32509, 32482, 32454, 32425, 32395, 32364, 32331, 32297, 32261, 32225,
+ 32187, 32147, 32107, 32065, 32022, 31978, 31932, 31886, 31837, 31788,
+ 31738, 31686, 31633, 31578, 31523, 31466, 31408, 31349, 31288, 31226,
+ 31163, 31099, 31034, 30967, 30899, 30830, 30759, 30688, 30615, 30541,
+ 30466, 30390, 30312, 30233, 30153, 30072, 29990, 29906, 29821, 29736,
+ 29648, 29560, 29471, 29380, 29289, 29196, 29102, 29006, 28910, 28813,
+ 28714, 28614, 28513, 28411, 28308, 28204, 28099, 27992, 27885, 27776,
+ 27666, 27555, 27443, 27330, 27216, 27101, 26985, 26867, 26749, 26630,
+ 26509, 26388, 26265, 26141, 26017, 25891, 25764, 25637, 25508, 25378,
+ 25247, 25116, 24983, 24849, 24715, 24579, 24442, 24305, 24166, 24027,
+ 23886, 23745, 23602, 23459, 23315, 23170, 23024, 22877, 22729, 22580,
+ 22431, 22280, 22129, 21976, 21823, 21669, 21514, 21359, 21202, 21045,
+ 20886, 20727, 20568, 20407, 20245, 20083, 19920, 19756, 19592, 19426,
+ 19260, 19093, 18925, 18757, 18588, 18418, 18247, 18076, 17904, 17731,
+ 17557, 17383, 17208, 17033, 16857, 16680, 16502, 16324, 16145, 15966,
+ 15786, 15605, 15424, 15242, 15059, 14876, 14692, 14508, 14323, 14138,
+ 13952, 13765, 13578, 13390, 13202, 13013, 12824, 12634, 12444, 12254,
+ 12062, 11871, 11679, 11486, 11293, 11099, 10905, 10711, 10516, 10321,
+ 10126, 9930, 9733, 9536, 9339, 9142, 8944, 8746, 8547, 8348,
+ 8149, 7949, 7749, 7549, 7349, 7148, 6947, 6746, 6544, 6342,
+ 6140, 5938, 5735, 5532, 5329, 5126, 4922, 4719, 4515, 4311,
+ 4107, 3902, 3698, 3493, 3289, 3084, 2879, 2673, 2468, 2263,
+ 2057, 1852, 1646, 1441, 1235, 1029, 823, 618, 412, 206]
diff --git a/peripherals/spwm/sint/de10_lite/de10_lite.qsf b/peripherals/spwm/sint/de10_lite/de10_lite.qsf
index 423d4d5d..47805621 100644
--- a/peripherals/spwm/sint/de10_lite/de10_lite.qsf
+++ b/peripherals/spwm/sint/de10_lite/de10_lite.qsf
@@ -42,7 +42,7 @@ set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY de10_lite
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:49:34 JUNE 20, 2019"
-set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Standard Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -241,4 +241,5 @@ set_global_assignment -name VHDL_FILE de10_lite.vhd
set_global_assignment -name QIP_FILE pll.qip
set_global_assignment -name SOURCE_FILE db/de10_lite.cmp.rdb
set_global_assignment -name VHDL_FILE ../../../gpio/led_displays.vhd
+set_global_assignment -name MIF_FILE output_files/tabela_seno.mif
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/peripherals/spwm/sint/de10_lite/de10_lite.vhd b/peripherals/spwm/sint/de10_lite/de10_lite.vhd
index 32da6db5..deeae1bc 100644
--- a/peripherals/spwm/sint/de10_lite/de10_lite.vhd
+++ b/peripherals/spwm/sint/de10_lite/de10_lite.vhd
@@ -123,8 +123,11 @@ architecture rtl of de10_lite is
signal ddata_r_dig_fil : std_logic_vector(31 downto 0);
signal ddata_r_stepmot : std_logic_vector(31 downto 0);
signal ddata_r_lcd : std_logic_vector(31 downto 0);
- signal ddata_r_nn_accelerator : std_logic_vector(31 downto 0);
- signal ddata_r_fir_fil : std_logic_vector(31 downto 0);
+ signal ddata_r_nn_accelerator : std_logic_vector(31 downto 0);
+ signal ddata_r_fir_fil : std_logic_vector(31 downto 0);
+ signal ddata_r_crc : std_logic_vector(31 downto 0);
+ signal ddata_r_key : std_logic_vector(31 downto 0);
+ signal ddata_r_accelerometer : std_logic_vector(31 downto 0);
-- Interrupt Signals
signal interrupts : std_logic_vector(31 downto 0);
@@ -133,8 +136,12 @@ architecture rtl of de10_lite is
-- I/O signals
signal input_in : std_logic_vector(31 downto 0);
-
signal switching_sine : std_logic;
+
+ --Timer
+ signal ifcap : std_logic ; -- capture flag
+
+ signal sel_modulation : std_logic;
begin
@@ -174,7 +181,11 @@ begin
port map(
clock => clk_50MHz,
reset => rst,
+ sel_modulation => SW(5),
sine_pwm1 => ARDUINO_IO(0),
+ sine_pwm2 => ARDUINO_IO(2),
+ sine_pwm3 => ARDUINO_IO(4),
+ sine_pwm4 => ARDUINO_IO(6),
daddress => daddress,
ddata_w => ddata_w,
ddata_r => ddata_r_spwm,
@@ -217,6 +228,7 @@ begin
-- 0x20000 -> Data memory
-- 0x40000 -> Input/Output generic address space
-- ( ... ) -> ( ... )
+
datamux: entity work.databusmux
port map(
dcsel => dcsel,
@@ -263,10 +275,14 @@ begin
ddata_r_periph => ddata_r_periph,
ddata_r_spwm => ddata_r_spwm,
ddata_r_dif_fil => ddata_r_dig_fil,
- ddata_r_stepmot => ddata_r_stepmot,
- ddata_r_lcd => ddata_r_lcd,
- ddata_r_fir_fil => ddata_r_fir_fil,
- ddata_r_nn_accelerator => ddata_r_nn_accelerator
+ ddata_r_stepmot => ddata_r_stepmot,
+ ddata_r_lcd => ddata_r_lcd,
+ ddata_r_fir_fil => ddata_r_fir_fil,
+ ddata_r_nn_accelerator => ddata_r_nn_accelerator,
+ ddata_r_crc => ddata_r_crc,
+ ddata_r_key => ddata_r_key,
+ ddata_r_accelerometer => ddata_r_accelerometer
+
);
generic_gpio: entity work.gpio
@@ -301,7 +317,8 @@ begin
d_rd => d_rd,
dcsel => dcsel,
dmask => dmask,
- timer_interrupt => timer_interrupt
+ timer_interrupt => timer_interrupt,
+ ifcap => ifcap
);
generic_displays : entity work.led_displays
diff --git a/peripherals/spwm/spwm.vhd b/peripherals/spwm/spwm.vhd
index 5f105edd..cfd8b4a1 100644
--- a/peripherals/spwm/spwm.vhd
+++ b/peripherals/spwm/spwm.vhd
@@ -13,8 +13,12 @@ entity spwm is
-- hardware input/output
clock : in std_logic;
reset : in std_logic;
+ sel_modulation : in std_logic;
sine_pwm1 : out std_logic;
-
+ sine_pwm2 : out std_logic;
+ sine_pwm3 : out std_logic;
+ sine_pwm4 : out std_logic;
+
-- Core data bus signals
daddress : in unsigned(DADDRESS_BUS_SIZE-1 downto 0);
ddata_w : in std_logic_vector(31 downto 0);
@@ -164,9 +168,121 @@ architecture RTL of spwm is
-6140, -5938, -5735, -5532, -5329, -5126, -4922, -4719, -4515, -4311,
-4107, -3902, -3698, -3493, -3289, -3084, -2879, -2673, -2468, -2263,
-2057, -1852, -1646, -1441, -1235, -1029, -823, -618, -412, -206);
+
+ constant sine_table_offset : sine_table_t := ( 0, -206, -412, -618, -823, -1029, -1235, -1441, -1646, -1852,
+ -2057, -2263, -2468, -2673, -2879, -3084, -3289, -3493, -3698, -3902,
+ -4107, -4311, -4515, -4719, -4922, -5126, -5329, -5532, -5735, -5938,
+ -6140, -6342, -6544, -6746, -6947, -7148, -7349, -7549, -7749, -7949,
+ -8149, -8348, -8547, -8746, -8944, -9142, -9339, -9536, -9733, -9930,
+ -10126,-10321,-10516,-10711,-10905,-11099,-11293,-11486,-11679,-11871,
+ -12062,-12254,-12444,-12634,-12824,-13013,-13202,-13390,-13578,-13765,
+ -13952,-14138,-14323,-14508,-14692,-14876,-15059,-15242,-15424,-15605,
+ -15786,-15966,-16145,-16324,-16502,-16680,-16857,-17033,-17208,-17383,
+ -17557,-17731,-17904,-18076,-18247,-18418,-18588,-18757,-18925,-19093,
+ -19260,-19426,-19592,-19756,-19920,-20083,-20245,-20407,-20568,-20727,
+ -20886,-21045,-21202,-21359,-21514,-21669,-21823,-21976,-22129,-22280,
+ -22431,-22580,-22729,-22877,-23024,-23170,-23315,-23459,-23602,-23745,
+ -23886,-24027,-24166,-24305,-24442,-24579,-24715,-24849,-24983,-25116,
+ -25247,-25378,-25508,-25637,-25764,-25891,-26017,-26141,-26265,-26388,
+ -26509,-26630,-26749,-26867,-26985,-27101,-27216,-27330,-27443,-27555,
+ -27666,-27776,-27885,-27992,-28099,-28204,-28308,-28411,-28513,-28614,
+ -28714,-28813,-28910,-29006,-29102,-29196,-29289,-29380,-29471,-29560,
+ -29648,-29736,-29821,-29906,-29990,-30072,-30153,-30233,-30312,-30390,
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+ 29648, 29560, 29471, 29380, 29289, 29196, 29102, 29006, 28910, 28813,
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+ 25247, 25116, 24983, 24849, 24715, 24579, 24442, 24305, 24166, 24027,
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+ 17557, 17383, 17208, 17033, 16857, 16680, 16502, 16324, 16145, 15966,
+ 15786, 15605, 15424, 15242, 15059, 14876, 14692, 14508, 14323, 14138,
+ 13952, 13765, 13578, 13390, 13202, 13013, 12824, 12634, 12444, 12254,
+ 12062, 11871, 11679, 11486, 11293, 11099, 10905, 10711, 10516, 10321,
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+ 8149, 7949, 7749, 7549, 7349, 7148, 6947, 6746, 6544, 6342,
+ 6140, 5938, 5735, 5532, 5329, 5126, 4922, 4719, 4515, 4311,
+ 4107, 3902, 3698, 3493, 3289, 3084, 2879, 2673, 2468, 2263,
+ 2057, 1852, 1646, 1441, 1235, 1029, 823, 618, 412, 206);
+ --signal sine_table : sine_table_t;
+ --signal sine_table_offset : sine_table_t;
signal sine_value : signed(15 downto 0);
+ signal sine_offset_value : signed(15 downto 0);
signal sine_index : natural := sine_resolution-1;
+ signal sine_offset_index : natural := sine_resolution-1;
+
+ -- These lines works with Quartus. MIF is a Memory Initialization file
+ --attribute init_sine_file : string;
+ --attribute init_sine_offset_file : string;
+ -- Quartus uses Project folder to look for mif file.
+ --attribute init_sine_file of sine_table : signal is "../table_sine.mif";
+ --attribute init_sine_offset_file of sine_table_offset : signal is "../table_sine_offset.mif";
begin
@@ -273,6 +389,24 @@ begin
sine_value <= count_temp;
end process;
+ -- Processo que atualiza o valor de seno defasado
+ sine_offset_process: process (clk_sine, reset)
+ variable count_temp : signed(15 downto 0);
+ begin
+ if reset = '1' then
+ count_temp := (others => '0');
+ sine_offset_index <= 0;
+ elsif (rising_edge(clk_sine)) then
+ if sine_offset_index = sine_resolution-1 then
+ sine_offset_index <= 0;
+ else
+ count_temp := to_signed(sine_table_offset(sine_offset_index),16);
+ sine_offset_index <= sine_offset_index + 1;
+ end if;
+ end if;
+ sine_offset_value <= count_temp;
+ end process;
+
-- Processo que faz a contagem da moduladora
modulator_process: process (clk_mod, reset)
variable count_temp : signed(15 downto 0);
@@ -300,18 +434,49 @@ begin
mod_count <= count_temp;
end process;
--- Processo que comparada seno e moduladora
- spwm_process: process (clk_mod, reset)
- begin
- if reset = '1' then
- sine_pwm1 <= '0';
- elsif (rising_edge(clk_mod)) then
- if(sine_value > (scaling_factor*mod_count)) then
- sine_pwm1 <= '1';
- else
- sine_pwm1 <= '0';
- end if;
- end if;
- end process;
+ -- Processo que compara seno e moduladora
+ spwm_process: process (clk_mod, reset)
+ begin
+ if reset = '1' then
+ sine_pwm1 <= '0';
+ sine_pwm2 <= '0';
+ sine_pwm3 <= '0';
+ sine_pwm4 <= '0';
+ elsif rising_edge(clk_mod) then
+ if sel_modulation = '0' then -- Modulação Bipolar
+ if sine_value > (scaling_factor * mod_count) then
+ sine_pwm1 <= '1'; -- Sinal positivo
+ sine_pwm2 <= '0';
+ sine_pwm3 <= '1'; -- Complementar
+ sine_pwm4 <= '0';
+ else
+ sine_pwm1 <= '0';
+ sine_pwm2 <= '1'; -- Complementar
+ sine_pwm3 <= '0';
+ sine_pwm4 <= '1';
+ end if;
+ elsif sel_modulation = '1' then -- Modulação Unipolar
+ -- Tabela sine_value para os primeiros sinais (sem defasagem)
+ if sine_value > (scaling_factor * mod_count) then
+ sine_pwm1 <= '1'; -- Sinal positivo
+ sine_pwm2 <= '0';
+ else
+ sine_pwm1 <= '0';
+ sine_pwm2 <= '1'; -- Complementar
+ end if;
+
+ -- Tabela sine_offset_value para os sinais defasados (180 graus)
+ if sine_offset_value > (scaling_factor * mod_count) then
+ sine_pwm3 <= '1'; -- Sinal positivo
+ sine_pwm4 <= '0';
+ else
+ sine_pwm3 <= '0';
+ sine_pwm4 <= '1'; -- Complementar
+ end if;
+ end if;
+ end if;
+ end process;
+
+
end architecture RTL;
diff --git a/peripherals/spwm/spwm_example_unipolar.png b/peripherals/spwm/spwm_example_unipolar.png
new file mode 100644
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