From 6f28870ea9593a23d2ae66db117467cf4ee082d8 Mon Sep 17 00:00:00 2001
From: Thiago de Lira <49963038+lirahc@users.noreply.github.com>
Date: Tue, 19 Dec 2023 13:55:45 -0300
Subject: [PATCH 1/3] Add files via upload
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Foi atualizado máquina de estados para o sensor ultrassonic HCSR04
---
.../hcsr04_ultrassonic_sensor/HCSR04.vhd | 196 ++++++++++--------
.../hcsr04_ultrassonic_sensor/testbench.do | 4 +-
.../hcsr04_ultrassonic_sensor/testbench2.do | 6 +-
.../hcsr04_ultrassonic_sensor/testbench2.vhd | 114 +++++-----
4 files changed, 180 insertions(+), 140 deletions(-)
diff --git a/peripherals/hcsr04_ultrassonic_sensor/HCSR04.vhd b/peripherals/hcsr04_ultrassonic_sensor/HCSR04.vhd
index 095ba5b6..3d576642 100644
--- a/peripherals/hcsr04_ultrassonic_sensor/HCSR04.vhd
+++ b/peripherals/hcsr04_ultrassonic_sensor/HCSR04.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------
-- Name : HCSR04.vhd
--- Author : Suzi Yousif
+-- Author : Thiago de Lira
-- Description : Ultrassonic Sensor HC-SR04
-------------------------------------------------------------------
library ieee;
@@ -8,94 +8,126 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HCSR04 is
- generic (
- --! Chip selec
- MY_CHIPSELECT : std_logic_vector(1 downto 0) := "10";
- MY_WORD_ADDRESS : unsigned(7 downto 0) := x"10"
- );
-
- port(
- clk : in std_logic;
- rst : in std_logic;
-
- -- Core data bus signals
- -- ToDo: daddress shoud be unsgined
- daddress : in natural;
- ddata_w : in std_logic_vector(31 downto 0);
- ddata_r : out std_logic_vector(31 downto 0);
- d_we : in std_logic;
- d_rd : in std_logic;
- dcsel : in std_logic_vector(1 downto 0); --! Chip select
- -- ToDo: Module should mask bytes (Word, half word and byte access)
- dmask : in std_logic_vector(3 downto 0); --! Byte enable mask
-
- -- hardware input/output signals
- echo : in std_logic;
- Trig : out std_logic
- );
+ generic (
+ --! Chip selec
+ MY_CHIPSELECT : std_logic_vector(1 downto 0) := "10";
+ MY_WORD_ADDRESS : unsigned(7 downto 0) := x"10";
+ DADDRESS_BUS_SIZE : integer := 32
+ );
+
+ port(
+ clk : in std_logic;
+ rst : in std_logic;
+
+ -- Core data bus signals
+ -- ToDo: daddress shoud be unsgined
+ daddress : in unsigned(DADDRESS_BUS_SIZE-1 downto 0);
+ ddata_w : in std_logic_vector(31 downto 0);
+ ddata_r : out std_logic_vector(31 downto 0);
+ d_we : in std_logic;
+ d_rd : in std_logic;
+ dcsel : in std_logic_vector(1 downto 0); --! Chip select
+ -- ToDo: Module should mask bytes (Word, half word and byte access)
+ dmask : in std_logic_vector(3 downto 0); --! Byte enable mask
+
+ -- hardware input/output signals
+ echo : in std_logic;
+ Trig : out std_logic
+ );
end entity HCSR04;
architecture RTL of HCSR04 is
- type state_type is (Idle, Trig_state, Sonic_Burst, Echo_state);
- signal state : state_type;
- signal echo_counter : unsigned (31 downto 0);
- signal echo_wait : unsigned (7 downto 0);
- signal measure_ms : unsigned (31 downto 0);
+ type state_type is (Idle, Trig_state, Sonic_Burst, Echo_state, Register_state);
+ signal state : state_type;
+
+ signal counter : unsigned (31 downto 0);
+
+ signal echo_counter : unsigned (31 downto 0);
+ signal echo_wait : unsigned (7 downto 0);
+ signal measure_ms : unsigned (31 downto 0);
+
+ --
+ constant ECHO_TIMEOUT : integer := 100;
+ constant MEASUREMENT_CYCLE : integer := 600;
+
begin
- -- Input register
- process(clk, rst)
- begin
- if rst = '1' then
- ddata_r <= (others => '0');
- else
- if rising_edge(clk) then
- if (d_rd = '1') and (dcsel = MY_CHIPSELECT) then
- ddata_r <= std_logic_vector(measure_ms);
- end if;
- end if;
- end if;
- end process;
-
- state_transation: process(clk, rst) is
- begin
- if rst = '1' then
- state <= Idle;
- echo_wait <= to_unsigned(0, 8);
- echo_counter <= to_unsigned(0, 32);
- measure_ms <= to_unsigned(0, 32);
- Trig <= '0';
- elsif rising_edge(clk) then
- case state is
- when Idle =>
- Trig <= '0';
- echo_counter <= to_unsigned(0, 32);
- state <= Trig_state;
-
- when Trig_state =>
- Trig <= '1';
- state <= Sonic_Burst;
-
- when Sonic_Burst =>
- Trig <= '0';
- if (echo_wait >= 76) then
- echo_wait <= to_unsigned(0, 8);
- state <= Echo_state;
- else
- echo_wait <= echo_wait + 1;
- state <= Sonic_Burst;
- end if;
+ -- Input register
+ process(clk, rst)
+ begin
+ if rst = '1' then
+ ddata_r <= (others => '0');
+ else
+ if rising_edge(clk) then
+ if (d_rd = '1') and (dcsel = MY_CHIPSELECT) then
+ ddata_r <= std_logic_vector(measure_ms);
+ end if;
+ end if;
+ end if;
+ end process;
+
+ state_transation: process(clk, rst) is
+ begin
+ if rst = '1' then
+ state <= Idle;
+ echo_wait <= to_unsigned(0, 8);
+ echo_counter <= to_unsigned(0, 32);
+
+ measure_ms <= to_unsigned(0, 32);
+ Trig <= '0';
+
+ counter <= (others => '0');
+
+ elsif rising_edge(clk) then
+ case state is
+ when Idle =>
+ Trig <= '0';
+ echo_counter <= to_unsigned(0, 32);
+
+ counter <= (others => '0');
+
+ state <= Trig_state;
+
+ when Trig_state =>
+
+ Trig <= '1';
+
+ counter <= counter + 1;
+ if counter > x"10" then
+ state <= Sonic_Burst;
+ counter <= (others => '0');
+ end if;
+
+ when Sonic_Burst =>
+ Trig <= '0';
+
+ counter <= counter + 1;
+ --if counter > x"0b" then
+
+ if echo <= '1' then
+ state <= Echo_state;
+ counter <= (others => '0');
+ end if;
+
+ if counter > to_unsigned (ECHO_TIMEOUT,counter'length)then
+ state <= Register_State;
+ end if;
+ --end if;
- when Echo_state =>
+ when Echo_state =>
if (echo = '1') then
echo_counter <= echo_counter + 1;
- state <= Echo_state;
- elsif (echo_counter > x"FFFFFF") then
- state <= Idle;
- else
- measure_ms <= echo_counter;
- state <= Idle;
end if;
+
+ counter <= counter + 1;
+ if counter > to_unsigned (MEASUREMENT_CYCLE,counter'length) then
+ state <= Register_State;
+ end if;
+
+ when Register_State =>
+ measure_ms <= echo_counter;
+ state <= Idle;
+
end case;
- end if;
- end process;
+ end if;
+ end process;
end architecture RTL;
diff --git a/peripherals/hcsr04_ultrassonic_sensor/testbench.do b/peripherals/hcsr04_ultrassonic_sensor/testbench.do
index 449ae027..0bbf6f50 100644
--- a/peripherals/hcsr04_ultrassonic_sensor/testbench.do
+++ b/peripherals/hcsr04_ultrassonic_sensor/testbench.do
@@ -33,8 +33,8 @@ vcom ../../core/core.vhd
vcom ../../core/txt_util.vhdl
vcom ../../core/trace_debug.vhd
vcom testbench.vhd
-
-vsim -t ns work.coretestbench
+vsim -voptargs="+acc" -t ns work.coretestbench
+#vsim -t ns work.coretestbench
view wave
add wave -radix binary -label clk /clk
diff --git a/peripherals/hcsr04_ultrassonic_sensor/testbench2.do b/peripherals/hcsr04_ultrassonic_sensor/testbench2.do
index ade9ad66..7dcf2da2 100644
--- a/peripherals/hcsr04_ultrassonic_sensor/testbench2.do
+++ b/peripherals/hcsr04_ultrassonic_sensor/testbench2.do
@@ -13,8 +13,8 @@ vlib work
vcom HCSR04.vhd testbench2.vhd
#Simula (work é o diretorio, testbench é o nome da entity)
-vsim -t ns work.testbench
-
+#vsim -t ns work.testbenchlira
+vsim -voptargs="+acc" -t ns work.testbenchlira
#Mosta forma de onda
view wave
@@ -31,7 +31,7 @@ add wave -label measure_ms -radix unsigned /HCSR04_inst/measure_ms
add wave -label echo_counter -radix unsigned /HCSR04_inst/echo_counter
add wave -label echo_wait -radix unsigned /HCSR04_inst/echo_wait
-run 1000000 ns
+run 10 ms
wave zoomfull
write wave wave.ps
diff --git a/peripherals/hcsr04_ultrassonic_sensor/testbench2.vhd b/peripherals/hcsr04_ultrassonic_sensor/testbench2.vhd
index da719d9a..3cb9cfdd 100644
--- a/peripherals/hcsr04_ultrassonic_sensor/testbench2.vhd
+++ b/peripherals/hcsr04_ultrassonic_sensor/testbench2.vhd
@@ -1,6 +1,6 @@
---------------------------------------------------------------------
-- Name : testbench2.vhd
--- Author : Suzi Yousif
+-- Author : Thiago de Lira
-- Description : A simple testbench for Ultrassonic Sensor HC-SR04.
-- This test was made to check the state machine and
-- the variable 'measure_ms'.
@@ -11,61 +11,69 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-entity testbench is
-end entity testbench;
+entity testbenchlira is
+end entity testbenchlira;
+
+architecture RTL of testbenchlira is
+ signal clk : std_logic;
+ signal rst : std_logic;
+ signal daddress :unsigned(31 downto 0);
+ signal ddata_r : std_logic_vector(31 downto 0);
+ signal ddata_w : std_logic_vector(31 downto 0);
+ signal dmask : std_logic_vector(3 downto 0);
+ signal dcsel : std_logic_vector(1 downto 0);
+ signal d_we : std_logic := '0';
+ signal d_rd : std_logic;
+
+ -- I/O signals
+ signal echo : std_logic;
+ signal Trig : std_logic;
+
-architecture RTL of testbench is
- signal clk : std_logic;
- signal rst : std_logic;
- signal daddress : natural;
- signal ddata_r : std_logic_vector(31 downto 0);
- signal ddata_w : std_logic_vector(31 downto 0);
- signal dmask : std_logic_vector(3 downto 0);
- signal dcsel : std_logic_vector(1 downto 0);
- signal d_we : std_logic := '0';
- signal d_rd : std_logic;
-
- -- I/O signals
- signal echo : std_logic;
- signal Trig : std_logic;
begin
- HCSR04_inst : entity work.HCSR04
- generic map(
- MY_CHIPSELECT => "10",
- MY_WORD_ADDRESS => x"10"
- )
- port map(
- clk => clk,
- rst => rst,
- daddress => daddress,
- ddata_w => ddata_w,
- ddata_r => ddata_r,
- d_we => d_we,
- d_rd => d_rd,
- dcsel => dcsel,
- dmask => dmask,
- echo => echo,
- Trig => Trig
- );
+ HCSR04_inst : entity work.HCSR04
+ generic map(
+ MY_CHIPSELECT => "10",
+ MY_WORD_ADDRESS => x"10"
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => ddata_r,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+ echo => echo,
+ Trig => Trig
+
+ );
+
+ clock_driver : process
+ constant period : time := 10000 ns;
+
+ -- Simulation constants
+ constant ECHO_TIMEOUT : integer := 1000;
+ constant MEASUREMENT_CYCLE : integer := 60000;
+ begin
+ clk <= '0';
+ wait for period / 2;
+ clk <= '1';
+ wait for period / 2;
+ end process clock_driver;
+
+ reset : process is
+ begin
+ rst <= '1';
+ wait for 10000 ns;
+ rst <= '0';
+ wait;
+ end process reset;
+ -- echo <= '0', '1' after 800000 ns, '0' after 850000 ns;
+ echo <= '0', '1' after 800000 ns, '0' after 1070000 ns;
- clock_driver : process
- constant period : time := 10000 ns;
- begin
- clk <= '0';
- wait for period / 2;
- clk <= '1';
- wait for period / 2;
- end process clock_driver;
- reset : process is
- begin
- rst <= '1';
- wait for 10000 ns;
- rst <= '0';
- wait;
- end process reset;
-
- echo <= '0', '1' after 800000 ns, '0' after 850000 ns;
-
end architecture RTL;
From 2941c64d86f4a1c267bda7617ac98e33aa6ba78f Mon Sep 17 00:00:00 2001
From: Thiago de Lira <49963038+lirahc@users.noreply.github.com>
Date: Tue, 19 Dec 2023 13:56:42 -0300
Subject: [PATCH 2/3] Add files via upload
---
.../sint/de10_lite/de0_lite.vhd | 564 ++++++++++--------
1 file changed, 315 insertions(+), 249 deletions(-)
diff --git a/peripherals/hcsr04_ultrassonic_sensor/sint/de10_lite/de0_lite.vhd b/peripherals/hcsr04_ultrassonic_sensor/sint/de10_lite/de0_lite.vhd
index 60505fe4..454945ed 100644
--- a/peripherals/hcsr04_ultrassonic_sensor/sint/de10_lite/de0_lite.vhd
+++ b/peripherals/hcsr04_ultrassonic_sensor/sint/de10_lite/de0_lite.vhd
@@ -1,6 +1,6 @@
-------------------------------------------------------------------
-- Name : de0_lite.vhd
--- Author : Suzi Yousif
+-- Author :
-- Version : 0.1
-- Copyright : Departamento de Eletrônica, Florianópolis, IFSC
-- Description : Projeto base DE10-Lite
@@ -12,259 +12,325 @@ use ieee.numeric_std.all;
use work.decoder_types.all;
entity de0_lite is
- generic (
- --! Num of 32-bits memory words
- IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes
- DMEMORY_WORDS : integer := 1024 --!= 2k (512 * 2) bytes
- );
- port (
- ---------- CLOCK ----------
- ADC_CLK_10: in std_logic;
- MAX10_CLK1_50: in std_logic;
- MAX10_CLK2_50: in std_logic;
-
- ----------- SDRAM ------------
- DRAM_ADDR: out std_logic_vector (12 downto 0);
- DRAM_BA: out std_logic_vector (1 downto 0);
- DRAM_CAS_N: out std_logic;
- DRAM_CKE: out std_logic;
- DRAM_CLK: out std_logic;
- DRAM_CS_N: out std_logic;
- DRAM_DQ: inout std_logic_vector(15 downto 0);
- DRAM_LDQM: out std_logic;
- DRAM_RAS_N: out std_logic;
- DRAM_UDQM: out std_logic;
- DRAM_WE_N: out std_logic;
-
- ----------- SEG7 ------------
- HEX0: out std_logic_vector(7 downto 0);
- HEX1: out std_logic_vector(7 downto 0);
- HEX2: out std_logic_vector(7 downto 0);
- HEX3: out std_logic_vector(7 downto 0);
- HEX4: out std_logic_vector(7 downto 0);
- HEX5: out std_logic_vector(7 downto 0);
-
- ----------- KEY ------------
- KEY: in std_logic_vector(1 downto 0);
-
- ----------- LED ------------
- LEDR: out std_logic_vector(9 downto 0);
-
- ----------- SW ------------
- SW: in std_logic_vector(9 downto 0);
-
- ----------- VGA ------------
- VGA_B: out std_logic_vector(3 downto 0);
- VGA_G: out std_logic_vector(3 downto 0);
- VGA_HS: out std_logic;
- VGA_R: out std_logic_vector(3 downto 0);
- VGA_VS: out std_logic;
-
- ----------- Accelerometer ------------
- GSENSOR_CS_N: out std_logic;
- GSENSOR_INT: in std_logic_vector(2 downto 1);
- GSENSOR_SCLK: out std_logic;
- GSENSOR_SDI: inout std_logic;
- GSENSOR_SDO: inout std_logic;
-
- ----------- Arduino ------------
- ARDUINO_IO: inout std_logic_vector(15 downto 0);
- ARDUINO_RESET_N: inout std_logic
- );
+ generic (
+ --! Num of 32-bits memory words
+ IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes
+ DMEMORY_WORDS : integer := 1024 --!= 2k (512 * 2) bytes
+ );
+ port (
+ ---------- CLOCK ----------
+ ADC_CLK_10: in std_logic;
+ MAX10_CLK1_50: in std_logic;
+ MAX10_CLK2_50: in std_logic;
+
+ ----------- SDRAM ------------
+ DRAM_ADDR: out std_logic_vector (12 downto 0);
+ DRAM_BA: out std_logic_vector (1 downto 0);
+ DRAM_CAS_N: out std_logic;
+ DRAM_CKE: out std_logic;
+ DRAM_CLK: out std_logic;
+ DRAM_CS_N: out std_logic;
+ DRAM_DQ: inout std_logic_vector(15 downto 0);
+ DRAM_LDQM: out std_logic;
+ DRAM_RAS_N: out std_logic;
+ DRAM_UDQM: out std_logic;
+ DRAM_WE_N: out std_logic;
+
+ ----------- SEG7 ------------
+ HEX0: out std_logic_vector(7 downto 0);
+ HEX1: out std_logic_vector(7 downto 0);
+ HEX2: out std_logic_vector(7 downto 0);
+ HEX3: out std_logic_vector(7 downto 0);
+ HEX4: out std_logic_vector(7 downto 0);
+ HEX5: out std_logic_vector(7 downto 0);
+
+ ----------- KEY ------------
+ KEY: in std_logic_vector(1 downto 0);
+
+ ----------- LED ------------
+ LEDR: out std_logic_vector(9 downto 0);
+
+ ----------- SW ------------
+ SW: in std_logic_vector(9 downto 0);
+
+ ----------- VGA ------------
+ VGA_B: out std_logic_vector(3 downto 0);
+ VGA_G: out std_logic_vector(3 downto 0);
+ VGA_HS: out std_logic;
+ VGA_R: out std_logic_vector(3 downto 0);
+ VGA_VS: out std_logic;
+
+ ----------- Accelerometer ------------
+ GSENSOR_CS_N: out std_logic;
+ GSENSOR_INT: in std_logic_vector(2 downto 1);
+ GSENSOR_SCLK: out std_logic;
+ GSENSOR_SDI: inout std_logic;
+ GSENSOR_SDO: inout std_logic;
+
+ ----------- Arduino ------------
+ ARDUINO_IO: inout std_logic_vector(15 downto 0);
+ ARDUINO_RESET_N: inout std_logic
+ );
end entity;
+
+
architecture rtl of de0_lite is
+ -- Clocks and reset
+ signal clk : std_logic;
+ signal rst : std_logic;
+ signal clk_50MHz : std_logic;
+ -- PLL signals
+ signal locked_sig : std_logic;
+
+ -- Instruction bus signals
+ signal idata : std_logic_vector(31 downto 0);
+ signal iaddress : unsigned(15 downto 0);
+ signal address : std_logic_vector (9 downto 0);
+
+ -- Data bus signals
+ signal daddress : unsigned(31 downto 0);
+ signal ddata_r : std_logic_vector(31 downto 0);
+ signal ddata_w : std_logic_vector(31 downto 0);
+ signal ddata_r_mem : std_logic_vector(31 downto 0);
+ signal dmask : std_logic_vector(3 downto 0);
+ signal dcsel : std_logic_vector(1 downto 0);
+ signal d_we : std_logic;
+ signal d_rd : std_logic;
+ signal d_sig : std_logic;
+
+ -- SDRAM signals
+ signal ddata_r_sdram : std_logic_vector(31 downto 0);
+
+ -- CPU state signals
+ signal state : cpu_state_t;
+ signal div_result : std_logic_vector(31 downto 0);
+
+ -- I/O signals
+ signal gpio_input : std_logic_vector(31 downto 0);
+ signal gpio_output : std_logic_vector(31 downto 0);
+
+ -- Peripheral data signals
+ signal ddata_r_gpio : std_logic_vector(31 downto 0);
+ signal ddata_r_timer : std_logic_vector(31 downto 0);
+ signal ddata_r_periph : std_logic_vector(31 downto 0);
+ signal ddata_r_segments : std_logic_vector(31 downto 0);
+ signal ddata_r_uart : std_logic_vector(31 downto 0);
+ signal ddata_r_adc : std_logic_vector(31 downto 0);
+ signal ddata_r_i2c : std_logic_vector(31 downto 0);
+ signal ddata_r_dig_fil : std_logic_vector(31 downto 0);
+ signal ddata_r_stepmot : std_logic_vector(31 downto 0);
+ signal ddata_r_lcd : std_logic_vector(31 downto 0);
+ signal ddata_r_nn_accelerator : std_logic_vector(31 downto 0);
+ signal ddata_r_fir_fil : std_logic_vector(31 downto 0);
+ signal ddata_r_spwm : std_logic_vector(31 downto 0);
+ signal ddata_r_crc : std_logic_vector(31 downto 0);
+ signal ddata_r_key : std_logic_vector(31 downto 0);
+ signal ddata_r_hcsr04 : std_logic_vector(31 downto 0);
+
+ -- Interrupt Signals
+ signal interrupts : std_logic_vector(31 downto 0);
+ signal gpio_interrupts : std_logic_vector(6 downto 0);
+ signal timer_interrupt : std_logic_vector(5 downto 0);
+ signal ifcap : std_logic; --
+
+ -- I/O signals
+ signal input_in : std_logic_vector(31 downto 0);
- signal clk : std_logic;
- signal rst : std_logic;
-
- -- Instruction bus signals
- signal idata : std_logic_vector(31 downto 0);
- signal iaddress : integer range 0 to IMEMORY_WORDS-1 := 0;
- signal address : std_logic_vector (9 downto 0);
-
- -- Data bus signals
- signal daddress : integer range 0 to DMEMORY_WORDS-1;
- signal ddata_r : std_logic_vector(31 downto 0);
- signal ddata_w : std_logic_vector(31 downto 0);
- signal dmask : std_logic_vector(3 downto 0);
- signal dcsel : std_logic_vector(1 downto 0);
- signal d_we : std_logic := '0';
-
- signal ddata_r_mem : std_logic_vector(31 downto 0);
- signal d_rd : std_logic;
-
- -- I/O signals
- signal ddata_r_gpio : std_logic_vector(31 downto 0);
-
- -- PLL signals
- signal locked_sig : std_logic;
-
- -- CPU state signals
- signal state : cpu_state_t;
- signal d_sig : std_logic;
- signal gpio_input : std_logic;
- signal gpio_output : std_logic;
-
- -- Display variables
- type displays_type is array (0 to 5) of std_logic_vector(3 downto 0);
- type displays_out_type is array (0 to 5) of std_logic_vector(7 downto 0);
- signal displays : displays_type;
- signal displays_out : displays_out_type;
-
begin
- pll_inst: entity work.pll
- port map(
- areset => '0',
- inclk0 => ADC_CLK_10,
- c0 => clk,
- locked => locked_sig
- );
-
- -- Dummy out signals
- rst <= SW(9);
- LEDR(9) <= SW(9);
-
- -- IMem shoud be read from instruction and data buses
- -- Not enough RAM ports for instruction bus, data bus and in-circuit programming
- instr_mux: entity work.instructionbusmux
- generic map(
- IMEMORY_WORDS => IMEMORY_WORDS,
- DMEMORY_WORDS => DMEMORY_WORDS
- )
- port map(
- d_rd => d_rd,
- dcsel => dcsel,
- daddress => daddress,
- iaddress => iaddress,
- address => address
- );
-
- -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor
- iram_quartus_inst: entity work.iram_quartus
- port map(
- address => address,
- byteena => "1111",
- clock => clk,
- data => (others => '0'),
- wren => '0',
- q => idata
- );
-
- -- Data Memory RAM
- dmem: entity work.dmemory
- generic map(
- MEMORY_WORDS => DMEMORY_WORDS
- )
- port map(
- rst => rst,
- clk => clk,
- data => ddata_w,
- address => daddress,
- we => d_we,
- csel => dcsel(0),
- dmask => dmask,
- signal_ext => d_sig,
- q => ddata_r_mem
- );
-
- -- Adress space mux ((check sections.ld) -> Data chip select:
- -- 0x00000 -> Instruction memory
- -- 0x20000 -> Data memory
- -- 0x40000 -> Input/Output generic address space
- -- ( ... ) -> ( ... )
- datamux: entity work.databusmux
- port map(
- dcsel => dcsel,
- idata => idata,
- ddata_r_mem => ddata_r_mem,
- ddata_r_gpio => ddata_r_gpio,
- ddata_r => ddata_r
- );
-
- -- Softcore instatiation
- myRisc: entity work.core
- generic map(
- IMEMORY_WORDS => IMEMORY_WORDS,
- DMEMORY_WORDS => DMEMORY_WORDS
- )
- port map(
- clk => clk,
- rst => rst,
- iaddress => iaddress,
- idata => idata,
- daddress => daddress,
- ddata_r => ddata_r,
- ddata_w => ddata_w,
- d_we => d_we,
- d_rd => d_rd,
- d_sig => d_sig,
- dcsel => dcsel,
- dmask => dmask,
- state => state
- );
-
- HCSR04_inst: entity work.HCSR04
- generic map(
- MY_CHIPSELECT => "10",
- MY_WORD_ADDRESS => x"10"
- )
- port map(
- clk => clk,
- rst => SW(8),
- daddress => daddress,
- ddata_w => ddata_w,
- ddata_r => ddata_r_gpio,
- d_we => d_we,
- d_rd => d_rd,
- dcsel => dcsel,
- dmask => dmask,
- echo => gpio_input,
- Trig => gpio_output
- );
-
- -- Connect input hardware to gpio data
- gpio_input <= ARDUINO_IO(0);
-
- -- Connect gpio data to output hardware
- ARDUINO_IO(1) <= gpio_output;
-
- -- Display
- hex_gen : for i in 0 to 5 generate
- hex_dec : entity work.display_dec
- port map(
- data_in => displays(i),
- disp => displays_out(i)
- );
- end generate;
-
- HEX0 <= displays_out(0);
- HEX1 <= displays_out(1);
- HEX2 <= displays_out(2);
- HEX3 <= displays_out(3);
- HEX4 <= displays_out(4);
- HEX5 <= displays_out(5);
-
- display : process (clk, rst) is
- begin
- if rst = '1' then
- for i in 0 to 5 loop
- displays(i) <= (others => '0');
- end loop;
- elsif rising_edge(clk) then
- if (d_we = '1') and (dcsel = "10")then
- if to_unsigned(daddress, 32)(8 downto 0) = x"02" then -- OUT_SEGS
- displays(0) <= ddata_w(3 downto 0);
- displays(1) <= ddata_w(7 downto 4);
- displays(2) <= ddata_w(11 downto 8);
- displays(3) <= ddata_w(15 downto 12);
- displays(4) <= ddata_w(19 downto 16);
- displays(5) <= ddata_w(23 downto 20);
- end if;
- end if;
- end if;
- end process display;
-
+ -- Reset
+ rst <= SW(9);
+ LEDR(9) <= SW(9);
+
+ -- Clocks
+ pll_inst : entity work.pll
+ port map(
+ areset => '0',
+ inclk0 => MAX10_CLK1_50,
+ c0 => clk,
+ c1 => clk_50MHz,
+ locked => locked_sig
+ );
+
+ -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor
+ iram_quartus_inst: entity work.iram_quartus
+ port map(
+ address => address,
+ byteena => "1111",
+ clock => clk,
+ data => (others => '0'),
+ wren => '0',
+ q => idata
+ );
+
+ -- IMem shoud be read from instruction and data buses
+ -- Not enough RAM ports for instruction bus, data bus and in-circuit programming
+ instr_mux: entity work.instructionbusmux
+ port map(
+ d_rd => d_rd,
+ dcsel => dcsel,
+ daddress => daddress,
+ iaddress => iaddress,
+ address => address
+ );
+
+ -- Data Memory RAM
+ dmem: entity work.dmemory
+ generic map(
+ MEMORY_WORDS => DMEMORY_WORDS
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ data => ddata_w,
+ address => daddress,
+ we => d_we,
+ csel => dcsel(0),
+ dmask => dmask,
+ signal_ext => d_sig,
+ q => ddata_r_mem
+ );
+
+ -- Adress space mux ((check sections.ld) -> Data chip select:
+ -- 0x00000 -> Instruction memory
+ -- 0x20000 -> Data memory
+ -- 0x40000 -> Input/Output generic address space
+ -- ( ... ) -> ( ... )
+ datamux: entity work.databusmux
+ port map(
+ dcsel => dcsel,
+ idata => idata,
+ ddata_r_mem => ddata_r_mem,
+ ddata_r_periph => ddata_r_periph,
+ ddata_r_sdram =>ddata_r_sdram,
+ ddata_r => ddata_r
+ );
+
+ -- Softcore instatiation
+ myRiscv : entity work.core
+ port map(
+ clk => clk,
+ rst => rst,
+ clk_32x => clk_50MHz,
+ iaddress => iaddress,
+ idata => idata,
+ daddress => daddress,
+ ddata_r => ddata_r,
+ ddata_w => ddata_w,
+ d_we => d_we,
+ d_rd => d_rd,
+ d_sig => d_sig,
+ dcsel => dcsel,
+ dmask => dmask,
+ interrupts=>interrupts,
+ state => state
+ );
+
+ -- IRQ lines
+ interrupts(24 downto 18) <= gpio_interrupts(6 downto 0);
+ interrupts(30 downto 25) <= timer_interrupt;
+
+ io_data_bus_mux: entity work.iodatabusmux
+ port map(
+ daddress => daddress,
+ ddata_r_gpio => ddata_r_gpio,
+ ddata_r_segments => ddata_r_segments,
+ ddata_r_uart => ddata_r_uart,
+ ddata_r_adc => ddata_r_adc,
+ ddata_r_i2c => ddata_r_i2c,
+ ddata_r_timer => ddata_r_timer,
+ ddata_r_periph => ddata_r_periph,
+ ddata_r_dif_fil => ddata_r_dig_fil,
+ ddata_r_stepmot => ddata_r_stepmot,
+ ddata_r_lcd => ddata_r_lcd,
+ ddata_r_fir_fil => ddata_r_fir_fil,
+ ddata_r_nn_accelerator => ddata_r_nn_accelerator,
+ ddata_r_spwm => ddata_r_spwm,
+ ddata_r_crc => ddata_r_crc,
+ ddata_r_key => ddata_r_key
+ );
+
+ generic_gpio: entity work.gpio
+ port map(
+ clk => clk,
+ rst => rst,
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => ddata_r_gpio,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+ input => gpio_input,
+ output => gpio_output,
+ gpio_interrupts => gpio_interrupts
+ );
+
+ -- Timer instantiation
+ timer : entity work.Timer
+ generic map(
+ prescaler_size => 16,
+ compare_size => 32
+ )
+ port map(
+ clock => clk,
+ reset => rst,
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => ddata_r_timer,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+ timer_interrupt => timer_interrupt,
+ ifcap => ifcap --
+ );
+
+ generic_displays : entity work.led_displays
+ port map(
+ clk => clk,
+ rst => rst,
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => ddata_r_segments,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+ hex0 => HEX0,
+ hex1 => HEX1,
+ hex2 => HEX2,
+ hex3 => HEX3,
+ hex4 => HEX4,
+ hex5 => HEX5,
+ hex6 => open,
+ hex7 => open
+ );
+
+ HCSR04_inst: entity work.HCSR04
+ generic map(
+ MY_CHIPSELECT => "10",
+ MY_WORD_ADDRESS => x"10"
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => ddata_r_hcsr04,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+ --echo => ARDUINO_IO(0),
+ echo => d_we,
+ Trig => ARDUINO_IO(1)
+ );
+
+ -- Connect input hardware to gpio data
+ gpio_input(3 downto 0) <= SW(3 downto 0);
+ LEDR(7 downto 0) <= gpio_output(7 downto 0);
+
end;
From 8161965910c19e1af4e75053d1407d32e95ccbb7 Mon Sep 17 00:00:00 2001
From: Thiago de Lira <49963038+lirahc@users.noreply.github.com>
Date: Tue, 19 Dec 2023 13:57:42 -0300
Subject: [PATCH 3/3] Update README.md
---
.../hcsr04_ultrassonic_sensor/README.md | 64 +++++++++----------
1 file changed, 29 insertions(+), 35 deletions(-)
diff --git a/peripherals/hcsr04_ultrassonic_sensor/README.md b/peripherals/hcsr04_ultrassonic_sensor/README.md
index db309884..f2b40794 100644
--- a/peripherals/hcsr04_ultrassonic_sensor/README.md
+++ b/peripherals/hcsr04_ultrassonic_sensor/README.md
@@ -1,42 +1,36 @@
# Sensor Ultrassônico HC-SR04
-
-Esta é uma implementação de uso do periférico [HC-SR04](https://cdn.sparkfun.com/datasheets/Sensors/Proximity/HCSR04.pdf), o qual é um sensor ultrassônica. O funcionamento dele é descrito conforme apresentado no diagrama abaixo. Primeiro é enviado um pulso de *trigger* de 10 us. Posteriormente é recebido um sinal de *echo*, em que sua largura é proporcional à distância do sensor a um objeto específico.
-
-
- 
-
-
-Para isso, gerou-se uma [máquina de estados](HCSR04.vhd), representada na figura abaixo.
-
- 
-
-
+- Esta é uma implementação de uso do periférico [HC-SR04](https://cdn.sparkfun.com/datasheets/Sensors/Proximity/HCSR04.pdf), o qual é um sensor ultrassônica. O funcionamento dele é descrito conforme apresentado no diagrama abaixo. Primeiro é enviado um pulso de trigger de 10 us. Posteriormente é recebido um sinal de echo, em que sua largura é proporcional à distância do sensor a um objeto específico.
+
+DIAGRAMA DE TEMPO
+
+- Para isso, gerou-se uma máquina de estados, representada na figura abaixo.
+
+MAQUINA DE ESTADOS
+
## Simulação
-Para a simulação, gerou-se dois arquivos de teste. Um sem o arquivo de memória [testbench2.vhd](testbench2.vhd) , onde é possível visualizar a mudança dos estados e o contador de pulsos do sinal de entrada *echo*. O outro arquivo é com o uso da arquitetura RiscV [testbench.vhd](testbench.vhd).
-
-
+- Para a simulação, gerou-se dois arquivos de teste. O arquivo [testbench2.vhd](/peripherals/hcsr04_ultrassonic_sensor) , sendo possível visualizar a mudança dos estados e o contador de pulsos do sinal de entrada echo.
+
## Montagem do circuito
-Este sensor necessita de tensão de entrada de 5V para seu funcionamento adequado. Por isso, para a montagem do circuito, utilizou-se um conversor de nível lógico de 5V a 3V3 bidirecional, conforme apresentado abaixo.
-
-Os pinos *echo* e *trigger* são conectados aos pinos do `ARDUINO_IO 0` e `1`, respectivamente.
-
-
- 
-
-
+- Este sensor necessita de tensão de entrada de 5V para seu funcionamento adequado. Por isso, para a montagem do circuito, utilizou-se um conversor de nível lógico de 5V a 3V3 bidirecional, conforme apresentado abaixo.
+- Os pinos echo e trigger são conectados aos pinos do ARDUINO_IO 0 e 1, respectivamente.
+MONTAGEM DO CIRCUITO
+
## Resultados da síntese
-A figura abaixo foi retirado com o auxílio de um analisador lógico. Nesta, pode ser visto o sinal de *trigger* de 10 us e o sinal de *echo* gerado pelo sensor.
-
- 
-
-
-Para melhor visualização dos resultados na placa, foram utilizados [os displays 7 segmentos](../disp7seg/display_dec.vhd). A saída é equivalente à quantidade de ciclos de 10 us, a qual aumenta com o aumento da distância do objeto.
-
+- A figura abaixo foi retirado com o auxílio de um analisador lógico. Nesta, pode ser visto o sinal de trigger de 10 us e o sinal de echo gerado pelo sensor.
+SIMULAÇÃO
+
+## Teste Prático
+### Distância de 05 cm.
+
+
+### Distância de 15 cm.
+
+
+### Disposição Trig & Echo
+
+
## ToDo
-Na síntese, observou-se que após um determinado tempo, ele parava de realizar a contagem e necessitava de *reset*. Por isso, posteriormente é necessário analisar o sinal de *echo* no osciloscópio para verificar uma possível perda de descida deste sinal.
+- Na síntese, observou-se que após um determinado tempo, ele parava de realizar a contagem e necessitava de reset. Por isso, posteriormente é necessário analisar o sinal de echo no osciloscópio para verificar uma possível perda de descida deste sinal. Sendo assim, o *Trigger* funciona num período de 10us sendo o período de 60ms do sistema, antes disso o sistema está em *Idle*, após o período de Trigger o sistema está enable e o sinal *Echo* está disponível para captação do sinal para validação do sensor, como pode ser visto na figura a seguir o sistema.
+
-## Referências
-* [HC-SR04 Datasheet](https://cdn.sparkfun.com/datasheets/Sensors/Proximity/HCSR04.pdf)
-
-