diff --git a/memory/iodatabusmux.vhd b/memory/iodatabusmux.vhd
index 995a03a8..a145ebaa 100644
--- a/memory/iodatabusmux.vhd
+++ b/memory/iodatabusmux.vhd
@@ -20,6 +20,7 @@ entity iodatabusmux is
 		ddata_r_adc      : in   std_logic_vector(31 downto 0);
 		ddata_r_i2c      : in   std_logic_vector(31 downto 0);
 		ddata_r_timer    : in   std_logic_vector(31 downto 0);
+		ddata_r_stepmot  : in   std_logic_vector(31 downto 0);
 		
 		-- Mux 
 		ddata_r_periph		: out 	std_logic_vector(31 downto 0)     --! Connect to data bus mux
@@ -37,6 +38,7 @@ begin
                           ddata_r_adc      when x"0003",
                           ddata_r_i2c      when x"0004",
                           ddata_r_timer    when x"0005",
+                          ddata_r_stepmot  when x"0009",
                           
                           -- Add new io peripherals here                          
                           (others => '0')when others;
diff --git a/memory/iram_quartus.vhd b/memory/iram_quartus.vhd
index 4d461c29..29e4c6d9 100644
--- a/memory/iram_quartus.vhd
+++ b/memory/iram_quartus.vhd
@@ -65,7 +65,7 @@ BEGIN
 		byte_size => 8,
 		clock_enable_input_a => "BYPASS",
 		clock_enable_output_a => "BYPASS",
-		init_file => "../../software/uart/quartus_main_irq.hex",
+		init_file => "../../software/step_motor/quartus_main_step_motor.hex",
 		intended_device_family => "MAX 10",
 		lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1",
 		lpm_type => "altsyncram",
diff --git a/peripherals/spi/images/osc_spi_gifs.gif b/peripherals/spi/images/osc_spi_gifs.gif
index b9ab8086..598b2774 100644
Binary files a/peripherals/spi/images/osc_spi_gifs.gif and b/peripherals/spi/images/osc_spi_gifs.gif differ
diff --git a/peripherals/step_motor/sim.s b/peripherals/step_motor/sim.s
new file mode 100644
index 00000000..e69de29b
diff --git a/peripherals/step_motor/stepmotor.vhd b/peripherals/step_motor/stepmotor.vhd
index fb04ebf3..0698fa75 100644
--- a/peripherals/step_motor/stepmotor.vhd
+++ b/peripherals/step_motor/stepmotor.vhd
@@ -8,15 +8,33 @@ use ieee.std_logic_1164.all;                            -- Elementos l
 use ieee.numeric_std.all;                               -- Conversões entre tipos
 
 entity stepmotor is
+    generic (
+        --! Chip selec
+        MY_CHIPSELECT : std_logic_vector(1 downto 0) := "10";
+        MY_WORD_ADDRESS : unsigned(7 downto 0) := x"10";
+        DADDRESS_BUS_SIZE : integer := 32
+    );
+
     port(
         clk                : in  std_logic;             -- Clock input
-        reverse            : in  std_logic;             -- Reverse flag: Changes the rotation direction
         rst                : in  std_logic;             -- Reset flag: Changes the step motor to it's initial state
+
+        -- Core data bus signals
+        daddress  : in  unsigned(DADDRESS_BUS_SIZE-1 downto 0);
+        ddata_w   : in  std_logic_vector(31 downto 0);
+        ddata_r   : out std_logic_vector(31 downto 0);
+        d_we      : in std_logic;
+        d_rd      : in std_logic;
+        dcsel     : in std_logic_vector(1 downto 0);    --! Chip select 
+        -- ToDo: Module should mask bytes (Word, half word and byte access)
+        dmask     : in std_logic_vector(3 downto 0);    --! Byte enable mask
+
+        -- hardware input/output signals        
+        reverse            : in  std_logic;             -- Reverse flag: Changes the rotation direction
         stop               : in  std_logic;             -- Stop flag: Stops the motor in it's actual position
-        ena                : in  std_logic;             -- Enable flag: Permits motor control  
         half_full          : in  std_logic;             -- Half or full step flag: Alternate the steps size
-        in1, in2, in3, in4 : out std_logic;             -- Motor H-bridge control inputs
-        speed              : in  unsigned(2 downto 0)   -- Defines the motor speed, in a range from 1 to 8
+        speed              : in  unsigned(2 downto 0);  -- Defines the motor speed, in a range from 1 to 8
+        in1, in2, in3, in4 : out std_logic              -- Motor H-bridge control inputs
     );
 
 end entity stepmotor;
@@ -44,7 +62,7 @@ begin
             cntr <= cntr + 1;
         end if;
     end process rotate;
-    rot <= cntr(to_integer(speed));
+    rot <= cntr(7-to_integer(speed));
 
     mealy : process(rot, rst)
     begin
@@ -52,75 +70,73 @@ begin
             state <= A;
         end if;
         if rising_edge(rot) then
-            if ena = '1' then
-                if stop = '0' then
-                    case state is
-                        when A =>
-                            if reverse = '1' and half_full = '0' then
-                                state <= DA;
-                            elsif reverse = '0' and half_full = '0' then
-                                state <= AB;
-                            elsif reverse = '1' and half_full = '1' then
-                                state <= D;
-                            else
-                                state <= B;
-                            end if;
-                        when AB =>
-                            if reverse = '1' then
-                                state <= A;
-                            else
-                                state <= B;
-                            end if;
-                        when B =>
-                            if reverse = '1' and half_full = '0' then
-                                state <= AB;
-                            elsif reverse = '0' and half_full = '0' then
-                                state <= BC;
-                            elsif reverse = '1' and half_full = '1' then
-                                state <= A;
-                            else
-                                state <= C;
-                            end if;
-                        when BC =>
-                            if reverse = '1' then
-                                state <= B;
-                            else
-                                state <= C;
-                            end if;
-                        when C =>
-                            if reverse = '1' and half_full = '0' then
-                                state <= BC;
-                            elsif reverse = '0' and half_full = '0' then
-                                state <= CD;
-                            elsif reverse = '1' and half_full = '1' then
-                                state <= B;
-                            else
-                                state <= D;
-                            end if;
-                        when CD =>
-                            if reverse = '1' then
-                                state <= C;
-                            else
-                                state <= D;
-                            end if;
-                        when D =>
-                            if reverse = '1' and half_full = '0' then
-                                state <= C;
-                            elsif reverse = '0' and half_full = '0' then
-                                state <= DA;
-                            elsif reverse = '1' and half_full = '1' then
-                                state <= C;
-                            else
-                                state <= A;
-                            end if;
-                        when DA =>
-                            if reverse = '1' then
-                                state <= D;
-                            else
-                                state <= A;
-                            end if;
-                    end case;
-                end if;
+            if stop = '0' then
+                case state is
+                    when A =>
+                        if reverse = '1' and half_full = '0' then
+                            state <= DA;
+                        elsif reverse = '0' and half_full = '0' then
+                            state <= AB;
+                        elsif reverse = '1' and half_full = '1' then
+                            state <= D;
+                        else
+                            state <= B;
+                        end if;
+                    when AB =>
+                        if reverse = '1' then
+                            state <= A;
+                        else
+                            state <= B;
+                        end if;
+                    when B =>
+                        if reverse = '1' and half_full = '0' then
+                            state <= AB;
+                        elsif reverse = '0' and half_full = '0' then
+                            state <= BC;
+                        elsif reverse = '1' and half_full = '1' then
+                            state <= A;
+                        else
+                            state <= C;
+                        end if;
+                    when BC =>
+                        if reverse = '1' then
+                            state <= B;
+                        else
+                            state <= C;
+                        end if;
+                    when C =>
+                        if reverse = '1' and half_full = '0' then
+                            state <= BC;
+                        elsif reverse = '0' and half_full = '0' then
+                            state <= CD;
+                        elsif reverse = '1' and half_full = '1' then
+                            state <= B;
+                        else
+                            state <= D;
+                        end if;
+                    when CD =>
+                        if reverse = '1' then
+                            state <= C;
+                        else
+                            state <= D;
+                        end if;
+                    when D =>
+                        if reverse = '1' and half_full = '0' then
+                            state <= C;
+                        elsif reverse = '0' and half_full = '0' then
+                            state <= DA;
+                        elsif reverse = '1' and half_full = '1' then
+                            state <= C;
+                        else
+                            state <= A;
+                        end if;
+                    when DA =>
+                        if reverse = '1' then
+                            state <= D;
+                        else
+                            state <= A;
+                        end if;
+                end case;
             end if;
         end if;
     end process mealy;
diff --git a/peripherals/step_motor/tb_stepmotor.vhd b/peripherals/step_motor/tb_stepmotor-no_core.vhd
similarity index 89%
rename from peripherals/step_motor/tb_stepmotor.vhd
rename to peripherals/step_motor/tb_stepmotor-no_core.vhd
index 99f96496..f0044f51 100644
--- a/peripherals/step_motor/tb_stepmotor.vhd
+++ b/peripherals/step_motor/tb_stepmotor-no_core.vhd
@@ -26,7 +26,6 @@ begin
             reverse   => reverse,
             rst       => rst,
             stop      => stop,
-            ena       => ena,
             half_full => half_full,
             in1       => in1,
             in2       => in2,
@@ -43,14 +42,6 @@ begin
         wait for 1 ms;
     end process clk0;
 
-    en0: process is
-    begin
-        ena <= '0';
-        wait for 6 ms;
-        ena <= '1';
-        wait;
-    end process en0;
-
     speed0: process is
     begin
         rst <='0';
diff --git a/peripherals/step_motor/testbench.do b/peripherals/step_motor/testbench.do
new file mode 100644
index 00000000..a9e2d045
--- /dev/null
+++ b/peripherals/step_motor/testbench.do
@@ -0,0 +1,186 @@
+#******************************************************************************
+#                                                                             *
+#                  Copyright (C) 2019 IFSC                                    *
+#                                                                             *
+#                                                                             *
+# All information provided herein is provided on an "as is" basis,            *
+# without warranty of any kind.                                               *
+#                                                                             *
+# File Name: testbench.do                                                     *
+#                                                                             *
+# Function: riscv muticycle simulation script                                 *
+#                                                                             *
+# REVISION HISTORY:                                                           *
+#  Revision 0.1.0    08/01/2018 - Initial Revision                            *
+#  Revision 0.2.0    31/05/2021 - Change path and added some peripherals      *
+#******************************************************************************
+
+vlib work
+vcom ../../memory/iram_quartus.vhd
+vcom ../../memory/dmemory.vhd
+vcom ../../memory/instructionbusmux.vhd
+vcom ../../memory/databusmux.vhd
+vcom ../../memory/iodatabusmux.vhd
+vcom ../../alu/alu_types.vhd
+vcom ../../alu/alu.vhd
+vcom ../../alu/m/division_functions.vhd
+vcom ../../alu/m/quick_naive.vhd
+vcom ../../alu/m/M_types.vhd
+vcom ../../alu/m/M.vhd
+vcom ../../decoder/decoder_types.vhd
+vcom ../../decoder/iregister.vhd
+vcom ../../decoder/decoder.vhd
+vcom ../../registers/register_file.vhd
+vcom ../../peripherals/gpio/gpio.vhd
+vcom ../../peripherals/gpio/led_displays.vhd
+vcom ../../peripherals/timer/Timer.vhd
+vcom ./stepmotor.vhd
+vcom ../../core/csr.vhd
+vcom ../../core/core.vhd
+vcom ../../core/txt_util.vhdl
+vcom ../../core/trace_debug.vhd
+vcom testbench.vhd
+
+vsim -t ns work.coretestbench
+
+view wave
+add wave -radix binary 	/clk
+add wave -radix binary 	/rst
+add wave -height 15 -divider "Instruction Memory"
+add wave -label iAddr -radix hex /address
+add wave -label iWord -radix hex idata
+add wave -label decoded -radix ASCII /debugString
+# add wave /debugString
+# add wave -radix hex /imem/RAM
+# add wave -radix hex /q
+
+add wave -height 15 -divider "PC and Ctrl Targers"
+add wave -radix hex -label pc 			/myRiscv/pc
+add wave -radix hex -label jal_target 	/myRiscv/jal_target
+add wave -radix hex -label jalr_target 	/myRiscv/jalr_target
+add wave -label branch_cmp 				/myRiscv/branch_cmp
+add wave -radix hex -label jumps 	/myRiscv/jumps
+
+
+add wave -height 15 -divider "Iregister debug"
+add wave -label opcode  /myRiscv/opcodes
+add wave -label rd /myRiscv/rd
+add wave -label rs1 /myRiscv/rs1
+add wave -label rs2 /myRiscv/rs2
+add wave -label imm_i /myRiscv/imm_i
+add wave -label imm_s /myRiscv/imm_s
+add wave -label imm_b /myRiscv/imm_b
+add wave -label imm_u /myRiscv/imm_u
+add wave -label imm_j /myRiscv/imm_j
+
+
+add wave -height 15 -divider "Register file debug"
+ add wave -label registers -radix hex /myRiscv/registers/ram
+ add wave -label w_ena 	/myRiscv/rf_w_ena
+ add wave -label w_data -radix hex	/myRiscv/rw_data
+ add wave -label r1_data -radix hex /myRiscv/rs1_data
+ add wave -label r2_data -radix hex /myRiscv/rs2_data
+
+# decoder debug
+add wave -label states /myRiscv/decoder0/state
+
+add wave -height 15 -divider "GPIO"
+add wave -label enable_exti_mask -radix hex /generic_gpio/enable_exti_mask
+add wave -label edge_exti_mask -radix hex /generic_gpio/edge_exti_mask
+add wave -label output_reg -radix hex /generic_gpio/output_reg
+
+add wave -height 15 -divider "CSR"
+add wave -label interrupts -radix hex /myRiscv/interrupts
+add wave -label pending_interrupts -radix hex /myRiscv/ins_csr/pending_interrupts
+add wave -label mret -radix hex /myRiscv/ins_csr/mret
+add wave -label pending /myRiscv/pending
+add wave -label csr_write /myRiscv/csr_write
+add wave -label csr_addr /myRiscv/imm_i
+add wave -label csr_value -radix hex /myRiscv/csr_value
+add wave -label load_mepc -radix hex /myRiscv/load_mepc
+# add wave -label load_mepc_holder -radix hex /myRiscv/ins_csr/load_mepc_holder
+add wave -label mepc -radix hex /myRiscv/mepc
+add wave -label mretpc -radix hex /myRiscv/mretpc
+add wave -label csr_new -radix hex /myRiscv/rs1_data
+# add wave -label mreg -radix hex /myRiscv/ins_csr/mreg
+
+
+add wave -height 15 -divider "Alu debug"
+add wave -radix dec -label aluData /myRiscv/alu_data
+add wave -radix dec -label aluOut 	/myRiscv/alu_out
+
+add wave -height 15 -divider "M Extension debug"
+add wave -label clock_32x /myRiscv/clk_32x
+add wave -label code_operator /myRiscv/M_data.code
+add wave -radix dec -label a_integer 	/myRiscv/M_data.a
+add wave -radix dec -label b_integer 	/myRiscv/M_data.b
+add wave -radix dec -label M_out   	  /myRiscv/M_out
+
+add wave -height 15 -divider "Data memory debug"
+add wave -label daddr -radix hex /myRiscv/memAddrTypeSBlock/addr
+add wave -label fsm_data -radix hex /dmem/fsm_data
+add wave -label ram_data -radix hex /dmem/ram_data
+add wave -label mState /dmem/state
+add wave -label fsm_we /dmem/fsm_we
+add wave -label ddata_r_mem -radix hex /dmem/q
+add wave -label datamemory -radix hex /dmem/ram_block
+
+
+add wave -height 15 -divider "Data bus"
+add wave -label daddress -radix hex /daddress
+add wave -label ddata_r -radix hex 	/ddata_r
+add wave -label ddata_w -radix hex 	/ddata_w
+add wave -label dmask -radix bin /dmask
+add wave -label dcsel 	/dcsel
+add wave -label d_we 	/d_we
+add wave -label d_rd 	/d_rd
+add wave -label d_sig   /d_sig
+
+add wave -height 15 -divider "Peripheral Data bus"
+add wave -label daddress -radix hex /daddress
+add wave -label ddata_r_periph -radix hex 	/ddata_r_periph
+add wave -label ddata_r_gpio -radix hex 	/ddata_r_gpio
+
+add wave -label gpio_interrupts -radix hex /gpio_interrupts
+add wave -label gpio_input -radix hex /gpio_input
+
+add wave -height 15 -divider "Timer"
+add wave -label enable_timer_irq_mask -radix hex /timer/enable_timer_irq_mask
+add wave -label timer_interrupt -radix hex /timer/timer_interrupt
+add wave -label timer_reset -radix binary /timer/timer_reset
+add wave -label timer_mode -radix unsigned /timer/timer_mode
+add wave -label prescaler -radix unsigned /timer/prescaler
+add wave -label top_counter -radix unsigned /timer/top_counter
+add wave -label counter -radix unsigned /timer/counter
+add wave -label compare_0A -radix unsigned /timer/compare_0A
+add wave -label compare_0B -radix unsigned /timer/compare_0B
+add wave -label compare_1A -radix unsigned /timer/compare_1A
+add wave -label compare_1B -radix unsigned /timer/compare_1B
+add wave -label compare_2A -radix unsigned /timer/compare_2A
+add wave -label compare_2B -radix unsigned /timer/compare_2B
+add wave -label output_0A -radix binary /timer/output_A(0)
+add wave -label output_0B -radix binary /timer/output_B(0)
+add wave -label output_1A -radix binary /timer/output_A(1)
+add wave -label output_1B -radix binary /timer/output_B(1)
+add wave -label output_2A -radix binary /timer/output_A(2)
+add wave -label output_2B -radix binary /timer/output_B(2)
+add wave -label internal_clock -radix binary /timer/internal_clock
+
+
+add wave -height 15 -divider "Input/Output SIM"
+add wave -label LEDR -radix hex /LEDR
+add wave -label HEX0 -radix hex /HEX0
+add wave -label ARDUINO_IO -radix hex /ARDUINO_IO
+
+add wave -height 15 -divider "Step Motor"
+add wave -radix binary   -label reverse /reverse
+add wave -radix binary   -label restart /rst
+add wave -radix binary   -label stop /stop
+add wave -radix binary   -label half_full /half_full
+add wave -radix unsigned -label speed /speed 
+add wave -radix binary   -label outputs /outputs
+add wave                 -label state /motor0/state
+
+
+run 2000 us
+wave zoomfull
diff --git a/peripherals/step_motor/testbench.vhd b/peripherals/step_motor/testbench.vhd
new file mode 100644
index 00000000..29126716
--- /dev/null
+++ b/peripherals/step_motor/testbench.vhd
@@ -0,0 +1,369 @@
+-------------------------------------------------------
+--! @file
+--! @brief RISCV Testbench
+--         This testbench simulates a core with a 
+--         generic IO hardware and a Timer     
+--
+-------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.decoder_types.all;
+
+entity coretestbench is
+	generic(
+		--! Num of 32-bits memory words
+		IMEMORY_WORDS : integer := 1024;	--!= 4K (1024 * 4) bytes
+		DMEMORY_WORDS : integer := 1024  	--!= 2k (512 * 2) bytes
+	);
+
+	port(
+		----------- SEG7 ------------
+		HEX0 : out std_logic_vector(7 downto 0);
+		HEX1 : out std_logic_vector(7 downto 0);
+		HEX2 : out std_logic_vector(7 downto 0);
+		HEX3 : out std_logic_vector(7 downto 0);
+		HEX4 : out std_logic_vector(7 downto 0);
+		HEX5 : out std_logic_vector(7 downto 0);
+		----------- SW ------------
+
+		SW: in std_logic_vector(9 downto 0);
+		LEDR: out std_logic_vector(9 downto 0);
+
+		---------- ARDUINO IO -----
+		ARDUINO_IO: inout std_logic_vector(15 downto 0)
+	);
+
+
+end entity coretestbench;
+
+architecture RTL of coretestbench is
+    -- Clocks and reset
+	signal clk       : std_logic;
+	signal clk_32x   : std_logic;
+	signal rst       : std_logic;
+	
+	-- Instruction bus and instruction memory
+	signal address     : std_logic_vector(9 downto 0);
+	signal iaddress : unsigned(15 downto 0);
+	signal idata : std_logic_vector(31 downto 0);
+	
+    -- Data bus
+	signal daddress : unsigned(31 downto 0);
+	signal ddata_r  : std_logic_vector(31 downto 0);
+	signal ddata_w  : std_logic_vector(31 downto 0);
+	signal dmask    : std_logic_vector(3 downto 0);
+	signal dcsel    : std_logic_vector(1 downto 0);
+	signal d_we     : std_logic := '0';
+	signal ddata_r_mem : std_logic_vector(31 downto 0);
+	signal d_rd : std_logic;
+	signal d_sig : std_logic;
+
+	-- Modelsim debug signals
+	signal cpu_state    : cpu_state_t;
+	signal debugString  : string(1 to 40) := (others => '0');
+
+	-- I/O signals
+	signal interrupts : std_logic_vector(31 downto 0);
+	signal ddata_r_gpio : std_logic_vector(31 downto 0);
+	signal gpio_input : std_logic_vector(31 downto 0);
+	signal gpio_output : std_logic_vector(31 downto 0);
+
+	signal ddata_r_timer : std_logic_vector(31 downto 0);
+	signal timer_interrupt : std_logic_vector(5 downto 0);
+	signal ddata_r_periph : std_logic_vector(31 downto 0);
+    signal ddata_r_sdram : std_logic_vector(31 downto 0);
+
+	signal gpio_interrupts : std_logic_vector(6 downto 0);
+	signal ddata_r_segments : std_logic_vector(31 downto 0);
+	signal ddata_r_uart : std_logic_vector(31 downto 0);
+	signal ddata_r_adc : std_logic_vector(31 downto 0);
+	signal ddata_r_i2c : std_logic_vector(31 downto 0);
+	
+	-- StepMotor signals
+	signal ddata_r_stepmot : std_logic_vector(31 downto 0);
+	signal reverse, stop : std_logic;
+    signal half_full : std_logic;
+    signal in1: std_logic;
+    signal in2: std_logic;
+    signal in3: std_logic;
+    signal in4: std_logic;
+    signal speed : unsigned(2 downto 0);
+    signal outputs : std_logic_vector(3 downto 0);
+	
+begin
+
+	clock_driver : process
+		constant period : time := 1000 ns;
+	begin
+		clk <= '0';
+		wait for period / 2;
+		clk <= '1';
+		wait for period / 2;
+	end process clock_driver;
+
+	--! Division unit clock
+	clock_driver_32x : process
+		constant period : time := 20 ns;
+	begin
+		clk_32x <= '0';
+		wait for period / 2;
+		clk_32x <= '1';
+		wait for period / 2;
+	end process clock_driver_32x;
+ 
+	reset : process is
+	begin
+		rst <= '1';
+		wait for 150 ns;
+		rst <= '0';
+		wait;
+	end process reset;
+	
+	step_test: process
+	begin
+	    outputs(0) <= in1; outputs(1) <= in2; outputs(2) <= in3; outputs(3) <= in4;
+	    stop <= '0';
+	    speed <= to_unsigned(0,speed'length);
+	    half_full <= '0';
+	    reverse <= '0';
+	    wait for 14000 ns;
+	    
+	    stop <= '1';
+	    wait for 2000 ns;
+	    
+	    stop <= '0';
+	    half_full <= '1';
+	    wait for 14000 ns;
+	    
+	    reverse <= '1';
+	    wait for 2000 ns;
+	    
+	    reverse <= '0';
+	    half_full <= '0';
+	    for i in 0 to 7 loop
+            speed <= to_unsigned(i, speed'length);
+            wait for 20 ms;
+        end loop;
+        
+        speed <= to_unsigned(0, speed'length);
+        
+        wait;
+	    
+	end process step_test;
+	
+	
+	-- Connect gpio data to output hardware
+    LEDR  <= gpio_output(9 downto 0);
+
+    -- Connect input hardware to gpio data
+    gpio_test: process
+    begin
+        gpio_input <= (others => '0');
+        wait for 500 us;
+                
+        -- Generate a input pulse (External IRQ 0 or pooling)
+        gpio_input(0) <= '1';
+        wait for 1 us;
+        gpio_input(0) <= '0';
+        
+        -- Generate a input pulse (External IRQ 1 or pooling)
+        wait for 200 us;
+        gpio_input(1) <= '1';
+        wait for 1 us;
+        gpio_input(1) <= '0';
+        
+        wait;
+    end process;  
+
+	-- IMem shoud be read from instruction and data buses
+    -- Not enough RAM ports for instruction bus, data bus and in-circuit programming
+    instr_mux: entity work.instructionbusmux
+        port map(
+            d_rd     => d_rd,
+            dcsel    => dcsel,
+            daddress => daddress,
+            iaddress => iaddress,
+            address  => address
+    );
+
+	-- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor
+	iram_quartus_inst : entity work.iram_quartus
+		port map(
+			address => address(9 downto 0),
+			byteena => "1111",
+			clock   => clk,
+			data    => (others => '0'),
+			wren    => '0',
+			q       => idata
+		);
+
+	-- dmemory_address <= daddress;
+	-- Data Memory RAM
+	dmem : entity work.dmemory
+		generic map(
+			MEMORY_WORDS => DMEMORY_WORDS
+		)
+		port map(
+			rst     => rst,
+			clk     => clk,
+			data    => ddata_w,
+			address => daddress,
+			we      => d_we,
+			signal_ext => d_sig,
+			csel    => dcsel(0),
+			dmask   => dmask,
+			q       => ddata_r_mem
+		);
+
+	-- Adress space mux ((check sections.ld) -> Data chip select:
+	-- 0x00000    ->    Instruction memory
+	-- 0x20000    ->    Data memory
+	-- 0x40000    ->    Input/Output generic address space
+	-- 0x60000    ->    SDRAM address space
+	data_bus_mux: entity work.databusmux
+	    port map(
+	        dcsel          => dcsel,
+	        idata          => idata,
+	        ddata_r_mem    => ddata_r_mem,
+	        ddata_r_periph => ddata_r_periph,
+	        ddata_r_sdram  => ddata_r_sdram,
+	        ddata_r        => ddata_r
+	    );
+		
+    io_data_bus_mux: entity work.iodatabusmux
+        port map(
+            daddress => daddress,
+            ddata_r_gpio => ddata_r_gpio,
+            ddata_r_segments => ddata_r_segments,
+            ddata_r_uart => ddata_r_uart,
+            ddata_r_adc => ddata_r_adc,
+            ddata_r_i2c => ddata_r_i2c,
+            ddata_r_timer => ddata_r_timer,
+            ddata_r_stepmot => ddata_r_stepmot,
+            ddata_r_periph => ddata_r_periph
+        );
+
+	-- Softcore instatiation
+	myRiscv : entity work.core
+		port map(
+			clk      => clk,
+			rst      => rst,
+			clk_32x  => clk_32x,
+			iaddress => iaddress,
+			idata    => idata,
+			daddress => daddress,
+			ddata_r  => ddata_r,
+			ddata_w  => ddata_w,
+			d_we     => d_we,
+			d_rd     => d_rd,
+			d_sig	 => d_sig,
+			dcsel    => dcsel,
+			dmask    => dmask,
+			interrupts=>interrupts,
+			state    => cpu_state
+		);
+    
+    -- Group IRQ signals.
+	irq_signals: process(timer_interrupt,gpio_interrupts)
+	begin
+	   interrupts <= (others => '0');
+       interrupts(24 downto 18) <= gpio_interrupts(6 downto 0);
+       interrupts(30 downto 25) <= timer_interrupt;
+    end process;
+
+    
+	-- Timer instantiation
+	timer : entity work.Timer
+	generic map(
+	    prescaler_size => 16,
+	    compare_size   => 32
+	)
+	port map(
+	    clock       => clk,
+	    reset       => rst,
+	    daddress => daddress,
+	    ddata_w  => ddata_w,
+	    ddata_r  => ddata_r_timer,
+	    d_we     => d_we,
+	    d_rd     => d_rd,
+	    dcsel    => dcsel,
+	    dmask    => dmask,
+	    timer_interrupt => timer_interrupt
+	);
+	
+	-- Generic GPIO module instantiation
+    generic_gpio: entity work.gpio
+    port map(
+        clk      => clk,
+        rst      => rst,
+        daddress => daddress,
+        ddata_w  => ddata_w,
+        ddata_r  => ddata_r_gpio,
+        d_we     => d_we,
+        d_rd     => d_rd,
+        dcsel    => dcsel,
+        dmask    => dmask,
+        input    => gpio_input,
+        output   => gpio_output,
+        gpio_interrupts => gpio_interrupts
+    );
+
+	generic_displays : entity work.led_displays      
+        port map(
+            clk      => clk,
+            rst      => rst,
+            daddress => daddress,
+            ddata_w  => ddata_w,
+            ddata_r  => ddata_r_segments,
+            d_we     => d_we,
+            d_rd     => d_rd,
+            dcsel    => dcsel,
+            dmask    => dmask,
+            hex0     => HEX0,
+            hex1     => HEX1,
+            hex2     => HEX2,
+            hex3     => HEX3,
+            hex4     => HEX4,
+            hex5     => HEX5,
+            hex6     => open,
+            hex7     => open
+        );
+        
+    -- Stepmotor instantiation
+    motor0: entity work.stepmotor
+        port map(
+            clk       => clk,
+            rst       => rst,
+            daddress  => daddress,
+            ddata_w   => ddata_w,
+            ddata_r   => ddata_r,
+            d_we      => d_we,
+            d_rd      => d_rd,
+            dcsel     => dcsel,
+            dmask     => dmask,
+            reverse   => reverse,
+            stop      => stop,
+            half_full => half_full,
+            speed     => speed,
+            in1       => in1,
+            in2       => in2,
+            in3       => in3,
+            in4       => in4
+        );
+
+	-- FileOutput DEBUG	
+	debug : entity work.trace_debug
+	generic map(
+		MEMORY_WORDS => IMEMORY_WORDS
+	)
+	port map(
+		pc   => iaddress,
+		data => idata,
+		inst => debugString
+	);
+
+end architecture RTL;
diff --git a/peripherals/step_motor/vsim.wlf b/peripherals/step_motor/vsim.wlf
index d63a48da..71d1508a 100644
Binary files a/peripherals/step_motor/vsim.wlf and b/peripherals/step_motor/vsim.wlf differ
diff --git a/peripherals/step_motor/work/_info b/peripherals/step_motor/work/_info
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diff --git a/work/_lib.qdb b/work/_lib.qdb
new file mode 100644
index 00000000..23fe3ff9
Binary files /dev/null and b/work/_lib.qdb differ
diff --git a/peripherals/step_motor/work/_lib1_0.qdb b/work/_lib1_0.qdb
similarity index 77%
rename from peripherals/step_motor/work/_lib1_0.qdb
rename to work/_lib1_0.qdb
index ff858cb3..571fd4b5 100644
Binary files a/peripherals/step_motor/work/_lib1_0.qdb and b/work/_lib1_0.qdb differ
diff --git a/work/_lib1_0.qpg b/work/_lib1_0.qpg
new file mode 100644
index 00000000..967a7a47
Binary files /dev/null and b/work/_lib1_0.qpg differ
diff --git a/work/_lib1_0.qtl b/work/_lib1_0.qtl
new file mode 100644
index 00000000..23480e5f
Binary files /dev/null and b/work/_lib1_0.qtl differ
diff --git a/work/_vmake b/work/_vmake
new file mode 100644
index 00000000..37aa36a8
--- /dev/null
+++ b/work/_vmake
@@ -0,0 +1,4 @@
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