diff --git a/peripherals/timer/Timer.vhd.bak b/peripherals/timer/Timer.vhd.bak deleted file mode 100644 index 2037f8c4..00000000 --- a/peripherals/timer/Timer.vhd.bak +++ /dev/null @@ -1,456 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity Timer is - generic( - DADDRESS_BUS_SIZE : integer := 32; - prescaler_size : integer := 16; - compare_size : integer := 32 - ); - port( - clock : in std_logic; - reset : in std_logic; - daddress : in unsigned(DADDRESS_BUS_SIZE-1 downto 0); - ddata_w : in std_logic_vector(31 downto 0); - ddata_r : out std_logic_vector(31 downto 0); - d_we : in std_logic; - d_rd : in std_logic; - dcsel : in std_logic_vector(1 downto 0); - dmask : in std_logic_vector(3 downto 0); - timer_interrupt : out std_logic_vector(5 downto 0); - - -- changes rk -- - ifcap : in std_logic ; -- capture flag - ------------ - - out_A : out std_logic_vector(2 downto 0); - out_B : out std_logic_vector(2 downto 0) - ); -end entity Timer; - -architecture RTL of Timer is - signal counter : unsigned(31 downto 0) := (others => '0'); - signal internal_clock : std_logic := '1'; - signal internal_counter_direction : std_logic := '0'; -- @suppress "signal internal_counter_direction is never read" - -- type counter_direction_t is (Up, Down); - - -- TIMER Signals - signal timer_reset : std_logic; - -- signal timer_mode : unsigned(1 downto 0); original - signal timer_mode : unsigned(2 downto 0); - signal prescaler : unsigned(prescaler_size - 1 downto 0); - signal top_counter : unsigned(31 downto 0); - signal compare_0A : unsigned(31 downto 0); - signal compare_1A : unsigned(31 downto 0); - signal compare_2A : unsigned(31 downto 0); - signal compare_0B : unsigned(31 downto 0); - signal compare_1B : unsigned(31 downto 0); - signal compare_2B : unsigned(31 downto 0); - - signal output_A : std_logic_vector(2 downto 0); - signal output_B : std_logic_vector(2 downto 0); - - signal captured_time : std_logic_vector(31 downto 0) := (others => '0'); - - signal enable_timer_irq_mask : std_logic_vector(31 downto 0); - - signal myInterrupts_d : std_logic_vector(5 downto 0); - signal interrupts: std_logic_vector(5 downto 0); - signal interrupts_holder: std_logic_vector(5 downto 0); - - constant TIMER_BASE_ADDRESS : unsigned(15 downto 0):=x"0050"; -begin - - interrupts_holder<=output_B(2) & output_A(2) & output_B(1) & output_A(1) & output_B(0) & output_A(0) ; - interrupts <= interrupts_holder and enable_timer_irq_mask(5 downto 0); - - - interrupt_edge : process (clock, reset) is - begin - if reset = '1' then - myInterrupts_d <= (others => '0'); - timer_interrupt<=(others => '0'); - elsif rising_edge(clock) then - - myInterrupts_d <= interrupts; - timer_interrupt <= not myInterrupts_d and interrupts; - - end if; - end process interrupt_edge; - - -- Output register - p0: process(clock, reset) - begin - if reset = '1' then - timer_reset<='0'; - timer_mode <="000"; - prescaler <= (others => '0'); - top_counter<= (others => '0'); - compare_0A <= (others => '0'); - compare_0B <= (others => '0'); - compare_1A <= (others => '0'); - compare_1B <= (others => '0'); - compare_2A <= (others => '0'); - compare_2B <= (others => '0'); - enable_timer_irq_mask<=(others => '0'); - else - if rising_edge(clock) then - if (d_we = '1') and (dcsel = "10") then - -- ToDo: Simplify compartors - -- ToDo: Maybe use byte addressing? - -- x"01" (word addressing) is x"04" (byte addressing) - - if daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"0000") then -- TIMER_ADDRESS - timer_reset <= ddata_w(0); - elsif daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"0001") then -- TIMER_ADDRESS - timer_mode <= unsigned(ddata_w(2 downto 0)); - elsif daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"0002") then -- TIMER_ADDRESS - prescaler <= unsigned(ddata_w(prescaler_size - 1 downto 0)); - elsif daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"0003") then -- TIMER_ADDRESS - top_counter <= unsigned(ddata_w); - elsif daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"0004") then -- TIMER_ADDRESS - compare_0A <= unsigned(ddata_w); - elsif daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"0005") then -- TIMER_ADDRESS - compare_0B <= unsigned(ddata_w); - elsif daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"0006") then -- TIMER_ADDRESS - compare_1A <= unsigned(ddata_w); - elsif daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"0007") then -- TIMER_ADDRESS - compare_1B <= unsigned(ddata_w); - elsif daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"0008") then -- TIMER_ADDRESS - compare_2A <= unsigned(ddata_w); - elsif daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"0009") then -- TIMER_ADDRESS - compare_2B <= unsigned(ddata_w); - elsif daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"000b") then -- TIMER_ADDRESS - enable_timer_irq_mask <= ddata_w; - end if; - end if; - end if; - end if; - end process p0; - - -- Input register - pi: process(clock, reset) - begin - if reset = '1' then - ddata_r <= (others => '0'); - else - if rising_edge(clock) then - ddata_r <= (others => '0'); - if (d_rd = '1') and (dcsel = "10") then - if daddress(15 downto 0) = (TIMER_BASE_ADDRESS +x"0000") then - --ddata_r(4 downto 0) <= SW(4 downto 0); - elsif daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"0004")then - --ddata_r(7 downto 0) <= data_out; - elsif daddress(15 downto 0) =(TIMER_BASE_ADDRESS + x"000a") then - ddata_r(2 downto 0) <= output_A(2 downto 0); - ddata_r(5 downto 3) <= output_B(2 downto 0); - elsif daddress(15 downto 0) = (TIMER_BASE_ADDRESS + x"000c") then - ddata_r <= captured_time; - end if; - end if; - end if; - end if; - - end process pi; - - - p1 : process(clock, reset, prescaler) is - variable temp_counter : unsigned(prescaler_size - 1 downto 0) := (others => '0'); - begin - if reset = '1' then - temp_counter := (others => '0'); - internal_clock <= '0'; - else - if prescaler /= x"0001" then - if rising_edge(clock) then - temp_counter := temp_counter + 1; - if temp_counter >= prescaler - 1 then - internal_clock <= not (internal_clock); - temp_counter := (others => '0'); - else - internal_clock <= '1'; -- todo - end if; - else - -- internal_clock <= ''; - end if; - else - internal_clock <= clock; - end if; - end if; - end process p1; - - p2 : process(internal_clock, reset) is - variable internal_output_A : std_logic_vector(2 downto 0) := (others => '0'); - variable internal_output_B : std_logic_vector(2 downto 0) := (others => '0'); - variable counter_direction : std_logic := '0'; - --variable time : std_logic_vector(31 downto 0) := (others => '0'); - variable ifc : std_logic := '0'; - begin - if reset = '1' then - internal_output_A := (others => '0'); - internal_output_B := (others => '0'); - output_A <= internal_output_A; - output_B <= internal_output_B; - counter_direction := '0'; - ifc := '0'; - else - if rising_edge(internal_clock) then - if timer_reset = '1' then - internal_output_A := (others => '0'); - internal_output_B := (others => '0'); - counter <= (others => '0'); - counter_direction := '0'; - captured_time <= (others => '0'); - else - case timer_mode is - when "000" => -- one shot mode - - if counter >= compare_0A - 1 then - internal_output_A(0) := '1'; - else - internal_output_A(0) := '0'; - counter <= counter + 1; - end if; - - if counter >= compare_0B - 1 then - internal_output_B(0) := '1'; - else - internal_output_B(0) := '0'; - counter <= counter + 1; - end if; - - if counter >= compare_1A - 1 then - internal_output_A(1) := '1'; - else - internal_output_A(1) := '0'; - counter <= counter + 1; - end if; - - if counter >= compare_1B - 1 then - internal_output_B(1) := '1'; - else - internal_output_B(1) := '0'; - counter <= counter + 1; - end if; - - if counter >= compare_2A - 1 then - internal_output_A(2) := '1'; - else - internal_output_A(2) := '0'; - counter <= counter + 1; - end if; - - if counter >= compare_2B - 1 then - internal_output_B(2) := '1'; - else - internal_output_B(2) := '0'; - counter <= counter + 1; - end if; - - when "011" => -- clear on compare mode, counter is as sawtooth wave - - -- the counter resets if reaches B comparator. - -- the output has a rectangular waveform like a simple PWM, but active when between A and B comparators - if counter >= top_counter - 1 then - counter <= (others => '0'); - else - counter <= counter + 1; - end if; - - if (counter >= compare_0A - 1) and (counter < compare_0B - 1) then - internal_output_A(0) := '1'; - internal_output_B(0) := '0'; - else - internal_output_A(0) := '0'; - internal_output_B(0) := '1'; - end if; - - if (counter >= compare_1A - 1) and (counter < compare_1B - 1) then - internal_output_A(1) := '1'; - internal_output_B(1) := '0'; - else - internal_output_A(1) := '0'; - internal_output_B(1) := '1'; - end if; - - if (counter >= compare_2A - 1) and (counter < compare_2B - 1) then - internal_output_A(2) := '1'; - internal_output_B(2) := '0'; - else - internal_output_A(2) := '0'; - internal_output_B(2) := '1'; - end if; - - when "010" => -- clear on compare mode, counter is a centered triangle wave - - -- the counter change its direction (up or down) when it reaches its maximum possible value - -- the output has a rectangular waveform centered to the top value, active when between A and B comparators. - if counter_direction = '0' then - if counter >= top_counter - 1 then - counter_direction := '1'; - counter <= counter - 1; - else - counter <= counter + 1; - end if; - - if counter >= compare_0A - 1 then - internal_output_A(0) := '1'; - else - internal_output_A(0) := '0'; - end if; - - if counter >= compare_0B - 1 then - internal_output_B(0) := '0'; - else - internal_output_B(0) := '1'; - end if; - - if counter >= compare_1A - 1 then - internal_output_A(1) := '1'; - else - internal_output_A(1) := '0'; - end if; - - if counter >= compare_1B - 1 then - internal_output_B(1) := '0'; - else - internal_output_B(1) := '1'; - end if; - - if counter >= compare_2A - 1 then - internal_output_A(2) := '1'; - else - internal_output_A(2) := '0'; - end if; - - if counter >= compare_2B - 1 then - internal_output_B(2) := '0'; - else - internal_output_B(2) := '1'; - end if; - - else - if counter <= 0 then - counter_direction := '0'; - counter <= counter + 1; - else - counter <= counter - 1; - end if; - - if counter > compare_0A - 1 then - internal_output_A(0) := '1'; - else - internal_output_A(0) := '0'; - end if; - - if counter > compare_0B - 1 then - internal_output_B(0) := '0'; - else - internal_output_B(0) := '1'; - end if; - - if counter > compare_1A - 1 then - internal_output_A(1) := '1'; - else - internal_output_A(1) := '0'; - end if; - - if counter > compare_1B - 1 then - internal_output_B(1) := '0'; - else - internal_output_B(1) := '1'; - end if; - - if counter > compare_2A - 1 then - internal_output_A(2) := '1'; - else - internal_output_A(2) := '0'; - end if; - - if counter > compare_2B - 1 then - internal_output_B(2) := '0'; - else - internal_output_B(2) := '1'; - end if; - - end if; - - internal_counter_direction <= counter_direction; - - when "001" => -- clear on top mode, counter is as sawtooth wave - - -- the counter resets if reaches its maximum possible value - -- the output has a rectangular waveform like a simple PWM - if counter >= top_counter - 1 then - counter <= (others => '0'); - else - counter <= counter + 1; - end if; - - if counter >= compare_0A - 1 then - internal_output_A(0) := '1'; - else - internal_output_A(0) := '0'; - end if; - - if counter >= compare_0B - 1 then - internal_output_B(0) := '1'; - else - internal_output_B(0) := '0'; - end if; - - if counter >= compare_1A - 1 then - internal_output_A(1) := '1'; - else - internal_output_A(1) := '0'; - end if; - - if counter >= compare_1B - 1 then - internal_output_B(1) := '1'; - else - internal_output_B(1) := '0'; - end if; - - if counter >= compare_2A - 1 then - internal_output_A(2) := '1'; - else - internal_output_A(2) := '0'; - end if; - - if counter >= compare_2B - 1 then - internal_output_B(2) := '1'; - else - internal_output_B(2) := '0'; - end if; - - when "100" => -- capture timer - if ifcap = '1' and ifc = '0' then - captured_time <= std_logic_vector(counter); - ifc := '1'; - elsif ifcap = '0' then - ifc := '0'; - end if; - - counter <= counter +1; - - when others => -- none / error - internal_output_A := (others => '0'); - internal_output_B := (others => '0'); - - end case; - end if; - end if; - - output_A <= internal_output_A; - output_B <= internal_output_B; - - end if; - - out_A <= output_A; - out_B <= output_B; - - end process p2; - - -end architecture RTL; diff --git a/peripherals/timer/sim.s b/peripherals/timer/sim.s deleted file mode 100644 index 8e524487..00000000 --- a/peripherals/timer/sim.s +++ /dev/null @@ -1,51 +0,0 @@ -0: 30047073 : csrrci x8, x0, 768 - -4: 00001297 : auipc x5, 0x1000 -8: 91428293 : addi x5, x5, -1772 -C: 30729073 : csrrw x5, x7, 775 - -10: 00001297 : auipc x5, 0x1000 -14: 86028293 : addi x5, x5, -1952 -18: 7EC29073 : csrrw x5, x12, 2028 - -1C: 7EC0E073 : csrrsi x1, x12, 2028 - -20: 00000297 : auipc x5, 0x0 -24: 78828293 : addi x5, x5, 1928 -28: 30529073 : csrrw x5, x5, 773 - -2C: 02001137 : lui x2, 0x2001000 -30: 80010113 : addi x2, x2, -2048 -34: 020001B7 : lui x3, 0x2000000 -38: 00018193 : addi x3, x3, 0 -3C: FF010113 : addi x2, x2, -16 -40: 00012023 : sw x0, 0(x2) -44: 00012223 : sw x0, 4(x2) -48: 00012423 : sw x0, 8(x2) -4C: 00012623 : sw x0, 12(x2) -50: 3A4000EF : jal x1, 932 - -3F4: FF010113 : addi x2, x2, -16 -3F8: 00112623 : sw x1, 12(x2) -3FC: F6DFF0EF : jal x1, -148 - -368: 04000737 : lui x14, 0x4000000 -36C: 00100693 : addi x13, x0, 1 -370: 14D72023 : sw x13, 320(x14) -374: 00500693 : addi x13, x0, 5 -378: 14D72223 : sw x13, 324(x14) -37C: 00200613 : addi x12, x0, 2 -380: 14C72423 : sw x12, 328(x14) -384: 01400593 : addi x11, x0, 20 -388: 14B72623 : sw x11, 332(x14) -38C: 16C72A23 : sw x12, 372(x14) -390: 14D72823 : sw x13, 336(x14) -394: 00A00693 : addi x13, x0, 10 -398: 14D72C23 : sw x13, 344(x14) -39C: 00E00693 : addi x13, x0, 14 -3A0: 16D72023 : sw x13, 352(x14) -3A4: 14072023 : sw x0, 320(x14) -3A8: 00008067 : jalr x0, 0(x1) - -400: 0000006F : jal x0, 0 - diff --git a/peripherals/timer/vsim.wlf b/peripherals/timer/vsim.wlf deleted file mode 100644 index e8ffd11f..00000000 Binary files a/peripherals/timer/vsim.wlf and /dev/null differ diff --git a/peripherals/timer/wave.ps b/peripherals/timer/wave.ps deleted file mode 100644 index 8a55d2d2..00000000 Binary files a/peripherals/timer/wave.ps and /dev/null differ