From 9d22272a060ad20f17bba317fdfe3ced3e76f7a7 Mon Sep 17 00:00:00 2001
From: StanisLK <74256083+StanisLK@users.noreply.github.com>
Date: Tue, 10 Sep 2024 15:57:26 -0300
Subject: [PATCH] Stanis lk patch 1 (#75)

* Create Readme.md

* Add files via upload

* Update Readme.md

* Create de10_lite.vhd

* Add files via upload

* Delete peripherals/encoder/sintese.zip
---
 peripherals/encoder/Readme.md               |  64 ++++
 peripherals/encoder/encoder.vhd             |  74 ++++
 peripherals/encoder/seven_segment_cntrl.vhd |  62 ++++
 peripherals/encoder/sint/de10_lite.qpf      |  30 ++
 peripherals/encoder/sint/de10_lite.qsf      | 364 ++++++++++++++++++++
 peripherals/encoder/sint/de10_lite.sdc      |  86 +++++
 peripherals/encoder/sint/de10_lite.vhd      | 125 +++++++
 peripherals/encoder/testbench_encoder.vhd   |  61 ++++
 8 files changed, 866 insertions(+)
 create mode 100644 peripherals/encoder/Readme.md
 create mode 100644 peripherals/encoder/encoder.vhd
 create mode 100644 peripherals/encoder/seven_segment_cntrl.vhd
 create mode 100644 peripherals/encoder/sint/de10_lite.qpf
 create mode 100644 peripherals/encoder/sint/de10_lite.qsf
 create mode 100644 peripherals/encoder/sint/de10_lite.sdc
 create mode 100644 peripherals/encoder/sint/de10_lite.vhd
 create mode 100644 peripherals/encoder/testbench_encoder.vhd

diff --git a/peripherals/encoder/Readme.md b/peripherals/encoder/Readme.md
new file mode 100644
index 00000000..79b61fee
--- /dev/null
+++ b/peripherals/encoder/Readme.md
@@ -0,0 +1,64 @@
+# Encoder Frequency Measurement
+
+Este projeto VHDL implementa uma contagem de pulsos de um encoder e calcula a frequência desses pulsos com base em um período de tempo configurável. O código permite selecionar diferentes períodos de medição e calcula a frequência em Hz (pulsos por segundo).
+
+## Exemplo prático
+
+Abaixo temos o exemplo de um sinal de 53 kHZ sendo injetado na placa, para que seja feita a medição de sua frequencia através do periférico implementado.
+
+![placafrequencia2](https://github.com/user-attachments/assets/9359def6-587d-4871-8f45-2e44bb7a2341)
+![placafrequencia](https://github.com/user-attachments/assets/d2db3114-3129-4139-8568-bb752e0e1ee2)
+
+O valor medido é apresentado no display em formato hexadecimal, ou seja, CF08, que convertido a decimal, nos dá exatamente 53k, igual a frequencia do sinal injetado.
+
+## Entidade `encoder`
+
+A entidade `encoder` recebe os seguintes sinais de entrada e saída:
+
+### Entradas:
+- `clk`: Sinal de clock do sistema (50 MHz assumido).
+- `aclr_n`: Sinal de reset ativo em baixo.
+- `select_time`: Vetor de 3 bits para seleção do período de medição.
+  - "000" -> 1 ms
+  - "001" -> 10 ms
+  - "010" -> 100 ms
+  - "011" -> 1000 ms
+- `encoder_pulse`: Sinal de pulso do encoder.
+
+### Saídas:
+- `frequency`: Frequência dos pulsos do encoder em Hz, é possivel medir frequencias de até 4 Mhz com esta aplicação, devido a limitação do tamanho do registrador utilizado em pulse counter.
+
+## Arquitetura `rtl`
+
+A arquitetura `rtl` define o seguinte comportamento:
+
+1. **Seleção do Período de Medição:**
+   - O `select_time` define o tempo de medição. O tempo é armazenado no sinal `time_period` e um multiplicador é ajustado para converter a contagem de pulsos em frequência (Hz).
+   - Períodos disponíveis: 1 ms, 10 ms, 100 ms, e 1000 ms.
+
+2. **Contagem de Pulsos:**
+   - Um contador (`time_counter`) é incrementado a cada ciclo de clock até atingir o valor do `time_period`.
+   - Quando o contador de tempo atinge o período definido, a frequência é calculada multiplicando a contagem de pulsos (`pulse_count`) pelo multiplicador apropriado para gerar a frequência em Hz.
+
+3. **Reinicialização e Contagem:**
+   - A cada intervalo de tempo definido, o contador de pulsos é resetado, e um novo cálculo de frequência é feito.
+   - O sinal de controle `flag` garante que o contador de pulsos seja resetado corretamente no final de cada período de medição.
+
+## Como Utilizar
+
+- Atribua um valor de entrada ao vetor `select_time` para definir o período de medição desejado.
+- Aplique o sinal do encoder no `encoder_pulse`.
+- A frequência calculada será disponibilizada na saída `frequency` em pulsos por segundo.
+
+## Sinais Importantes
+
+- `pulse_count`: Contador de pulsos do encoder.
+- `time_period`: Período de contagem selecionado.
+- `time_counter`: Contador de tempo baseado no clock.
+- `multiplicador`: Fator para converter a contagem de pulsos na frequência adequada.
+
+Este código é útil para sistemas que necessitam medir a frequência de pulsos de um encoder, como em aplicações de controle de motores ou medição de velocidade de rotação.
+
+
+
+
diff --git a/peripherals/encoder/encoder.vhd b/peripherals/encoder/encoder.vhd
new file mode 100644
index 00000000..1f042014
--- /dev/null
+++ b/peripherals/encoder/encoder.vhd
@@ -0,0 +1,74 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity encoder is
+    port (
+        clk         : in  std_logic;                     
+        aclr_n      : in  std_logic;                     
+        select_time : in  std_logic_vector(2 downto 0);          
+        encoder_pulse : in std_logic;                    
+        frequency   : out unsigned(31 downto 0)          
+    );
+end entity encoder;
+
+architecture rtl of encoder is
+    signal pulse_count  : unsigned(21 downto 0) := (others => '0');
+    signal time_period  : unsigned(31 downto 0);
+    signal multiplicador: unsigned(9 downto 0):= (others => '0');
+    signal time_counter : unsigned(31 downto 0) := (others => '0');
+    signal flag         : std_logic := '0';  -- Sinal para reiniciar pulse_count
+
+begin
+
+
+    process(select_time)
+    begin
+        case select_time is
+            when "000" => time_period <= to_unsigned(50000, 32);-- 1ms (assumindo clock de 50 MHz)
+               multiplicador <= to_unsigned(1000, 10);
+           when "001" => time_period <= to_unsigned(500000, 32);  -- 10ms
+               multiplicador <= to_unsigned(100, 10);
+           when "010" => time_period <= to_unsigned(5000000, 32); -- 100ms
+               multiplicador <= to_unsigned(10, 10);
+           when "011" => time_period <= to_unsigned(50000000, 32); -- 1000ms
+               multiplicador <= to_unsigned(1, 10);
+           when others => time_period <= to_unsigned(50000, 32); -- Default para 1ms
+           multiplicador <= to_unsigned(1000, 10);
+        end case;
+    end process;
+
+    -- Contagem dos pulsos do clock
+    process(aclr_n, clk)
+    begin
+        if aclr_n = '0' then
+            time_counter <= (others => '0');
+            frequency <= (others => '0');
+        elsif flag = '1' then
+          flag <= '0';
+        elsif rising_edge(clk) then
+            if time_counter < time_period then
+                time_counter <= time_counter + 1;
+            else
+                time_counter <= (others => '0');
+                frequency <= pulse_count*multiplicador;  -- Frequência em pulsos por período (Hz)
+                flag <= '1';  -- Garante que o flag seja resetado no início
+            end if;
+        end if;
+    end process;
+
+    -- Contagem dos pulsos do encoder
+    process(aclr_n, encoder_pulse,flag)
+        variable q_var : unsigned(21 downto 0) := (others => '0');
+    begin
+        if aclr_n = '0' then
+          q_var := (others => '0');
+        elsif flag = '1' then
+          q_var := (others => '0');
+        elsif rising_edge(encoder_pulse) then
+            q_var := q_var + 1;
+        end if;
+        pulse_count <= q_var;
+    end process;
+
+end architecture rtl;
diff --git a/peripherals/encoder/seven_segment_cntrl.vhd b/peripherals/encoder/seven_segment_cntrl.vhd
new file mode 100644
index 00000000..7785466e
--- /dev/null
+++ b/peripherals/encoder/seven_segment_cntrl.vhd
@@ -0,0 +1,62 @@
+-------------------------------------------------------------------
+-- name        : seven_segment_cntrl.vhd
+-- author      : Stanislau de Lira Kaszubowski
+-- data        : 02/04/2024
+-- copyright   : Instituto Federal de Santa Catarina
+-- description : Traduz uma entrada de 4 bits para o acionamento de um display de 7 segmentos.
+------------------------------------------------------------------- 
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity seven_segment_cntrl is
+    port (
+        input: in unsigned (4-1 downto 0);
+        segs : out std_logic_vector (7 downto 0)
+    );
+end entity seven_segment_cntrl;
+
+architecture rtl of seven_segment_cntrl is
+begin
+
+   process (input)
+   begin
+       case input is
+        when "0000" =>
+            segs <= "11000000"; --0
+        when "0001" =>
+            segs <= "11111001"; --1
+        when "0010" =>
+            segs <= "10100100"; --2
+        when "0011" =>
+            segs <= "10110000"; --3
+        when "0100" =>
+            segs <= "10011001"; --4
+        when "0101" =>
+            segs <= "10010010"; --5
+        when "0110" =>
+            segs <= "10000010"; --6
+        when "0111" =>
+            segs <= "11111000"; --7
+        when "1000" =>
+            segs <= "10000000"; --8
+        when "1001" =>
+            segs <= "10010000"; --9
+        when "1010" =>
+            segs <= "10001000"; -- A 
+        when "1011" =>
+            segs <= "10000011"; -- b
+        when "1100" =>
+            segs <= "11000110"; -- C
+        when "1101" =>
+            segs <= "10100001"; -- d
+        when "1110" =>
+            segs <= "10000110"; -- E
+        when "1111" =>
+            segs <= "10001110"; -- F
+        when others =>
+            segs <= "00000000"; -- Default (off)
+        end case;
+    end process;
+
+end architecture rtl;
\ No newline at end of file
diff --git a/peripherals/encoder/sint/de10_lite.qpf b/peripherals/encoder/sint/de10_lite.qpf
new file mode 100644
index 00000000..c44f1c80
--- /dev/null
+++ b/peripherals/encoder/sint/de10_lite.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
+# Date created = 09:41:06  April 06, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "09:41:06  April 06, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "de10_lite"
diff --git a/peripherals/encoder/sint/de10_lite.qsf b/peripherals/encoder/sint/de10_lite.qsf
new file mode 100644
index 00000000..af6804c8
--- /dev/null
+++ b/peripherals/encoder/sint/de10_lite.qsf
@@ -0,0 +1,364 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2018  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition
+# Date created = 09:41:06  April 06, 2020
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		de10_lite_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M50DAF484C7G
+set_global_assignment -name TOP_LEVEL_ENTITY de10_lite
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:41:06  APRIL 06, 2020"
+set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_location_assignment PIN_N5 -to ADC_CLK_10
+set_location_assignment PIN_P11 -to MAX10_CLK1_50
+set_location_assignment PIN_N14 -to MAX10_CLK2_50
+set_location_assignment PIN_U17 -to DRAM_ADDR[0]
+set_location_assignment PIN_W19 -to DRAM_ADDR[1]
+set_location_assignment PIN_V18 -to DRAM_ADDR[2]
+set_location_assignment PIN_U18 -to DRAM_ADDR[3]
+set_location_assignment PIN_U19 -to DRAM_ADDR[4]
+set_location_assignment PIN_T18 -to DRAM_ADDR[5]
+set_location_assignment PIN_T19 -to DRAM_ADDR[6]
+set_location_assignment PIN_R18 -to DRAM_ADDR[7]
+set_location_assignment PIN_P18 -to DRAM_ADDR[8]
+set_location_assignment PIN_P19 -to DRAM_ADDR[9]
+set_location_assignment PIN_T20 -to DRAM_ADDR[10]
+set_location_assignment PIN_P20 -to DRAM_ADDR[11]
+set_location_assignment PIN_R20 -to DRAM_ADDR[12]
+set_location_assignment PIN_T21 -to DRAM_BA[0]
+set_location_assignment PIN_T22 -to DRAM_BA[1]
+set_location_assignment PIN_U21 -to DRAM_CAS_N
+set_location_assignment PIN_N22 -to DRAM_CKE
+set_location_assignment PIN_L14 -to DRAM_CLK
+set_location_assignment PIN_U20 -to DRAM_CS_N
+set_location_assignment PIN_Y21 -to DRAM_DQ[0]
+set_location_assignment PIN_Y20 -to DRAM_DQ[1]
+set_location_assignment PIN_AA22 -to DRAM_DQ[2]
+set_location_assignment PIN_AA21 -to DRAM_DQ[3]
+set_location_assignment PIN_Y22 -to DRAM_DQ[4]
+set_location_assignment PIN_W22 -to DRAM_DQ[5]
+set_location_assignment PIN_W20 -to DRAM_DQ[6]
+set_location_assignment PIN_V21 -to DRAM_DQ[7]
+set_location_assignment PIN_P21 -to DRAM_DQ[8]
+set_location_assignment PIN_J22 -to DRAM_DQ[9]
+set_location_assignment PIN_H21 -to DRAM_DQ[10]
+set_location_assignment PIN_H22 -to DRAM_DQ[11]
+set_location_assignment PIN_G22 -to DRAM_DQ[12]
+set_location_assignment PIN_G20 -to DRAM_DQ[13]
+set_location_assignment PIN_G19 -to DRAM_DQ[14]
+set_location_assignment PIN_F22 -to DRAM_DQ[15]
+set_location_assignment PIN_V22 -to DRAM_LDQM
+set_location_assignment PIN_U22 -to DRAM_RAS_N
+set_location_assignment PIN_J21 -to DRAM_UDQM
+set_location_assignment PIN_V20 -to DRAM_WE_N
+set_location_assignment PIN_C14 -to HEX0[0]
+set_location_assignment PIN_E15 -to HEX0[1]
+set_location_assignment PIN_C15 -to HEX0[2]
+set_location_assignment PIN_C16 -to HEX0[3]
+set_location_assignment PIN_E16 -to HEX0[4]
+set_location_assignment PIN_D17 -to HEX0[5]
+set_location_assignment PIN_C17 -to HEX0[6]
+set_location_assignment PIN_D15 -to HEX0[7]
+set_location_assignment PIN_C18 -to HEX1[0]
+set_location_assignment PIN_D18 -to HEX1[1]
+set_location_assignment PIN_E18 -to HEX1[2]
+set_location_assignment PIN_B16 -to HEX1[3]
+set_location_assignment PIN_A17 -to HEX1[4]
+set_location_assignment PIN_A18 -to HEX1[5]
+set_location_assignment PIN_B17 -to HEX1[6]
+set_location_assignment PIN_A16 -to HEX1[7]
+set_location_assignment PIN_B20 -to HEX2[0]
+set_location_assignment PIN_A20 -to HEX2[1]
+set_location_assignment PIN_B19 -to HEX2[2]
+set_location_assignment PIN_A21 -to HEX2[3]
+set_location_assignment PIN_B21 -to HEX2[4]
+set_location_assignment PIN_C22 -to HEX2[5]
+set_location_assignment PIN_B22 -to HEX2[6]
+set_location_assignment PIN_A19 -to HEX2[7]
+set_location_assignment PIN_F21 -to HEX3[0]
+set_location_assignment PIN_E22 -to HEX3[1]
+set_location_assignment PIN_E21 -to HEX3[2]
+set_location_assignment PIN_C19 -to HEX3[3]
+set_location_assignment PIN_C20 -to HEX3[4]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_E17 -to HEX3[6]
+set_location_assignment PIN_D22 -to HEX3[7]
+set_location_assignment PIN_F18 -to HEX4[0]
+set_location_assignment PIN_E20 -to HEX4[1]
+set_location_assignment PIN_E19 -to HEX4[2]
+set_location_assignment PIN_J18 -to HEX4[3]
+set_location_assignment PIN_H19 -to HEX4[4]
+set_location_assignment PIN_F19 -to HEX4[5]
+set_location_assignment PIN_F20 -to HEX4[6]
+set_location_assignment PIN_F17 -to HEX4[7]
+set_location_assignment PIN_J20 -to HEX5[0]
+set_location_assignment PIN_K20 -to HEX5[1]
+set_location_assignment PIN_L18 -to HEX5[2]
+set_location_assignment PIN_N18 -to HEX5[3]
+set_location_assignment PIN_M20 -to HEX5[4]
+set_location_assignment PIN_N19 -to HEX5[5]
+set_location_assignment PIN_N20 -to HEX5[6]
+set_location_assignment PIN_L19 -to HEX5[7]
+set_location_assignment PIN_B8 -to KEY[0]
+set_location_assignment PIN_A7 -to KEY[1]
+set_location_assignment PIN_A8 -to LEDR[0]
+set_location_assignment PIN_A9 -to LEDR[1]
+set_location_assignment PIN_A10 -to LEDR[2]
+set_location_assignment PIN_B10 -to LEDR[3]
+set_location_assignment PIN_D13 -to LEDR[4]
+set_location_assignment PIN_C13 -to LEDR[5]
+set_location_assignment PIN_E14 -to LEDR[6]
+set_location_assignment PIN_D14 -to LEDR[7]
+set_location_assignment PIN_A11 -to LEDR[8]
+set_location_assignment PIN_B11 -to LEDR[9]
+set_location_assignment PIN_C10 -to SW[0]
+set_location_assignment PIN_C11 -to SW[1]
+set_location_assignment PIN_D12 -to SW[2]
+set_location_assignment PIN_C12 -to SW[3]
+set_location_assignment PIN_A12 -to SW[4]
+set_location_assignment PIN_B12 -to SW[5]
+set_location_assignment PIN_A13 -to SW[6]
+set_location_assignment PIN_A14 -to SW[7]
+set_location_assignment PIN_B14 -to SW[8]
+set_location_assignment PIN_F15 -to SW[9]
+set_location_assignment PIN_P1 -to VGA_B[0]
+set_location_assignment PIN_T1 -to VGA_B[1]
+set_location_assignment PIN_P4 -to VGA_B[2]
+set_location_assignment PIN_N2 -to VGA_B[3]
+set_location_assignment PIN_W1 -to VGA_G[0]
+set_location_assignment PIN_T2 -to VGA_G[1]
+set_location_assignment PIN_R2 -to VGA_G[2]
+set_location_assignment PIN_R1 -to VGA_G[3]
+set_location_assignment PIN_N3 -to VGA_HS
+set_location_assignment PIN_AA1 -to VGA_R[0]
+set_location_assignment PIN_V1 -to VGA_R[1]
+set_location_assignment PIN_Y2 -to VGA_R[2]
+set_location_assignment PIN_Y1 -to VGA_R[3]
+set_location_assignment PIN_N1 -to VGA_VS
+set_location_assignment PIN_AB16 -to GSENSOR_CS_N
+set_location_assignment PIN_Y14 -to GSENSOR_INT[1]
+set_location_assignment PIN_Y13 -to GSENSOR_INT[2]
+set_location_assignment PIN_AB15 -to GSENSOR_SCLK
+set_location_assignment PIN_V11 -to GSENSOR_SDI
+set_location_assignment PIN_V12 -to GSENSOR_SDO
+set_location_assignment PIN_AB5 -to ARDUINO_IO[0]
+set_location_assignment PIN_AB6 -to ARDUINO_IO[1]
+set_location_assignment PIN_AB7 -to ARDUINO_IO[2]
+set_location_assignment PIN_AB8 -to ARDUINO_IO[3]
+set_location_assignment PIN_AB9 -to ARDUINO_IO[4]
+set_location_assignment PIN_Y10 -to ARDUINO_IO[5]
+set_location_assignment PIN_AA11 -to ARDUINO_IO[6]
+set_location_assignment PIN_AA12 -to ARDUINO_IO[7]
+set_location_assignment PIN_AB17 -to ARDUINO_IO[8]
+set_location_assignment PIN_AA17 -to ARDUINO_IO[9]
+set_location_assignment PIN_AB19 -to ARDUINO_IO[10]
+set_location_assignment PIN_AA19 -to ARDUINO_IO[11]
+set_location_assignment PIN_Y19 -to ARDUINO_IO[12]
+set_location_assignment PIN_AB20 -to ARDUINO_IO[13]
+set_location_assignment PIN_AB21 -to ARDUINO_IO[14]
+set_location_assignment PIN_AA20 -to ARDUINO_IO[15]
+set_location_assignment PIN_F16 -to ARDUINO_RESET_N
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7]
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15]
+set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to ARDUINO_RESET_N
+set_global_assignment -name VHDL_FILE ../../seven_segment_cntrl.vhd
+set_global_assignment -name VHDL_FILE ../../encoder.vhd
+set_global_assignment -name VHDL_FILE ../../logica7.vhd
+set_global_assignment -name SOURCE_FILE Spf1.spf
+set_global_assignment -name VHDL_FILE ../../counter.vhd
+set_global_assignment -name QSYS_FILE probes.qsys
+set_global_assignment -name SDC_FILE de10_lite.sdc
+set_global_assignment -name VHDL_FILE de10_lite.vhd
+set_global_assignment -name SOURCE_FILE output_files/Spf1.spf
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/peripherals/encoder/sint/de10_lite.sdc b/peripherals/encoder/sint/de10_lite.sdc
new file mode 100644
index 00000000..7267c16e
--- /dev/null
+++ b/peripherals/encoder/sint/de10_lite.sdc
@@ -0,0 +1,86 @@
+#**************************************************************
+# This .sdc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period "10.0 MHz" [get_ports ADC_CLK_10]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+
diff --git a/peripherals/encoder/sint/de10_lite.vhd b/peripherals/encoder/sint/de10_lite.vhd
new file mode 100644
index 00000000..48aaa320
--- /dev/null
+++ b/peripherals/encoder/sint/de10_lite.vhd
@@ -0,0 +1,125 @@
+-------------------------------------------------------------------
+-- Name        : de0_lite.vhd
+-- Author      : 
+-- Version     : 0.1
+-- Copyright   : Departamento de Eletrônica, Florianópolis, IFSC
+-- Description : Projeto base DE10-Lite
+-------------------------------------------------------------------
+LIBRARY ieee;
+USE IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+-- Utilização das funções de my_package
+use work.logica7.all;
+
+entity de10_lite is 
+	port (
+		---------- CLOCK ----------
+		ADC_CLK_10:	in std_logic;
+		MAX10_CLK1_50: in std_logic;
+		MAX10_CLK2_50: in std_logic;
+		
+		----------- SDRAM ------------
+		DRAM_ADDR: out std_logic_vector (12 downto 0);
+		DRAM_BA: out std_logic_vector (1 downto 0);
+		DRAM_CAS_N: out std_logic;
+		DRAM_CKE: out std_logic;
+		DRAM_CLK: out std_logic;
+		DRAM_CS_N: out std_logic;		
+		DRAM_DQ: inout std_logic_vector(15 downto 0);
+		DRAM_LDQM: out std_logic;
+		DRAM_RAS_N: out std_logic;
+		DRAM_UDQM: out std_logic;
+		DRAM_WE_N: out std_logic;
+		
+		----------- SEG7 ------------
+		HEX0: out std_logic_vector(7 downto 0);
+		HEX1: out std_logic_vector(7 downto 0);
+		HEX2: out std_logic_vector(7 downto 0);
+		HEX3: out std_logic_vector(7 downto 0);
+		HEX4: out std_logic_vector(7 downto 0);
+		HEX5: out std_logic_vector(7 downto 0);
+
+		----------- KEY ------------
+		KEY: in std_logic_vector(1 downto 0);
+
+		----------- LED ------------
+		LEDR: out std_logic_vector(9 downto 0);
+
+		----------- SW ------------
+		SW: in std_logic_vector(9 downto 0);
+
+		----------- VGA ------------
+		VGA_B: out std_logic_vector(3 downto 0);
+		VGA_G: out std_logic_vector(3 downto 0);
+		VGA_HS: out std_logic;
+		VGA_R: out std_logic_vector(3 downto 0);
+		VGA_VS: out std_logic;
+	
+		----------- Accelerometer ------------
+		GSENSOR_CS_N: out std_logic;
+		GSENSOR_INT: in std_logic_vector(2 downto 1);
+		GSENSOR_SCLK: out std_logic;
+		GSENSOR_SDI: inout std_logic;
+		GSENSOR_SDO: inout std_logic;
+	
+		----------- Arduino ------------
+		ARDUINO_IO: inout std_logic_vector(15 downto 0);
+		ARDUINO_RESET_N: inout std_logic
+	);
+end entity;
+
+
+architecture rtl of de10_lite is
+
+
+	signal frequencia: unsigned(31 downto 0);
+
+
+begin
+	
+
+	   
+	   encoder:entity work.encoder
+	       port map(
+	           clk           => MAX10_CLK1_50,
+	           aclr_n        => SW(0),
+	           select_time   => SW(4 downto 2),
+	           encoder_pulse => SW(1),
+	           frequency     => frequencia
+	       );
+	   
+	       display0:entity work.seven_segment_cntrl
+            port map(
+                input => frequencia(3 downto 0),
+                segs  => HEX0
+            );
+            
+            display1:entity work.seven_segment_cntrl
+            port map(
+                input => frequencia(7 downto 4),
+                segs  => HEX1
+            );
+	    
+           display2:entity work.seven_segment_cntrl
+            port map(
+                input => frequencia(11 downto 8),
+                segs  => HEX2
+            );
+           display3:entity work.seven_segment_cntrl
+            port map(
+                input => frequencia(15 downto 12),
+                segs  => HEX3
+            );
+            
+            display4:entity work.seven_segment_cntrl
+            port map(
+                input => frequencia(19 downto 16),
+                segs  => HEX4
+            );
+           display5:entity work.seven_segment_cntrl
+            port map(
+                input => frequencia(23 downto 20),
+                segs  => HEX5
+            );
+end;
+
diff --git a/peripherals/encoder/testbench_encoder.vhd b/peripherals/encoder/testbench_encoder.vhd
new file mode 100644
index 00000000..610451ee
--- /dev/null
+++ b/peripherals/encoder/testbench_encoder.vhd
@@ -0,0 +1,61 @@
+-------------------------------------------------------------------
+-- name        : testbench_counter.vhd
+-- author      : Stanislau de Lira Kaszubowski
+-- data        : 02/04/2024
+-- copyright   : Instituto Federal de Santa Catarina
+-- description : Realiza o testbench de counter.vhd
+------------------------------------------------------------------- 
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity testbench_encoder is
+
+end entity testbench_encoder;
+
+architecture RTL of testbench_encoder is
+    signal  clk_tb: std_logic;
+    signal  encoder_pulse_tb: std_logic;
+    signal  aclr_n_tb: std_logic;
+    signal  frequency_tb: unsigned (31 downto 0);
+    signal  select_time_tb: std_logic_vector (2 downto 0)
+;
+    
+begin
+    
+encoder_inst : entity work.encoder
+    port map(
+        clk           => clk_tb,
+        aclr_n        => aclr_n_tb,
+        select_time   => select_time_tb,
+        encoder_pulse => encoder_pulse_tb,
+        frequency     => frequency_tb
+    );
+
+
+        clock_driver : process
+        constant period : time := 20 ns;  --50mhz
+    begin
+        clk_tb <= '0';
+        wait for period / 2;
+        clk_tb <= '1';
+        wait for period / 2;
+    end process clock_driver;
+    
+        encoder_driver : process
+        constant period : time := 40 ns;  --25mhz
+    begin
+        encoder_pulse_tb <= '0';
+        wait for period / 2;
+        encoder_pulse_tb <= '1';
+        wait for period / 2;
+    end process encoder_driver;
+    
+    
+
+    select_time_tb<= "000"; --1ms
+    aclr_n_tb<= '1', '0'after 35 ns, '1' after 100 ns, '0'after 400000 ns, '1'after 500000 ns;
+
+    
+end architecture RTL;
\ No newline at end of file