diff --git a/peripherals/morse/MorseCodeBuzzer.vhd b/peripherals/morse/MorseCodeBuzzer.vhd new file mode 100644 index 00000000..07fa9269 --- /dev/null +++ b/peripherals/morse/MorseCodeBuzzer.vhd @@ -0,0 +1,170 @@ +--! Use standard library +library ieee; + +use ieee.std_logic_1164.all; + +use ieee.numeric_std.all; +use work.MorseCode_Package.all; + + +entity MorseCodeBuzzer is + Port ( + clk : in std_logic; -- Clock input + rst : in std_logic; -- Reset input + entrada: in integer; --entrada do numero/letra/caracter especial + buzzer : out std_logic; -- Buzzer output + ledt : out std_logic;-- led acionado com o tempo T (ponto) + ledf : out std_logic;-- led acionado com o fim da palavra + led3t: out std_logic-- led acionado com o tempo 3T (traço) + ); + +end MorseCodeBuzzer; + +architecture Behavioral of MorseCodeBuzzer is + constant T: integer :=225;--225 para a placa; para os testbench 10 muda a frequencia de operação + constant Tbase: integer :=5555;--5555 para a placa; para os testbench 1 muda a frequencia do tom + signal count_T,count_3T,count_7T, count_within_char, count_between_letters : integer:=0; -- contadores de cada tempo + signal count_T_TC, count_3T_TC,count_7T_TC, count_within_char_TC, count_between_letters_TC: std_logic:='0';-- sinal de contagem completa + signal counter : integer := 0;-- contador da palavra + signal temp: bit:='1';--qual o bit atual + signal count_pulse: integer range 0 to Tbase-1 := 0; -- Contador para a geração da freq do buzzer + signal tone: std_logic := '0'; -- Sinal de saida do buzzer modulado pela frequencia + signal morse_code : bit_vector (4 downto 0);-- vetor que é recebido pelo arquivo package (onde entra o número inteiro e sai o vetor de bits) + type MorseStates is (IDLE, TIME_T, TIME_3T, TIME_7T,NEXT_CARACTER, TIME_WITHIN_LETTER, TIME_BETWEEN_LETTERS);-- maquina de estados + signal STATE : MorseStates := IDLE;-- estado inicial + +begin + process (clk, rst) + begin + + if rst = '1' then -- não esquecer de resetar tudo + STATE <= IDLE; + counter <= 0; + temp<='0'; + morse_code<="00000"; + buzzer <= '1'; + ledt<='0'; + ledf<='0'; + led3t<='0'; + elsif rising_edge(clk) then -- no limiar de subida do clock + + if count_pulse <= 0 then + -- Se o contador atingir 0, inverta o sinal do buzzer para gerar a frequencia + tone <= not tone; + count_pulse <= Tbase - 1; -- Reinicia o contador + else + count_pulse <= count_pulse - 1; -- Decrementa o contador + end if; + ledt<='0'; + case STATE is + when IDLE => + if entrada >= 0 and entrada <= 9 then --limitar o numero entre 0 a 9 + morse_code <= Morse_codes(entrada);-- entra com a entrada na tabela e recebe o vetor de bit + temp<= morse_code(counter);-- seleciona o bit em relação ao contador (faz a varredura) + ledf<='0';-- desliga o led de quando acaba a palavra + if temp = '0' then -- caso seja ponto + count_T <=T; -- o valor de count passa a ser a constante definida anteriormente + STATE<= TIME_T;-- vai para o estado de T + elsif temp = '1' then --caso seja traco + count_3T <=3*T; -- o valor de count passa a ser a 3*constante definida anteriormente + STATE<= TIME_3T;-- vai para o estado de 3T + else + -- STATE<= IDLE; + null; + end if; + end if; + when TIME_T =>-- ponto + buzzer<=tone;-- saida recebe o tom + ledt<='1'; -- led do T acende + count_within_char_TC<='0'; + if count_T=0 then + count_T_TC<='1'; -- flag de fim da contagem de T + else + count_T<=count_T-1; + end if; + + if count_T_TC = '1' then-- caso tenha terminado T + count_within_char<=3*T; -- define o contador do intervalo entre bit + STATE<= TIME_WITHIN_LETTER; -- vai para o intervalo entre bit + end if; + + when TIME_3T =>-- traco + buzzer<=tone; + led3t<='1'; + count_within_char_TC<='0'; + if count_3T=0 then + count_3T_TC<='1'; + else + count_3T<=count_3T-1; + end if; + if count_3T_TC='1' then + count_within_char<=3*T; + STATE<=TIME_WITHIN_LETTER; + end if; + + when TIME_7T => -- intervalo entre palavra + buzzer<=tone; + if count_7T=0 then + count_7T_TC<='1'; + else + count_7T<=count_7T-1; + end if; + + if count_7T_TC='1' then + + STATE<=IDLE; + end if; + when NEXT_CARACTER =>-- proxima bit + counter<= counter+1; -- aumenta o contador da bit + temp<=morse_code(counter);-- seleciona o prox bit da bit + if counter = 4 then-- como foi feito apenas com numeros e o seu numero max é 5 (lembra do 0) + morse_code <= Morse_codes(entrada); + temp<= morse_code(counter); + counter<= 0; + count_between_letters<=3*T; + STATE<= TIME_BETWEEN_LETTERS;-- intervalo entre palavras/numeros/fim do caracter atual + ledf<='1'; + else + -- recomeça o processo com o proximo bit + if temp = '0' then -- caso seja ponto + count_T <=T; + STATE<= TIME_T; + elsif temp = '1' then --caso seja traco + count_3T <=3*T; + STATE<= TIME_3T; + end if; + end if; + + when TIME_WITHIN_LETTER =>-- "silencio" entre os bits + count_T_TC<='0'; -- reseta a flag do T + count_3T_TC<='0'; -- reseta a flag do 3T + buzzer<='1'; -- silencia a saida + ledt<='0'; + led3t<='0'; + if count_within_char=0 then + count_within_char_TC<='1'; + else + count_within_char<=count_within_char-1; + end if; + + if count_within_char_TC = '1' then + STATE<= NEXT_CARACTER;-- vai para o proximo bit + end if; + + when TIME_BETWEEN_LETTERS =>-- intervalo entre palavras/numeros/fim do caracter atual + buzzer<='1'; + if count_between_letters=0 then + count_between_letters_TC<='1'; + else + count_between_letters<=count_between_letters-1; + end if; + if count_between_letters_TC='1' then + STATE<=IDLE; + end if; + + end case; + end if; + end process; +end Behavioral; + + diff --git a/peripherals/morse/MorseCode_Package.vhd b/peripherals/morse/MorseCode_Package.vhd new file mode 100644 index 00000000..1ec9c6d2 --- /dev/null +++ b/peripherals/morse/MorseCode_Package.vhd @@ -0,0 +1,42 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package MorseCode_Package is + type MorseCodeTable is array(integer range 0 to 9) of bit_vector(0 to 4); + + function Morse_codes(Morse_value : integer) return bit_vector; + + constant MorseCodes : MorseCodeTable := ( + -- Para uma futura implementação: + -- acrescentar as letra e caracteres especiais + -- utilizar de "." e "-" no lugar de "0" e "1" + -- 'A' => ".-", 'B' => "-...", 'C' => "-.-.", + -- 'D' => "-..", 'E' => ".", 'F' => "..-.", + -- 'G' => "--.", 'H' => "....", 'I' => "..", + -- 'J' => ".---", 'K' => "-.-", 'L' => ".-..", + -- 'M' => "--", 'N' => "-.", 'O' => "---", + -- 'P' => ".--.", 'Q' => "--.-", 'R' => ".-.", + -- 'S' => "...", 'T' => "-", 'U' => "..-", + -- 'V' => "...-", 'W' => ".--", 'X' => "-..-", + -- 'Y' => "-.--", 'Z' => "--..", + -- 0 => "-----", 1 => ".----", 2 => "..---", + -- 3 => "...--", 4 => " ....-", 5 => ".....", + -- 6 => "-....", 7 => "--...", 8 => "---..", + -- 9 => "----." + -- ponto e 0 e traço e 1 + 0 => "11111", 1 => "01111", 2 => "00111", + 3 => "00011", 4 => "00001", 5 => "00000", + 6 => "10000", 7 => "11000", 8 => "11100", + 9 => "11110" + ); + +end package MorseCode_Package; + +package body MorseCode_Package is + function Morse_Codes(Morse_value : integer) return bit_vector is + begin + return MorseCodes(Morse_value); + end function Morse_Codes; + +end package body MorseCode_Package; diff --git a/peripherals/morse/README.md b/peripherals/morse/README.md new file mode 100644 index 00000000..b5a47eb2 --- /dev/null +++ b/peripherals/morse/README.md @@ -0,0 +1,22 @@ +# MorseCode Numbers + +Esta implementação contempla o uso de um módulo buzzer (figura abaixo) como periférico. Que recebe um sinal de entrada e converte para um sinal sonoro itermitente que é representado por pontos e traços. Atualmente está implementado os números do código morse. + + +![# modulo buzzer ](./imagens/modulo%20buzzer.png) + + + +O ponto tem o periodo de T e o traço 3T emitindo som, intervalo entre caracter tem 3T e entre palavras 7T. O período T pode variar de acordo com a experiência do operador de código morse. A seguir a tabela de código morse implementada: + +![numeros morse](./imagens/Morse_code_numbers.png) + +Este periférico possui 3 pinos, VCC de 3V3, GND e o pino de controle, no qual envia um sinal que emite som quando '0' e fica sem som quando '1' + +Utilizou-se uma tabela para converter a entrada em pontos e traços (pontos são represnetados por '0' traços representados por '1') e uma maquina de estados para realizar os diferentes periodos de operação. A maquina de estados a seguir resume a operação deste programa + + +![maquina de estados ](./imagens/Maquina_de_estados.png) + +# Simulação +A primeira simulação foi feita ainda antes do periférico ser implementado no projeto como um todo e pode ser visto nos arquivos [testbench](/peripherals/morse/testbench.vhd) e [tb.do](/peripherals/morse/tb.do) diff --git a/peripherals/morse/imagens/Maquina_de_estados.png b/peripherals/morse/imagens/Maquina_de_estados.png new file mode 100644 index 00000000..3ecf4e9e Binary files /dev/null and b/peripherals/morse/imagens/Maquina_de_estados.png differ diff --git a/peripherals/morse/imagens/Morse_code_numbers.png b/peripherals/morse/imagens/Morse_code_numbers.png new file mode 100644 index 00000000..442387bb Binary files /dev/null and b/peripherals/morse/imagens/Morse_code_numbers.png differ diff --git a/peripherals/morse/imagens/modulo buzzer.png b/peripherals/morse/imagens/modulo buzzer.png new file mode 100644 index 00000000..bd36015a Binary files /dev/null and b/peripherals/morse/imagens/modulo buzzer.png differ diff --git a/peripherals/morse/sint/PLL_Morse.cmp b/peripherals/morse/sint/PLL_Morse.cmp new file mode 100644 index 00000000..5551a298 --- /dev/null +++ b/peripherals/morse/sint/PLL_Morse.cmp @@ -0,0 +1,23 @@ +--Copyright (C) 2022 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details, at +--https://fpgasoftware.intel.com/eula. + + +component PLL_Morse + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC + ); +end component; diff --git a/peripherals/morse/sint/PLL_Morse.ppf b/peripherals/morse/sint/PLL_Morse.ppf new file mode 100644 index 00000000..d83a3df1 --- /dev/null +++ b/peripherals/morse/sint/PLL_Morse.ppf @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/peripherals/morse/sint/PLL_Morse.qip b/peripherals/morse/sint/PLL_Morse.qip new file mode 100644 index 00000000..7c294b06 --- /dev/null +++ b/peripherals/morse/sint/PLL_Morse.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "21.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "PLL_Morse.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_Morse.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_Morse.ppf"] diff --git a/peripherals/morse/sint/PLL_Morse.vhd b/peripherals/morse/sint/PLL_Morse.vhd new file mode 100644 index 00000000..497cc05b --- /dev/null +++ b/peripherals/morse/sint/PLL_Morse.vhd @@ -0,0 +1,355 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: PLL_Morse.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 21.1.1 Build 850 06/23/2022 SJ Standard Edition +-- ************************************************************ + + +--Copyright (C) 2022 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and any partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details, at +--https://fpgasoftware.intel.com/eula. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY PLL_Morse IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC + ); +END PLL_Morse; + + +ARCHITECTURE SYN OF pll_morse IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire4_bv(0 DOWNTO 0) <= "0"; + sub_wire4 <= To_stdlogicvector(sub_wire4_bv); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + sub_wire2 <= inclk0; + sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 4000, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 100000, + intended_device_family => "MAX 10", + lpm_hint => "CBX_MODULE_PREFIX=PLL_Morse", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire3, + clk => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "4000" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "0.002500" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "10.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL_Morse.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "4000" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "100000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_Morse.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_Morse.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_Morse.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_Morse.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_Morse.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_Morse_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/peripherals/morse/sint/de10_lite.qpf b/peripherals/morse/sint/de10_lite.qpf new file mode 100644 index 00000000..c44f1c80 --- /dev/null +++ b/peripherals/morse/sint/de10_lite.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# Date created = 09:41:06 April 06, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "09:41:06 April 06, 2020" + +# Revisions + +PROJECT_REVISION = "de10_lite" diff --git a/peripherals/morse/sint/de10_lite.qsf b/peripherals/morse/sint/de10_lite.qsf new file mode 100644 index 00000000..e04c4b93 --- /dev/null +++ b/peripherals/morse/sint/de10_lite.qsf @@ -0,0 +1,362 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# Date created = 09:41:06 April 06, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# de10_lite_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite_Morse +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:41:06 APRIL 06, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N +set_global_assignment -name QSYS_FILE unnamed.qsys +set_global_assignment -name VHDL_FILE ../MorseCodeBuzzer.vhd +set_global_assignment -name VHDL_FILE ../MorseCode_Package.vhd +set_global_assignment -name SDC_FILE de10_lite.sdc +set_global_assignment -name VHDL_FILE de10_lite.vhd +set_global_assignment -name QIP_FILE PLL.qip +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ADC_CLK_10 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK1_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MAX10_CLK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_LDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_UDQM +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[7] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LEDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_INT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDI +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GSENSOR_SDO +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[15] +set_instance_assignment -name IO_STANDARD "3.3 V SCHMITT TRIGGER" -to ARDUINO_RESET_N +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name QIP_FILE PLL_Morse.qip \ No newline at end of file diff --git a/peripherals/morse/sint/de10_lite.sdc b/peripherals/morse/sint/de10_lite.sdc new file mode 100644 index 00000000..7267c16e --- /dev/null +++ b/peripherals/morse/sint/de10_lite.sdc @@ -0,0 +1,86 @@ +#************************************************************** +# This .sdc file is created by Terasic Tool. +# Users are recommended to modify this file to match users logic. +#************************************************************** + +#************************************************************** +# Create Clock +#************************************************************** +create_clock -period "10.0 MHz" [get_ports ADC_CLK_10] +create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50] +create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50] + +#************************************************************** +# Create Generated Clock +#************************************************************** +derive_pll_clocks + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** +derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + + + +#************************************************************** +# Set Load +#************************************************************** + + + diff --git a/peripherals/morse/sint/de10_lite.vhd b/peripherals/morse/sint/de10_lite.vhd new file mode 100644 index 00000000..097c6148 --- /dev/null +++ b/peripherals/morse/sint/de10_lite.vhd @@ -0,0 +1,104 @@ +------------------------------------------------------------------- +-- Name : de0_lite.vhd +-- Author : +-- Version : 0.1 +-- Copyright : Departamento de Eletrônica, Florianópolis, IFSC +-- Description : Projeto base DE10-Lite +------------------------------------------------------------------- +LIBRARY ieee; +USE IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +entity de10_lite_Morse is + port ( + ---------- CLOCK ---------- + ADC_CLK_10: in std_logic; + MAX10_CLK1_50: in std_logic; + MAX10_CLK2_50: in std_logic; + + ----------- SDRAM ------------ + DRAM_ADDR: out std_logic_vector (12 downto 0); + DRAM_BA: out std_logic_vector (1 downto 0); + DRAM_CAS_N: out std_logic; + DRAM_CKE: out std_logic; + DRAM_CLK: out std_logic; + DRAM_CS_N: out std_logic; + DRAM_DQ: inout std_logic_vector(15 downto 0); + DRAM_LDQM: out std_logic; + DRAM_RAS_N: out std_logic; + DRAM_UDQM: out std_logic; + DRAM_WE_N: out std_logic; + + ----------- SEG7 ------------ + HEX0: out std_logic_vector(7 downto 0); + HEX1: out std_logic_vector(7 downto 0); + HEX2: out std_logic_vector(7 downto 0); + HEX3: out std_logic_vector(7 downto 0); + HEX4: out std_logic_vector(7 downto 0); + HEX5: out std_logic_vector(7 downto 0); + + ----------- KEY ------------ + KEY: in std_logic_vector(1 downto 0); + + ----------- LED ------------ + LEDR: out std_logic_vector(9 downto 0); + + ----------- SW ------------ + SW: in std_logic_vector(9 downto 0); + + ----------- VGA ------------ + VGA_B: out std_logic_vector(3 downto 0); + VGA_G: out std_logic_vector(3 downto 0); + VGA_HS: out std_logic; + VGA_R: out std_logic_vector(3 downto 0); + VGA_VS: out std_logic; + + ----------- Accelerometer ------------ + GSENSOR_CS_N: out std_logic; + GSENSOR_INT: in std_logic_vector(2 downto 1); + GSENSOR_SCLK: out std_logic; + GSENSOR_SDI: inout std_logic; + GSENSOR_SDO: inout std_logic; + + ----------- Arduino ------------ + ARDUINO_IO: inout std_logic_vector(15 downto 0); + ARDUINO_RESET_N: inout std_logic + ); +end entity; + + +architecture rtl of de10_lite_Morse is + + signal clk : std_logic; + signal rst : std_logic; + signal entrada : integer; + signal buzzer : std_logic; + signal chaves: unsigned(4 downto 0); + +begin + final:entity work.MorseCodeBuzzer + port map( + clk => clk, + rst => rst, + entrada => entrada, + ledt=>LEDR(2), -- led do tempo T + ledf=>LEDR(8), -- led de fim do número + led3t=>LEDR(4),-- led do tempo 3T + buzzer => ARDUINO_IO(1)-- pino do meio do modulo do buzzer + ); + + entrada<=to_integer(chaves);-- converte as chaves para inteiro, para ir para a entrada + rst<=SW(9);-- reset + chaves(0)<=SW(0);-- chaves de entrada dos números + chaves(1)<=SW(1); + chaves(2)<=SW(2); + chaves(3)<=SW(3); + chaves(4)<=SW(4); + + PLL_inst : entity work.PLL_Morse --clock de 10M e dividido por 4000 (2.5khz) + port map( + inclk0 => ADC_CLK_10, + c0 => clk + ); +end; + diff --git a/peripherals/morse/sint/de10_lite_assignment_defaults.qdf b/peripherals/morse/sint/de10_lite_assignment_defaults.qdf new file mode 100644 index 00000000..bcfd7884 --- /dev/null +++ b/peripherals/morse/sint/de10_lite_assignment_defaults.qdf @@ -0,0 +1,806 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2023 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition +# Date created = 17:57:45 December 07, 2023 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL Enable +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST On -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/peripherals/morse/tb.do b/peripherals/morse/tb.do new file mode 100644 index 00000000..caad4d00 --- /dev/null +++ b/peripherals/morse/tb.do @@ -0,0 +1,47 @@ +#------------------------------------------------------ +#-- testbench do Somador de n-bits +#-- atualmente configurado para 16bits +#-- Matheus Sandim Gon�alves +#-- Departamento de Eletr�nica, Florian�polis, IFSC +#------------------------------------------------------- + +#Cria biblioteca do projeto +vlib work + +#compila projeto: todos os aquivo. Ordem é importante +vcom MorseCode_Package.vhd MorseCodeBuzzer.vhd testbench.vhd + +#Simula (work é o diretorio, testbench é o nome da entity) +vsim -voptargs="+acc" -t ns work.testbench + +#Mosta forma de onda +view wave + +#Adiciona ondas específicas +# -radix: binary, hex, dec +# -label: nome da forma de onda +# Sem labels +add wave -radix uns /clk_tb +add wave -radix uns /rst_tb +add wave -radix uns /entrada_tb +add wave -radix uns /buzzer_tb +add wave -radix uns /ledt_tb +add wave -radix uns /led3t_tb +add wave -radix uns /ledf_tb +add wave -label estado -radix binary /final/STATE + + +#SINAIS INTERMEDIARIOS CASO NECESSITE +#add wave -label cod -radix binary /final/morse_code +#add wave -label TC -radix binary /final/count_T_TC +#add wave -label T -radix dec /final/count_T +#add wave -label morse_code -radix uns /final/morse_code +#add wave -label temp -radix dec /final/temp +#add wave -label counter -radix dec /final/counter +#add wave -label tone -radix dec /final/tone + +#Simula até um 50000ns +run 50000ns + +wave zoomfull +write wave wave.ps diff --git a/peripherals/morse/testbench.vhd b/peripherals/morse/testbench.vhd new file mode 100644 index 00000000..b093d6b5 --- /dev/null +++ b/peripherals/morse/testbench.vhd @@ -0,0 +1,67 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity testbench is +end entity testbench; + +architecture RTL of testbench is -- sinais do testbench + signal clk_tb: std_logic; + signal rst_tb: std_logic; + signal entrada_tb:integer; + signal buzzer_tb: std_logic; + signal ledt_tb : std_logic; + signal led3t_tb : std_logic; + signal ledf_tb : std_logic; +begin + final: entity work.MorseCodeBuzzer -- relaciona os sinais do testbench com as entradas e saídas do arq. principal + port map( + clk => clk_tb, + rst => rst_tb, + entrada => entrada_tb, + ledt => ledt_tb, + led3t => led3t_tb, + ledf => ledf_tb, + buzzer => buzzer_tb + ); + process + begin-- faz o processo do clock 1 nseg em cada nivel logico + clk_tb <= '0'; + wait for 1 ns; + clk_tb <= '1'; + wait for 1 ns; + end process; + + process + begin + rst_tb<= '1';-- reset + wait for 1 ns; + rst_tb<= '0'; + wait for 20000 ns; + end process; + + process + begin + entrada_tb<= 4; --entra valor de 4 + wait for 500 ns; + entrada_tb<= 1; --entra valor de 1 + wait for 500 ns; + entrada_tb<= 2; --entra valor de 2 + wait for 500 ns; + entrada_tb<= 3; --entra valor de 3 + wait for 500 ns; + entrada_tb<= 4; --entra valor de 4 + wait for 500 ns; + entrada_tb<= 5; --entra valor de 5 + wait for 500 ns; + entrada_tb<= 6; --entra valor de 6 + wait for 500 ns; + entrada_tb<= 7; --entra valor de 7 + wait for 500 ns; + entrada_tb<= 8; --entra valor de 8 + wait for 500 ns; + entrada_tb<= 9; --entra valor de 9 + wait for 500 ns; + + end process; +end architecture RTL;