diff --git a/CONTRIBUTORS.md b/CONTRIBUTORS.md new file mode 100644 index 00000000..7048d416 --- /dev/null +++ b/CONTRIBUTORS.md @@ -0,0 +1,23 @@ +RISVC contributors (sorted alphabetically) +============================================ + +* **[Cleisson Fernandes Da Silva](https://github.com/cleissom)** + + * SDRAM integration (first attempt) + +* **[Ian Schmiegelow Dannapel](https://github.com/Eximmius)** + + * VGA integration (internal SRAM) + +* **[Jeferson Cansi Pedroso](https://github.com/jefersonpedroso)** + + * MAX10 ADC integration + +* **[Lucas Seara Manoel](https://github.com/lsmanoel)** + + * [M] Instructions extension. + +* **[Marcos Vinicius Leal Da Silva](https://github.com/marcosleal)** + + * 9600 baud rate UART. + diff --git a/LICENSE b/LICENSE new file mode 100644 index 00000000..f288702d --- /dev/null +++ b/LICENSE @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/README.md b/README.md new file mode 100644 index 00000000..f85a2eff --- /dev/null +++ b/README.md @@ -0,0 +1,82 @@ +# RISC SoftCore +--- + +RISC SoftCore é uma implementação em VHDL com fins diádicos do conjunto de instruções RISCV RV32I. Essa versão particular não implementa um pipeline. A ideia é criar um microcontrolador com periféricos comuns como I2C, USART, SPI e GPIOs inicialmente utilizado para disciplina de Dispositivos Lógicos Programáveis. + +Ferramentas de programação podem ser obtidas no [RISC-V Website](https://riscv.org/software-status/). + +## Getting Started (hardware): + +- Simulação: + - ModelSim: execução do script testbench.do + - testbench: ./core/testbench.vhd + - Utilizar uma memória SRAM IP (32-bits x 1024 words): + - Quartus RAM: catálogo de IPS, RAM 1-port + - Na aba de confguração __Regs/Clken/Byte Enable/AClrs__, desabilite __'q' output port__ e habilite __Create byte enable for port A__ + - Na aba de configuração __Mem Init__, habilite e configure o arquivo de inicialização da memória de instruções para __quartus.hex__ + - Na aba de configuração __Mem Init__, habilite Allow In-System Memory Content Editor. + - Se necessário, altere o caminho do arquivo de inicialização de memória (__quartus.hex__) no arquivo iram_quartus.vhdl + +- Síntese: Quartus 15 ou superior (testado no Kit de desenvolvimento DE10-Lite) + - Projeto: utilize ./sint/de10_lite + - Para gravação do programa pós síntese: + - Utilizar uma memória SRAM IP (32-bits x 1024 words Quartus RAM + - Gravação pelo Tools -> In-System Memory Editor + - Utilize uma PLL para ajuste do clock + +## Getting Started (software): + +A compilação de programas necessita do _toolchain_ __riscv32-unknown-elf__ suportando o subconjunto RV32I. Em ./tests/ há um exemplo bem simples de Makefile. Perceba que na fase atual do projeto utilizamos um _script_ de _linker_ customizado (sections.ld). libc ainda não foi testado/suportado. + +### Instalação do compilador no Linux + +Guia para instalação no [gnu-mcu-eclipse.github.io](https://gnu-mcu-eclipse.github.io/toolchain/riscv/install/#gnulinux) + +Toolchain Release: riscv-none-gcc [Github](https://github.com/gnu-mcu-eclipse/riscv-none-gcc/releases). + +1. Atualizar Makefile com o diretório da toolchain. + +Exemplo: + +```RISCV_TOOLS_PREFIX = /home/lucas/ssd2/vhdl/softcore/gnu-mcu-riscv/gnu-mcu-eclipse/riscv-none-gcc/8.2.0-2.2-20190521-0004/bin/riscv32-unknown-elf-``` + +2. Para compilar, _make_. + +### Instalação do compilador no Windows (Windows Subsystem for Linux) + +1. Instalar o WSL: [Microsoft Docs](https://docs.microsoft.com/en-us/windows/wsl/install-win10) +2. Instalar o Ubuntu no WSL + + - Para integrar o Visual Code com o compilador interno ao WSL, siga esse [link](https://devblogs.microsoft.com/commandline/an-in-depth-tutorial-on-linux-development-on-windows-with-wsl-and-visual-studio-code/) + +3. No shell Ubuntu (busque Ubuntu no Iniciar do Windows): +4. Instalar os pacotes para o nodejs: + +```sudo apt update +sudo apt upgrade +sudo apt install nodejs +sudo apt install npm +sudo npm --global install xpm +``` + +5. Instalar por xmp [GNU Eclipse](https://gnu-mcu-eclipse.github.io/toolchain/riscv/install/): + +```xpm install --global @gnu-mcu-eclipse/riscv-none-gcc``` + +6. Altere o caminho do compilador no _Makefile_: + - de: +```RISCV_TOOLS_PREFIX = riscv32-unknown-elf-``` + - para: +```RISCV_TOOLS_PREFIX = ~/opt/xPacks/@/.contents/bin/riscv-none-embed-``` + +7. Utilizando o shell Ubuntu, mude o diretório atual para o repositório: + +```cd /mnt/c/``` + +8. Para compilar, _make_. + +Após a compilação, mova, copie ou faça um _link_ simbólico de ./tests/quartus.hex para a raiz do projeto. + +## Simulador Assembly: + +RISV baseado no MARS: [RARS](https://github.com/TheThirdOne/rars) diff --git a/alu/alu.vhd b/alu/alu.vhd new file mode 100644 index 00000000..f6151315 --- /dev/null +++ b/alu/alu.vhd @@ -0,0 +1,53 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.alu_types.all; + +entity ULA is + port( + alu_data : in alu_data_t; + dataOut : out signed(31 downto 0) + ); +end entity ULA; + +architecture RTL of ULA is + signal shamt : std_logic_vector(4 downto 0); + signal comp_l : std_logic_vector(31 downto 0); + signal comp_lu : std_logic_vector(31 downto 0); + + signal or_vector : std_logic_vector(31 downto 0); + signal xor_vector : std_logic_vector(31 downto 0); + signal and_vector : std_logic_vector(31 downto 0); + +begin + -- shamt <= std_logic_vector(to_signed(alu_data.b,5)); -- to_unsigned + shamt <= std_logic_vector(alu_data.b(4 downto 0)); -- to_unsigned + + comp_l <= x"00000001" when alu_data.a < alu_data.b else (others => '0'); + --comp_lu <= "1" when (to_unsigned(alu_data.a,32)) < (to_unsigned(alu_data.a,32)) else + -- "0"; + comp_lu <= x"00000001" when (unsigned(alu_data.a) < unsigned(alu_data.a)) else (others => '0'); + + --or_vector <= std_logic_vector(to_signed(alu_data.a,32)) or std_logic_vector(to_signed(alu_data.b,32)); + or_vector <= std_logic_vector(alu_data.a or alu_data.b); + -- xor_vector <= std_logic_vector(to_signed(alu_data.a,32)) xor std_logic_vector(to_signed(alu_data.b,32)); + xor_vector <= std_logic_vector(alu_data.a xor alu_data.b); + -- and_vector <= std_logic_vector(to_signed(alu_data.a,32)) and std_logic_vector(to_signed(alu_data.b,32)); + and_vector <= std_logic_vector(alu_data.a and alu_data.b); + + + ula_op : with alu_data.code select + dataOut <= alu_data.a + alu_data.b when ALU_ADD, + alu_data.a - alu_data.b when ALU_SUB, + alu_data.a sll to_integer(unsigned(shamt)) when ALU_SLL, + signed(comp_l) when ALU_SLT, + signed(comp_lu) when ALU_SLTU, + signed(xor_vector) when ALU_XOR, + alu_data.a srl to_integer(unsigned(shamt)) when ALU_SRL, + alu_data.a srl to_integer(unsigned(shamt)) when ALU_SRA, + signed(or_vector) when ALU_OR, + signed(and_vector) when ALU_AND, + (others => '0') when others; + +end architecture RTL; diff --git a/alu/alu_types.vhd b/alu/alu_types.vhd new file mode 100644 index 00000000..ebb5767e --- /dev/null +++ b/alu/alu_types.vhd @@ -0,0 +1,58 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package alu_types is + + --! Record for instruction decoding + type alu_data_t is record + a : signed(31 downto 0); --! Source operand A + b : signed(31 downto 0); --! Source operand B + code : std_logic_vector(3 downto 0); --! Alu operation code + end record alu_data_t; + + constant ALU_ADD : std_logic_vector(3 downto 0) := "0000"; + constant ALU_SUB : std_logic_vector(3 downto 0) := "0001"; + + constant ALU_SLL : std_logic_vector(3 downto 0) := "0010"; + constant ALU_SRL : std_logic_vector(3 downto 0) := "0011"; + constant ALU_SRA : std_logic_vector(3 downto 0) := "0100"; + + constant ALU_SLT : std_logic_vector(3 downto 0) := "0101"; + constant ALU_SLTU : std_logic_vector(3 downto 0) := "0111"; + + constant ALU_XOR : std_logic_vector(3 downto 0) := "1000"; + constant ALU_OR : std_logic_vector(3 downto 0) := "1001"; + constant ALU_AND : std_logic_vector(3 downto 0) := "1010"; + + constant MUL_ULA : std_logic_vector(2 downto 0) := "001"; + constant AND_ULA : std_logic_vector(2 downto 0) := "010"; + constant OR_ULA : std_logic_vector(2 downto 0) := "011"; + constant XOR_ULA : std_logic_vector(2 downto 0) := "100"; + constant NOT_ULA : std_logic_vector(2 downto 0) := "101"; + constant SLL_ULA : std_logic_vector(2 downto 0) := "110"; + constant SRL_ULA : std_logic_vector(2 downto 0) := "111"; + + constant MUX_ULA_R : std_logic_vector(1 downto 0) := "00"; + constant MUX_ULA_I : std_logic_vector(1 downto 0) := "01"; + constant MUX_ULA_Shift : std_logic_vector(1 downto 0) := "10"; + constant MUX_ULA_BRANCH : std_logic_vector(1 downto 0) := "11"; + + constant MUX_BR_ULA : std_logic := '0'; + constant MUX_BR_RAM : std_logic := '1'; + + constant MUX_COMP_0 : std_logic := '0'; + constant MUX_COMP_EQUAL : std_logic := '1'; + + constant PC_DT_PSEUDO : std_logic := '0'; + constant PC_DT_BRANCH : std_logic := '1'; + + constant LED_IO_REG : std_logic_vector(7 downto 0) := "10000000"; + constant SW_IO_REG : std_logic_vector(7 downto 0) := "10000001"; + constant SEG7_IO_REG: std_logic_vector(7 downto 0) := "10000010"; + +end package alu_types; + +package body alu_types is + +end package body alu_types; diff --git a/alu/m/M.vhd b/alu/m/M.vhd new file mode 100644 index 00000000..d973d519 --- /dev/null +++ b/alu/m/M.vhd @@ -0,0 +1,54 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.M_types.all; + +entity M is + port( + M_data : in M_data_t; + dataOut : out std_logic_vector(31 downto 0) + ); +end entity; + +architecture RTL of M is + ------------------------------------------------------------------- + + + signal mul_signed: Signed(63 downto 0); + signal mulu_unsigned: Unsigned(63 downto 0); + + signal div_signed: Signed(31 downto 0); + signal divu_unsigned: Unsigned(31 downto 0); + + signal rem_signed: Signed(31 downto 0); + signal remu_unsigned: Unsigned(31 downto 0); + +begin + --===============================================================-- + + mul_signed <= M_data.a*M_data.b; + mulu_unsigned <= Unsigned(M_data.a)*Unsigned(M_data.b); + + div_signed <= M_data.a/M_data.b; + divu_unsigned <= Unsigned(M_data.a)/Unsigned(M_data.b); + + rem_signed <= M_data.a mod M_data.b; + remu_unsigned <= Unsigned(M_data.a) mod Unsigned(M_data.b); + + ula_op : with M_data.code select + dataOut <= Std_logic_vector(mul_signed(31 downto 0)) when M_MUL, + Std_logic_vector(mul_signed(63 downto 32)) when M_MULH, + + Std_logic_vector(mulu_unsigned(63 downto 32)) when M_MULHU, + Std_logic_vector(mulu_unsigned(63 downto 32)) when M_MULHSU, + + Std_logic_vector(div_signed) when M_DIV, + Std_logic_vector(divu_unsigned) when M_DIVU, + + Std_logic_vector(rem_signed) when M_REM, + Std_logic_vector(remu_unsigned) when M_REMU, + + (others => '0') when others; + +end architecture; \ No newline at end of file diff --git a/alu/m/M_types.vhd b/alu/m/M_types.vhd new file mode 100644 index 00000000..59afabd7 --- /dev/null +++ b/alu/m/M_types.vhd @@ -0,0 +1,27 @@ +LIBRARY ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package M_types is + + --! Record for instruction decoding + type M_data_t is record + a : signed(31 downto 0); --! Source operand A + b : signed(31 downto 0); --! Source operand B + code : std_logic_vector(2 downto 0); --! Alu operation code + end record M_data_t; + + constant M_MUL: std_logic_vector(2 downto 0) := "000"; + constant M_MULH: std_logic_vector(2 downto 0) := "001"; + constant M_MULHU: std_logic_vector(2 downto 0) := "010"; + constant M_MULHSU: std_logic_vector(2 downto 0) := "011"; + constant M_DIV: std_logic_vector(2 downto 0) := "100"; + constant M_DIVU: std_logic_vector(2 downto 0) := "101"; + constant M_REM: std_logic_vector(2 downto 0) := "110"; + constant M_REMU: std_logic_vector(2 downto 0) := "111"; + +end package; + +package body M_types is + +end; diff --git a/alu/m/README.md b/alu/m/README.md new file mode 100644 index 00000000..57d35442 --- /dev/null +++ b/alu/m/README.md @@ -0,0 +1,74 @@ +# [“M” Standard Extension for Integer Multiplication and Division, Version 2.0](https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf#chapter.6) + +[RV32/64G Instruction Set Listings](https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf#chapter.19) + +![M word](./img/M_word.png) + +![RV32M Standard Extension](./img/rv32M_standard_extension.png) + +* MUL - **Signed\*Signed** 32 bits multiplication (rs1*rs2) - Place lower 32 bits in rd. +* MULH - **Signed\*Signed** 32 bits multiplication (rs1*rs2) - Place higher 32 bits in rd. +* MULHU - **Unsigned\*Unsigned** 32 bits multiplication (rs1*rs2) - Place higher 32 bits in rd. +* MULHSU - **Signed\*Unsigned** 32 bits multiplication (rs1*rs2) - Place higher 32 bits in rd. +* DIV - **Signed\*Signed** 32 bits division (rs1*rs2) - Place lower 32 bits in rd. +* DIVU - **Unsigned\*Unsigned** 32 bits division (rs1*rs2) - Place lower 32 bits in rd. +* REM - **Signed** remainder of the corresponding division operation +* REMU - **Unsigned** remainder of the corresponding division operation + +![RV32M Standard Extension](./img/M_unit.png) + +##Files to use M unit: + +* M_types.vhd +* M.vhd + +##Testbench: + +* tb_M.do - Modelsim +* tb_M.vhd + +##Code to Teste: +```C +#include "utils.h" +#include "hardware.h" +#include + +int main(){ + volatile int a_int32=3, b_int32=2; + volatile int a_int64=3, b_int64=2; + + volatile uint32_t a_uint32=INT_MAX, b_uint32=2; + volatile uint64_t a_uint64=INT_MAX, b_uint64=2; + + volatile uint64_t mul_result; + volatile uint32_t mulh_result; + volatile uint32_t mulhsu_result; + volatile uint32_t mulhu_result; + volatile int div_result; + volatile uint32_t divu_result; + volatile int rem_result; + volatile uint32_t remu_result; + + while (1){ + + + mul_result = a_uint32 * b_int32; + + mulh_result = a_int64*b_int64; + + mulhsu_result = a_uint64*b_uint64; + + mulh_result = a_int64*b_int64; + + div_result = a_int32/b_int32; + + divu_result = a_uint32/b_uint32; + + div_result = a_int32%b_int32; + + divu_result = a_uint32%b_uint32; + } + + return 0; +} +``` diff --git a/alu/m/img/M_unit.png b/alu/m/img/M_unit.png new file mode 100644 index 00000000..07244300 Binary files /dev/null and b/alu/m/img/M_unit.png differ diff --git a/alu/m/img/M_word.png b/alu/m/img/M_word.png new file mode 100644 index 00000000..c4d66987 Binary files /dev/null and b/alu/m/img/M_word.png differ diff --git a/alu/m/img/mul_machine_state.png b/alu/m/img/mul_machine_state.png new file mode 100644 index 00000000..f9b131a8 Binary files /dev/null and b/alu/m/img/mul_machine_state.png differ diff --git a/alu/m/img/rv32M_standard_extension.png b/alu/m/img/rv32M_standard_extension.png new file mode 100644 index 00000000..cff49cf5 Binary files /dev/null and b/alu/m/img/rv32M_standard_extension.png differ diff --git a/alu/m/tb_M.do b/alu/m/tb_M.do new file mode 100644 index 00000000..a04bee09 --- /dev/null +++ b/alu/m/tb_M.do @@ -0,0 +1,29 @@ +#Cria Biblioteca +vlib work + +#Compila Projeto +vcom M_types.vhd +vcom M.vhd +vcom tb_M.vhd + +#Simula +vsim -t ns work.tb_M + +#Mosta forma de onda +view wave + +#Adiciona ondas específicas +#radix: binary, hex, dec +#label: nome da forma de onda + +#------------------------------------------------------------------------------------------ +add wave -radix dec -label a_integer /a_integer +add wave -radix dec -label b_integer /b_integer +add wave -radix dec -label M_data_out_integer /M_data_out_integer +add wave -radix bin -label code_logic_vector /code_logic_vector + +#------------------------------------------------------------------------------------------ +run 100ns + +wave zoomfull +write wave wave.pss \ No newline at end of file diff --git a/alu/m/tb_M.vhd b/alu/m/tb_M.vhd new file mode 100644 index 00000000..fe27ef7a --- /dev/null +++ b/alu/m/tb_M.vhd @@ -0,0 +1,106 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.M_types.all; + +entity tb_M is +end entity; + +architecture waveform of tb_M is + ------------------------------------------------------------------- + -- CLOCK + signal clock_50_0_logic, clock_50_PI_logic: std_logic; + + ------------------------------------------------------------------- + -- M + component M is + port( + M_DATA : in M_data_t; + DATAOUT : out std_logic_vector(31 downto 0) + ); + end component; + + -------------------------------------------------------------------- + -- A and B + signal a_integer: integer; + signal a_signed: signed (31 downto 0); + signal a_logic_vector: std_logic_vector (31 downto 0); + + signal b_integer: integer; + signal b_signed: signed (31 downto 0); + signal b_logic_vector: std_logic_vector (31 downto 0); + + -------------------------------------------------------------------- + -- code + signal code_logic_vector: std_logic_vector (2 downto 0); + + -------------------------------------------------------------------- + -- M_data + signal M_data_record: M_data_t; + + -------------------------------------------------------------------- + -- DATAOUT + signal M_data_out_integer: integer; + signal M_data_out_signed: signed(31 downto 0); + signal M_data_out_logic_vector: std_logic_vector(31 downto 0); + +begin + --===============================================================-- + -- M + M_vhd: M + port map( + M_DATA => M_data_record, + DATAOUT => M_data_out_logic_vector + ); + + --===============================================================-- + -- A and B + a_signed <= To_signed(a_integer, 32); + a_logic_vector <= Std_logic_vector(a_signed); + + b_signed <= To_signed(b_integer, 32); + b_logic_vector <= Std_logic_vector(b_signed); + + a_integer <= 7; + b_integer <= 3; + + --===============================================================-- + -- code + SET_CODE: process -- 50 MHz phase pi + begin + code_logic_vector <= "000"; + wait for 10 ns; + code_logic_vector <= "001"; + wait for 10 ns; + code_logic_vector <= "010"; + wait for 10 ns; + code_logic_vector <= "011"; + wait for 10 ns; + code_logic_vector <= "100"; + wait for 10 ns; + code_logic_vector <= "101"; + wait for 10 ns; + code_logic_vector <= "110"; + wait for 10 ns; + code_logic_vector <= "111"; + wait for 10 ns; + end process; + + + --===============================================================-- + -- M_data + M_data_record.a <= a_signed; + M_data_record.b <= b_signed; + M_data_record.code <= code_logic_vector; + + --===============================================================-- + -- DATAOUT + M_data_out_signed <= Signed(M_data_out_logic_vector); + M_data_out_integer <= To_integer(M_data_out_signed); + + --&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&-- + -- Code + M_data_record.code <= code_logic_vector; + +end architecture; \ No newline at end of file diff --git a/core/core.vhd b/core/core.vhd new file mode 100644 index 00000000..a2a0fa2a --- /dev/null +++ b/core/core.vhd @@ -0,0 +1,315 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.decoder_types.all; +use work.alu_types.all; +use work.M_types.all; + +entity core is + generic ( + --! Num of 32-bits memory words + IMEMORY_WORDS : integer := 1024; + DMEMORY_WORDS : integer := 512 + ); + port( + clk : in std_logic; + rst : in std_logic; + + iaddress : out integer range 0 to IMEMORY_WORDS-1; + idata : in std_logic_vector(31 downto 0); + + daddress : out natural; + + ddata_r : in std_logic_vector(31 downto 0); + ddata_w : out std_logic_vector(31 downto 0); + d_we : out std_logic; + d_rd : out std_logic; + d_sig : out std_logic; --! Signal extension + dcsel : out std_logic_vector(1 downto 0); --! Chip select + dmask : out std_logic_vector(3 downto 0); --! Byte enable mask + + state : out cpu_state_t + ); +end entity core; + +architecture RTL of core is + + signal pc : std_logic_vector(31 downto 0); + signal next_pc : std_logic_vector(31 downto 0); + signal opcodes : opcodes_t; + + signal rd : integer range 0 to 31; + signal rs1 : integer range 0 to 31; + signal rs2 : integer range 0 to 31; + signal imm_i : integer; + signal imm_s : integer; + signal imm_b : integer; + signal imm_u : integer; + signal imm_j : integer; + + signal rf_w_ena : std_logic; + signal rw_data : std_logic_vector(31 downto 0); + signal rs1_data : std_logic_vector(31 downto 0); + signal rs2_data : std_logic_vector(31 downto 0); + + --! Signals for alu control + signal alu_data : alu_data_t; + signal alu_out : signed(31 downto 0); + + --! Signals for M control + signal M_data : M_data_t; + signal M_out : std_logic_vector(31 downto 0); + + --! Control flow signals signals + signal jumps : jumps_ctrl_t; + + + signal ulaMuxData : std_logic_vector(1 downto 0); + signal writeBackMux : std_logic_vector(2 downto 0); + + signal dmemory : mem_ctrl_t; + + signal jal_target : integer; --!= Target address for jump instruction + signal jalr_target : integer; --!= Target address for jalr instruction + signal auipc_offtet : integer; --!= PC plus offset for aiupc instruction + + signal branch_cmp : std_logic; + signal bus_lag : std_logic; + +begin + + pc_blk: block + begin + + next_pc <= std_logic_vector(to_unsigned(to_integer(signed(pc)) + 4,32)); + + pc_proc: process (clk, rst) + begin + if rst = '1' then + pc <= (others => '0'); + else + if rising_edge(clk) then + if jumps.inc = '1' then + pc <= next_pc; + elsif jumps.load = '1' then + case jumps.load_from is + when "00" => + pc <= std_logic_vector(to_unsigned(jal_target,32)); + + when "01" => + if branch_cmp = '1' then + pc <= std_logic_vector(to_unsigned(to_integer(signed(pc)) + imm_b,32)); + else + pc <= next_pc; + end if; + + when "11" => + pc <= std_logic_vector(to_unsigned(jalr_target,32)); + + when others => + report "Not implemented" severity Failure; + end case; + + end if; + end if; + end if; + end process; + + jal_target <= to_integer(signed(pc)) + imm_j; + auipc_offtet <= to_integer(signed(pc)) + imm_u; + jalr_target <= to_integer(signed(rs1_data)) + imm_i; + + iaddress <= to_integer(unsigned(pc(16 downto 2))); + end block; + + + branch_unit: block + begin + cmp_prc: process(opcodes, rs1_data, rs2_data) + begin + branch_cmp <= '0'; + + case opcodes.funct3 is + when TYPE_BEQ => + if rs1_data = rs2_data then + branch_cmp <= '1'; + end if; + when TYPE_BNE => + if rs1_data /= rs2_data then + branch_cmp <= '1'; + end if; + when TYPE_BLT => + if (to_integer(signed(rs1_data)) < (to_integer(signed(rs2_data)))) then + branch_cmp <= '1'; + end if; + when TYPE_BGE => + if (to_integer(signed(rs1_data)) >= (to_integer(signed(rs2_data)))) then + branch_cmp <= '1'; + end if; + when TYPE_BLTU => + if (to_integer(unsigned(rs1_data)) < (to_integer(unsigned(rs2_data)))) then + branch_cmp <= '1'; + end if; + + when TYPE_BGEU => + if (to_integer(unsigned(rs1_data)) >= (to_integer(unsigned(rs2_data)))) then + branch_cmp <= '1'; + end if; + + when others => + end case; + end process; + end block; + + + ins_register: entity work.iregister + port map( + clk => clk, + rst => rst, + data => idata, + opcodes => opcodes, + rd => rd, + rs1 => rs1, + rs2 => rs2, + imm_i => imm_i, + imm_s => imm_s, + imm_b => imm_b, + imm_u => imm_u, + imm_j => imm_j + ); + + + registers: entity work.register_file + port map( + clk => clk, + rst => rst, + w_ena => rf_w_ena, + w_address => rd, + w_data => rw_data, + r1_address => rs1, + r1_data => rs1_data, + r2_address => rs2, + r2_data => rs2_data + ); + + writeBackMuxBlock: block + begin + with writeBackMux select + rw_data <= std_logic_vector(alu_out) when "000", + std_logic_vector(to_signed(imm_u,32)) when "001", + std_logic_vector(to_signed(auipc_offtet,32)) when "010", + next_pc when "011", + ddata_r when "100", + M_out when "101", + std_logic_vector(to_signed(imm_i,32)) when others; + + end block; + + decoder0: entity work.decoder + port map( + clk => clk, + rst => rst, + dmemory => dmemory, + opcodes => opcodes, + bus_lag => bus_lag, + jumps => jumps, + ulaMuxData => ulaMuxData, + ulaCod => alu_data.code, + M_Cod => M_data.code, + writeBackMux => writeBackMux, + reg_write => rf_w_ena, + cpu_state => state + ); + + + alu_0: entity work.ULA + port map( + alu_data => alu_data, + dataOut => alu_out + ); + + alu_data.a <= (signed(rs1_data)); + + aluMuxBlock: block + begin + with ulaMuxData select + alu_data.b <= (signed(rs2_data)) when "00", + to_signed(imm_i,32) when "01", + to_signed(imm_b,32) when others; + end block; + + M_0: entity work.M + port map( + M_data => M_data, + dataOut => M_out + ); + + M_data.a <= (signed(rs1_data)); + M_data.b <= (signed(rs2_data)); + + memAddrTypeSBlock: block + signal addr : std_logic_vector(31 downto 0); + signal byteSel: std_logic_vector(1 downto 0); + begin + -- != Load and Store instructions have different address generation + with dmemory.read select + addr <= std_logic_vector(to_signed(to_integer(signed(rs1_data)) + imm_i,32)) when '1', -- to_unsigned + std_logic_vector(to_signed(to_integer(signed(rs1_data)) + imm_s,32)) when others; -- to_unsigned + + byteSel <= addr(1 downto 0); + daddress <= to_integer(unsigned(addr(31 downto 2))); + + ddata_w <= rs2_data; --! Data to write + d_we <= dmemory.write; --! Write signal + d_rd <= dmemory.read; --! Read signal + d_sig <= dmemory.signal_ext; --! for byte and halfword loads + + bus_lag <= not addr(25); --! Stall another cycle when reading from imem + + -- Address space (check sections.ld) and chip select: + -- 0x0000000000 -> 0b000 0000 0000 0000 0000 0000 0000 + -- 0x0002000000 -> 0b010 0000 0000 0000 0000 0000 0000 + -- 0x0004000000 -> 0b100 0000 0000 0000 0000 0000 0000 + -- 0x0006000000 -> 0b110 0000 0000 0000 0000 0000 0000 + dcsel <= addr(26 downto 25); + + --! Byte sel mask generation + dmaskGen: process(dmemory, byteSel) + begin + dmask <= "0000"; + + case dmemory.word_size is + when "00" => + dmask <= "1111"; + when "01" => + case byteSel is + when "00" => + dmask <= "0011"; + when "10" => + dmask <= "1100"; + when others => + end case; + when "11" => + case byteSel is + when "00" => + dmask <= "0001"; + when "01" => + dmask <= "0010"; + when "10" => + dmask <= "0100"; + when "11" => + dmask <= "1000"; + when others => + end case; + + when others => + if dmemory.write = '1' then + report "Not implemented" severity Failure; + end if; + end case; + end process; + end block; + +end architecture RTL; + diff --git a/core/testbench.vhd b/core/testbench.vhd new file mode 100644 index 00000000..4179e446 --- /dev/null +++ b/core/testbench.vhd @@ -0,0 +1,271 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.decoder_types.all; + +entity coretestbench is + generic( + --! Num of 32-bits memory words + IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes + DMEMORY_WORDS : integer := 1024; --!= 2k (512 * 2) bytes + constant SIZE : integer := 8 -- 8 bytes UART package + ); + + port( + ----------- SEG7 ------------ + HEX0 : out std_logic_vector(7 downto 0); + HEX1 : out std_logic_vector(7 downto 0); + HEX2 : out std_logic_vector(7 downto 0); + HEX3 : out std_logic_vector(7 downto 0); + HEX4 : out std_logic_vector(7 downto 0); + HEX5 : out std_logic_vector(7 downto 0); + ----------- SW ------------ + + SW: in std_logic_vector(9 downto 0); + LEDR: out std_logic_vector(9 downto 0); + + ---------- ARDUINO IO ----- + ARDUINO_IO: inout std_logic_vector(15 downto 0) + ); + + +end entity coretestbench; + +architecture RTL of coretestbench is + signal clk : std_logic; + signal clk_sdram : std_logic; + signal clk_vga : std_logic; + signal rst : std_logic; + signal rst_n : std_logic; + + signal idata : std_logic_vector(31 downto 0); + + signal daddress : natural; + signal ddata_r : std_logic_vector(31 downto 0); + signal ddata_w : std_logic_vector(31 downto 0); + signal dmask : std_logic_vector(3 downto 0); + signal dcsel : std_logic_vector(1 downto 0); + signal d_we : std_logic := '0'; + + signal iaddress : integer range 0 to IMEMORY_WORDS - 1 := 0; + + signal address : std_logic_vector(31 downto 0); + + signal ddata_r_mem : std_logic_vector(31 downto 0); + signal d_rd : std_logic; + + signal input_in : std_logic_vector(31 downto 0); + signal cpu_state : cpu_state_t; + + signal debugString : string(1 to 40) := (others => '0'); + + + -- UART Signals + signal clk_baud : std_logic; + signal data_in : std_logic_vector(7 downto 0); + signal tx : std_logic; + signal start : std_logic; + signal tx_cmp : std_logic; + signal data_out : std_logic_vector(SIZE-1 downto 0); + signal rx : std_logic; + signal rx_cmp : std_logic; + + signal csel_uart : std_logic; + + signal dmemory_address : natural; + signal d_sig : std_logic; + + +begin + + clock_driver : process + constant period : time := 1000 ns; + begin + clk <= '0'; + wait for period / 2; + clk <= '1'; + wait for period / 2; + end process clock_driver; + + reset : process is + begin + rst <= '1'; + wait for 5 ns; + rst <= '0'; + wait; + end process reset; + + + -- Dummy out signals + -- ARDUINO_IO <= ddata_r(31 downto 16); + +-- imem: component imemory +-- generic map( +-- MEMORY_WORDS => IMEMORY_WORDS +-- ) +-- port map( +-- clk => clk, +-- data => idata, +-- write_address => 0, +-- read_address => iaddress, +-- we => '0', +-- q => idata +-- ); + + + rst_n <= not rst; + + -- imem: component imemory + -- generic map( + -- MEMORY_WORDS => IMEMORY_WORDS + -- ) + -- port map( + -- clk => clk, + -- data => idata, + -- write_address => 0, + -- read_address => iaddress, + -- we => '0', + -- q => idata + -- ); + + -- IMem shoud be read from instruction and data buses + -- Not enough RAM ports for instruction bus, data bus and in-circuit programming + -- with dcsel select + -- address <= std_logic_vector(to_unsigned(daddress,10)) when "01", + -- std_logic_vector(to_unsigned(iaddress,10)) when others; + process(d_rd, dcsel, daddress, iaddress) + begin + if (d_rd = '1') and (dcsel = "00") then + address <= std_logic_vector(to_unsigned(daddress, 32)); + else + address <= std_logic_vector(to_unsigned(iaddress, 32)); + end if; + end process; + + -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor + iram_quartus_inst : entity work.iram_quartus + port map( + address => address(9 downto 0), + byteena => "1111", + clock => clk, + data => (others => '0'), + wren => '0', + q => idata + ); + + dmemory_address <= to_integer(to_unsigned(daddress, 10)); + -- Data Memory RAM + dmem : entity work.dmemory + generic map( + MEMORY_WORDS => DMEMORY_WORDS + ) + port map( + rst => rst, + clk => clk, + data => ddata_w, + address => dmemory_address, + we => d_we, + signal_ext => d_sig, + csel => dcsel(0), + dmask => dmask, + q => ddata_r_mem + ); + + -- Adress space mux ((check sections.ld) -> Data chip select: + -- 0x00000 -> Instruction memory + -- 0x20000 -> Data memory + -- 0x40000 -> Input/Output generic address space + -- 0x60000 -> SDRAM address space + with dcsel select ddata_r <= + idata when "00", + ddata_r_mem when "01", + input_in when "10", + (others => '0') when others; + + -- Softcore instatiation + myRiscv : entity work.core + generic map( + IMEMORY_WORDS => IMEMORY_WORDS, + DMEMORY_WORDS => DMEMORY_WORDS + ) + port map( + clk => clk, + rst => rst, + iaddress => iaddress, + idata => idata, + daddress => daddress, + ddata_r => ddata_r, + ddata_w => ddata_w, + d_we => d_we, + d_rd => d_rd, + d_sig => d_sig, + dcsel => dcsel, + dmask => dmask, + state => cpu_state + ); + + -- Output register (Dummy LED blinky) + process(clk, rst) + begin + if rst = '1' then + LEDR(7 downto 0) <= (others => '0'); + HEX0 <= (others => '1'); + HEX1 <= (others => '1'); + HEX2 <= (others => '1'); + HEX3 <= (others => '1'); + HEX4 <= (others => '1'); + HEX5 <= (others => '1'); + else + if rising_edge(clk) then + if (d_we = '1') and (dcsel = "10") then + -- ToDo: Simplify compartors + -- ToDo: Maybe use byte addressing? + -- x"01" (word addressing) is x"04" (byte addressing) + if to_unsigned(daddress, 32)(8 downto 0) = x"01" then + LEDR(7 downto 0) <= ddata_w(7 downto 0); + elsif to_unsigned(daddress, 32)(8 downto 0) = x"02" then + HEX0 <= ddata_w(7 downto 0); + HEX1 <= ddata_w(15 downto 8); + HEX2 <= ddata_w(23 downto 16); + HEX3 <= ddata_w(31 downto 24); + -- HEX4 <= ddata_w(7 downto 0); + -- HEX5 <= ddata_w(7 downto 0); + end if; + end if; + end if; + end if; + end process; + + -- Input register + process(clk, rst) + begin + if rst = '1' then + input_in <= (others => '0'); + else + + if rising_edge(clk) then + if (d_rd = '1') and (dcsel = "10") then + if to_unsigned(daddress, 32)(8 downto 0) = x"00" then + input_in(4 downto 0) <= SW(4 downto 0); + elsif to_unsigned(daddress, 32)(8 downto 0) = x"04" then + input_in(7 downto 0) <= data_out; + end if; + end if; + end if; + end if; + + end process; + + -- FileOutput DEBUG + debug : entity work.trace_debug + generic map( + MEMORY_WORDS => IMEMORY_WORDS + ) + port map( + pc => iaddress, + data => idata, + inst => debugString + ); + +end architecture RTL; diff --git a/core/trace_debug.vhd b/core/trace_debug.vhd new file mode 100644 index 00000000..10fa7e9a --- /dev/null +++ b/core/trace_debug.vhd @@ -0,0 +1,443 @@ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use std.textio.all; + +use work.decoder_types.all; +use work.txt_util.all; + + +entity trace_debug is + generic ( + --! Num of 32-bits memory words + MEMORY_WORDS : integer := 1024 --!= 4K (1024 * 4) bytes + ); + port( + pc : in integer range 0 to MEMORY_WORDS - 1; + data : in std_logic_vector(31 downto 0); + inst : out string(1 to 40) + ); +end entity trace_debug; + +architecture RTL of trace_debug is + + function typeIstring (data: std_logic_vector; opcode: string; pc, rd, rs1, immediate: integer) return string is + begin + return str(pc*4 ,16) & ": " & hstr(data) & " : " & opcode & " x" & str(rd) & ", x" & str(rs1) & ", " & str(immediate); + end function; + + function typeUstring (data: std_logic_vector; opcode: string; pc, rd, immediate: integer) return string is + begin + return str(pc*4 ,16) & ": " & hstr(data) & " : " & opcode & " x" & str(rd) & ", 0x" & str(immediate, 16); + end function; + + function typeRstring (data: std_logic_vector; opcode: string; pc, rd, rs1, rs2: integer) return string is + begin + return str(pc*4,16) & ": " & hstr(data) & " : " & opcode & " x" & str(rd) & ", x" & str(rs1) & ", x" & str(rs2); + end function; + + function typeSstring (data: std_logic_vector; opcode: string; pc, rs1, rs2, immediate: integer) return string is + begin + return str(pc*4,16) & ": " & hstr(data) & " : " & opcode & " x" & str(rs2) & ", " & str(immediate) & "(x" & str(rs1) & ")"; + end function; + + function typeJstring (data: std_logic_vector; opcode: string; pc, rd, immediate: integer) return string is + begin + return str(pc*4,16) & ": " & hstr(data) & " : " & opcode & " x" & str(rd) & ", " & str(immediate); + end function; + + function typeJRstring (data: std_logic_vector; opcode: string; pc, rd, rs1, immediate: integer) return string is + begin + return str(pc*4,16) & ": " & hstr(data) & " : " & opcode & " " & "x" & str(rd) & ", " & str(immediate) & "(x" & str(rs1) & ")"; + end function; + + function typeLstring (data: std_logic_vector; opcode: string; pc, rd, rs1, immediate: integer) return string is + begin + return str(pc*4 ,16) & ": " & hstr(data) & " : " & opcode & " x" & str(rd) & "," & str(immediate) & "(" & str(rs1) & ")"; + end function; + + function typeBRstring (data: std_logic_vector; opcode: string; pc, rs1, rs2, immediate: integer) return string is + begin + return str(pc*4 ,16) & ": " & hstr(data) & " : " & opcode & " x" & str(rs1) & ", x" & str(rs2) & ", " & str(immediate); + end function; + + function str_pad(s : string; pad_char : character; len : integer) return string is + variable ret : string(1 to len); + variable j : integer := 0; + variable rm : integer; + begin + assert len >= s'length report "Specified length must be longer than the specified string" severity failure; + + -- Find last ':' character + for i in 1 to s'high loop + if s(i) = ':' then + rm := i; + end if; + end loop; + + -- remove extra espaces + rm := rm + 2; + j := rm; + + for i in 1 to s'high-rm + 1 loop + ret(i) := s(j); + j := j + 1; + end loop; + + for i in s'high-rm + 2 to len loop + ret(i) := pad_char; + end loop; + + return ret; + end function str_pad; + + +begin + + debug: process(data) + + variable opcodes : opcodes_t; --! Instruction decoding information. See decoder_types.vhd + + variable rd : integer range 0 to 31; --! Register address destination + variable rs1 : integer range 0 to 31; --! Register address source operand 1 + variable rs2 : integer range 0 to 31; --! Register address source operand 2 + + variable imm_i : integer; --! Immediate for I-type instruction + variable imm_s : integer; --! Immediate for S-type instruction + variable imm_b : integer; --! Immediate for B-type instruction + variable imm_u : integer; --! Immediate for U-type instruction + variable imm_j : integer; --! Immediate for J-type instruction + + + -- variable disassembly : string(32 downto 1); + variable my_line : line; + + file my_output : TEXT open WRITE_MODE is "sim.s"; + alias swrite is write [line, string, side, width]; + begin + + opcodes.opcode := data (6 downto 0); + opcodes.funct3 := data(14 downto 12); + opcodes.funct7 := data(31 downto 25); + + rd := to_integer(unsigned(data(11 downto 7))); + rs1 := to_integer(unsigned(data(19 downto 15))); + rs2 := to_integer(unsigned(data(24 downto 20))); + + imm_i := to_integer(signed(data(31 downto 20))); + imm_s := to_integer(signed(data(31 downto 25) & data(11 downto 7))); + imm_b := to_integer(signed(data(31) & data(7) & data(30 downto 25) & data(11 downto 8) & '0')); + imm_u := to_integer(signed(data(31 downto 12) & "000000000000")); + imm_j := to_integer(signed(data(31) & data(19 downto 12) & data(20) & data(30 downto 21) & '0')); + + inst <= (others => ' '); + + case opcodes.opcode is + + when TYPE_I => + + case opcodes.funct3 is + when TYPE_ADDI => + swrite(my_line, typeIstring(data, "addi", pc, rd, rs1, imm_i)); + writeline(my_output, my_line); + inst <= str_pad(typeIstring(data, "addi", pc, rd, rs1, imm_i), ' ', 40); + + when TYPE_SLTI => + swrite(my_line, typeIstring(data, "slti", pc, rd, rs1, imm_i)); + writeline(my_output, my_line); + inst <= str_pad(typeIstring(data, "slti", pc, rd, rs1, imm_i), ' ', 40); + + when TYPE_SLTIU => + swrite(my_line, typeIstring(data, "sltiu", pc, rd, rs1, imm_i)); + writeline(my_output, my_line); + inst <= str_pad(typeIstring(data, "sltiu", pc, rd, rs1, imm_i), ' ', 40); + + when TYPE_XORI => + swrite(my_line, typeIstring(data, "xoir", pc, rd, rs1, imm_i)); + writeline(my_output, my_line); + inst <= str_pad(typeIstring(data, "xoir", pc, rd, rs1, imm_i), ' ', 40); + + when TYPE_ORI => + swrite(my_line, typeIstring(data, "oir", pc, rd, rs1, imm_i)); + writeline(my_output, my_line); + inst <= str_pad(typeIstring(data, "oir", pc, rd, rs1, imm_i), ' ', 40); + + when TYPE_ANDI => + swrite(my_line, typeIstring(data, "andi", pc, rd, rs1, imm_i)); + writeline(my_output, my_line); + inst <= str_pad(typeIstring(data, "andi", pc, rd, rs1, imm_i), ' ', 40); + + when TYPE_SLLI => + swrite(my_line, typeIstring(data, "slli", pc, rd, rs1, imm_i)); + writeline(my_output, my_line); + inst <= str_pad(typeIstring(data, "slli", pc, rd, rs1, imm_i), ' ', 40); + + when TYPE_SR => + case opcodes.funct7 is + when TYPE_SRLI => + -- Shift ammount is rs2 + swrite(my_line, typeIstring(data, "srli", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeIstring(data, "srli", pc, rd, rs1, rs2), ' ', 40); + + when TYPE_SRAI => + -- Shift ammount is rs2 + swrite(my_line, typeIstring(data, "srai", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeIstring(data, "srai", pc, rd, rs1, rs2), ' ', 40); + + when others => + end case; + + + when others => + + end case; + + when TYPE_AUIPC => + swrite(my_line, typeUstring(data, "auipc", pc, rd, imm_u)); + writeline(my_output, my_line); + inst <= str_pad(typeUstring(data, "auipc", pc, rd, imm_u), ' ', 40); + + when TYPE_LUI => + swrite(my_line, typeUstring(data, "lui", pc, rd, imm_u)); + writeline(my_output, my_line); + inst <= str_pad(typeUstring(data, "lui", pc, rd, imm_u), ' ', 40); + + when TYPE_R => + if opcodes.funct7 = TYPE_MULDIV then + case opcodes.funct3 is + --------------------------------------------------------------------------- + when TYPE_MUL => + swrite(my_line, typeRstring(data, "mul", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "mul", pc, rd, rs1, rs2), ' ', 40); + when TYPE_MULH => + swrite(my_line, typeRstring(data, "mulh", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "mulh", pc, rd, rs1, rs2), ' ', 40); + when TYPE_MULHU => + swrite(my_line, typeRstring(data, "mulhu", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "mulhu", pc, rd, rs1, rs2), ' ', 40); + when TYPE_MULHSU => + swrite(my_line, typeRstring(data, "mulhsu", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "mulhsu", pc, rd, rs1, rs2), ' ', 40); + when TYPE_DIV => + swrite(my_line, typeRstring(data, "div", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "div", pc, rd, rs1, rs2), ' ', 40); + when TYPE_DIVU => + swrite(my_line, typeRstring(data, "divu", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "divu", pc, rd, rs1, rs2), ' ', 40); + when TYPE_REM => + swrite(my_line, typeRstring(data, "rem", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "rem", pc, rd, rs1, rs2), ' ', 40); + when TYPE_REMU => + swrite(my_line, typeRstring(data, "remu", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "remu", pc, rd, rs1, rs2), ' ', 40); + when others => + report "Not implemented" severity Failure; + end case; + else + case opcodes.funct3 is + when TYPE_ADD_SUB => + if opcodes.funct7 = TYPE_ADD then + swrite(my_line, typeRstring(data, "add", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "add", pc, rd, rs1, rs2), ' ', 40); + else + swrite(my_line, typeRstring(data, "sub", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "sub", pc, rd, rs1, rs2), ' ', 40); + end if; + + when TYPE_AND => + swrite(my_line, typeRstring(data, "and", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "and", pc, rd, rs1, rs2), ' ', 40); + when TYPE_OR => + swrite(my_line, typeRstring(data,"or", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "or", pc, rd, rs1, rs2), ' ', 40); + when TYPE_SLL => + swrite(my_line, typeRstring(data, "sll", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "sll", pc, rd, rs1, rs2), ' ', 40); + ------------------------------------------------------------------------------------ + --when TYPE_SLR => + -- swrite(my_line, typeRstring(data, "slr", pc, rd, rs1, rs2)); + -- writeline(my_output, my_line); + -- inst <= str_pad(typeRstring(data, "slr", pc, rd, rs1, rs2), ' ', 40); + when TYPE_SR => + + case opcodes.funct7 is + when TYPE_SRLI => + -- Shift ammount is rs2 + swrite(my_line, typeIstring(data, "srl", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeIstring(data, "srl", pc, rd, rs1, rs2), ' ', 40); + + when TYPE_SRAI => + -- Shift ammount is rs2 + swrite(my_line, typeIstring(data, "sra", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeIstring(data, "sra", pc, rd, rs1, rs2), ' ', 40); + + when others => + report "nao entrei aqui"; + end case; + ------------------------------------------------------------------------------------ + when TYPE_XOR => + swrite(my_line, typeRstring(data, "xor", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "xor", pc, rd, rs1, rs2), ' ', 40); + when others => + report "Not implemented" severity Failure; + end case; + end if; + + case opcodes.funct3 is + when TYPE_ADD_SUB => + if opcodes.funct7 = TYPE_ADD then + swrite(my_line, typeRstring(data, "add", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "add", pc, rd, rs1, rs2), ' ', 40); + else + swrite(my_line, typeRstring(data, "sub", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "sub", pc, rd, rs1, rs2), ' ', 40); + end if; + + when TYPE_AND => + swrite(my_line, typeRstring(data, "and", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "and", pc, rd, rs1, rs2), ' ', 40); + when TYPE_SLL => + swrite(my_line, typeRstring(data, "sll", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "sll", pc, rd, rs1, rs2), ' ', 40); + when TYPE_XOR => + swrite(my_line, typeRstring(data, "xor", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "xor", pc, rd, rs1, rs2), ' ', 40); + when TYPE_OR => + swrite(my_line, typeRstring(data, "or", pc, rd, rs1, rs2)); + writeline(my_output, my_line); + inst <= str_pad(typeRstring(data, "or", pc, rd, rs1, rs2), ' ', 40); + + when others => + report "Not implemented" severity Failure; + end case; + + when TYPE_S => + case opcodes.funct3 is + when TYPE_SB => + swrite(my_line, typeSstring(data, "sb", pc, rs1, rs2, imm_s)); + writeline(my_output, my_line); + inst <= str_pad(typeSstring(data, "sb", pc, rs1, rs2, imm_s), ' ', 40); + when TYPE_SH => + swrite(my_line, typeSstring(data, "sh", pc, rs1, rs2, imm_s)); + writeline(my_output, my_line); + inst <= str_pad(typeSstring(data, "sh", pc, rs1, rs2, imm_s), ' ', 40); + when TYPE_SW => + swrite(my_line, typeSstring(data, "sw", pc, rs1, rs2, imm_s)); + writeline(my_output, my_line); + inst <= str_pad(typeSstring(data, "sw", pc, rs1, rs2, imm_s), ' ', 40); + when others => + end case; + + when TYPE_L => + case opcodes.funct3 is + when TYPE_LB => + swrite(my_line, typeSstring(data, "lb", pc, rd, rs1, imm_i)); + writeline(my_output, my_line); + inst <= str_pad(typeSstring(data, "lb", pc, rd, rs1, imm_i), ' ', 40); + when TYPE_LBU => + swrite(my_line, typeSstring(data, "lbu", pc, rd, rs1, imm_i)); + writeline(my_output, my_line); + inst <= str_pad(typeSstring(data, "lbu", pc, rd, rs1, imm_i), ' ', 40); + when TYPE_LHU => + swrite(my_line, typeSstring(data, "lhu", pc, rd, rs1, imm_i)); + writeline(my_output, my_line); + inst <= str_pad(typeSstring(data, "lhu", pc, rd, rs1, imm_i), ' ', 40); + when TYPE_LH => + swrite(my_line, typeSstring(data, "lh", pc, rd, rs1, imm_i)); + writeline(my_output, my_line); + inst <= str_pad(typeSstring(data, "lh", pc, rd, rs1, imm_i), ' ', 40); + when TYPE_LW => + swrite(my_line, typeSstring(data, "lw", pc, rd, rs1, imm_i)); + writeline(my_output, my_line); + inst <= str_pad(typeSstring(data, "lw", pc, rd, rs1, imm_i), ' ', 40); + when others => + report "Not implemented" severity Failure; + end case; + + when TYPE_JAL => + swrite(my_line, typeJstring(data, "jal", pc, rd, imm_j)); + writeline(my_output, my_line); + swrite(my_line, ""); + writeline(my_output, my_line); + inst <= str_pad(typeJstring(data, "jal", pc, rd, imm_j), ' ', 40); + when TYPE_JALR => + swrite(my_line, typeJRstring(data, "jalr", pc, rd,rs1 , imm_i)); + writeline(my_output, my_line); + swrite(my_line, ""); + writeline(my_output, my_line); + inst <= str_pad(typeJRstring(data, "jalr", pc, rd,rs1 , imm_i), ' ', 40); + when TYPE_BRANCH => + + case opcodes.funct3 is + when TYPE_BEQ => + swrite(my_line, typeBRstring(data, "beq", pc, rs1, rs2, imm_b)); + writeline(my_output, my_line); + swrite(my_line, ""); + writeline(my_output, my_line); + inst <= str_pad(typeBRstring(data, "beq", pc, rs1, rs2, imm_b), ' ', 40); + when TYPE_BNE => + swrite(my_line, typeBRstring(data, "bne", pc, rs1, rs2, imm_b)); + writeline(my_output, my_line); + swrite(my_line, ""); + writeline(my_output, my_line); + inst <= str_pad(typeBRstring(data, "bne", pc, rs1, rs2, imm_b), ' ', 40); + when TYPE_BLT => + swrite(my_line, typeBRstring(data, "blt", pc, rs1, rs2, imm_b)); + writeline(my_output, my_line); + swrite(my_line, ""); + writeline(my_output, my_line); + inst <= str_pad(typeBRstring(data, "blt", pc, rs1, rs2, imm_b), ' ', 40); + when TYPE_BGE => + swrite(my_line, typeBRstring(data, "bge", pc, rs1, rs2, imm_b)); + writeline(my_output, my_line); + swrite(my_line, ""); + writeline(my_output, my_line); + inst <= str_pad(typeBRstring(data, "bge", pc, rs1, rs2, imm_b), ' ', 40); + when TYPE_BLTU => + swrite(my_line, typeBRstring(data, "bltu", pc, rs1, rs2, imm_b)); + writeline(my_output, my_line); + swrite(my_line, ""); + writeline(my_output, my_line); + inst <= str_pad(typeBRstring(data, "bltu", pc, rs1, rs2, imm_b), ' ', 40); + when TYPE_BGEU => + swrite(my_line, typeBRstring(data, "bgeu", pc, rs1, rs2, imm_b)); + writeline(my_output, my_line); + swrite(my_line, ""); + writeline(my_output, my_line); + inst <= str_pad(typeBRstring(data, "bgeu", pc, rs1, rs2, imm_b), ' ', 40); + when others => + end case; + + when TYPE_ENV_BREAK => + swrite(my_line, "halt!"); + writeline(my_output, my_line); + + when others => + end case; + end process; +end architecture RTL; diff --git a/core/txt_util.vhdl b/core/txt_util.vhdl new file mode 100644 index 00000000..2a6cf6b8 --- /dev/null +++ b/core/txt_util.vhdl @@ -0,0 +1,585 @@ +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; + + +package txt_util is + + -- prints a message to the screen + procedure print(text: string); + + -- prints the message when active + -- useful for debug switches + procedure print(active: boolean; text: string); + + -- converts std_logic into a character + function chr(sl: std_logic) return character; + + -- converts std_logic into a string (1 to 1) + function str(sl: std_logic) return string; + + -- converts std_logic_vector into a string (binary base) + function str(slv: std_logic_vector) return string; + + -- converts boolean into a string + function str(b: boolean) return string; + + -- converts an integer into a single character + -- (can also be used for hex conversion and other bases) + function chr(int: integer) return character; + + -- converts integer into string using specified base + function str(int: integer; base: integer) return string; + + -- converts integer to string, using base 10 + function str(int: integer) return string; + + -- convert std_logic_vector into a string in hex format + function hstr(slv: std_logic_vector) return string; + + + -- functions to manipulate strings + ----------------------------------- + + -- convert a character to upper case + function to_upper(c: character) return character; + + -- convert a character to lower case + function to_lower(c: character) return character; + + -- convert a string to upper case + function to_upper(s: string) return string; + + -- convert a string to lower case + function to_lower(s: string) return string; + + + + -- functions to convert strings into other formats + -------------------------------------------------- + + -- converts a character into std_logic + function to_std_logic(c: character) return std_logic; + + -- converts a string into std_logic_vector + function to_std_logic_vector(s: string) return std_logic_vector; + + + + -- file I/O + ----------- + + -- read variable length string from input file + procedure str_read(file in_file: TEXT; + res_string: out string); + + -- print string to a file and start new line + procedure print(file out_file: TEXT; + new_string: in string); + + -- print character to a file and start new line + procedure print(file out_file: TEXT; + char: in character); + +end txt_util; + + + + +package body txt_util is + + + + + -- prints text to the screen + + procedure print(text: string) is + variable msg_line: line; + begin + write(msg_line, text); + writeline(output, msg_line); + end print; + + + + + -- prints text to the screen when active + + procedure print(active: boolean; text: string) is + begin + if active then + print(text); + end if; + end print; + + + -- converts std_logic into a character + + function chr(sl: std_logic) return character is + variable c: character; + begin + case sl is + when 'U' => c:= 'U'; + when 'X' => c:= 'X'; + when '0' => c:= '0'; + when '1' => c:= '1'; + when 'Z' => c:= 'Z'; + when 'W' => c:= 'W'; + when 'L' => c:= 'L'; + when 'H' => c:= 'H'; + when '-' => c:= '-'; + end case; + return c; + end chr; + + + + -- converts std_logic into a string (1 to 1) + + function str(sl: std_logic) return string is + variable s: string(1 to 1); + begin + s(1) := chr(sl); + return s; + end str; + + + + -- converts std_logic_vector into a string (binary base) + -- (this also takes care of the fact that the range of + -- a string is natural while a std_logic_vector may + -- have an integer range) + + function str(slv: std_logic_vector) return string is + variable result : string (1 to slv'length); + variable r : integer; + begin + r := 1; + for i in slv'range loop + result(r) := chr(slv(i)); + r := r + 1; + end loop; + return result; + end str; + + + function str(b: boolean) return string is + + begin + if b then + return "true"; + else + return "false"; + end if; + end str; + + + -- converts an integer into a character + -- for 0 to 9 the obvious mapping is used, higher + -- values are mapped to the characters A-Z + -- (this is usefull for systems with base > 10) + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function chr(int: integer) return character is + variable c: character; + begin + case int is + when 0 => c := '0'; + when 1 => c := '1'; + when 2 => c := '2'; + when 3 => c := '3'; + when 4 => c := '4'; + when 5 => c := '5'; + when 6 => c := '6'; + when 7 => c := '7'; + when 8 => c := '8'; + when 9 => c := '9'; + when 10 => c := 'A'; + when 11 => c := 'B'; + when 12 => c := 'C'; + when 13 => c := 'D'; + when 14 => c := 'E'; + when 15 => c := 'F'; + when 16 => c := 'G'; + when 17 => c := 'H'; + when 18 => c := 'I'; + when 19 => c := 'J'; + when 20 => c := 'K'; + when 21 => c := 'L'; + when 22 => c := 'M'; + when 23 => c := 'N'; + when 24 => c := 'O'; + when 25 => c := 'P'; + when 26 => c := 'Q'; + when 27 => c := 'R'; + when 28 => c := 'S'; + when 29 => c := 'T'; + when 30 => c := 'U'; + when 31 => c := 'V'; + when 32 => c := 'W'; + when 33 => c := 'X'; + when 34 => c := 'Y'; + when 35 => c := 'Z'; + when others => c := '?'; + end case; + return c; + end chr; + + + + -- convert integer to string using specified base + -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) + + function str(int: integer; base: integer) return string is + + variable temp: string(1 to 10); + variable num: integer; + variable abs_int: integer; + variable len: integer := 1; + variable power: integer := 1; + + begin + + -- bug fix for negative numbers + abs_int := abs(int); + + num := abs_int; + + while num >= base loop -- Determine how many + len := len + 1; -- characters required + num := num / base; -- to represent the + end loop ; -- number. + + for i in len downto 1 loop -- Convert the number to + temp(i) := chr(abs_int/power mod base); -- a string starting + power := power * base; -- with the right hand + end loop ; -- side. + + -- return result and add sign if required + if int < 0 then + return '-'& temp(1 to len); + else + return temp(1 to len); + end if; + + end str; + + + -- convert integer to string, using base 10 + function str(int: integer) return string is + + begin + + return str(int, 10) ; + + end str; + + + + -- converts a std_logic_vector into a hex string. + function hstr(slv: std_logic_vector) return string is + variable hexlen: integer; + variable longslv : std_logic_vector(67 downto 0) := (others => '0'); + variable hex : string(1 to 16); + variable fourbit : std_logic_vector(3 downto 0); + begin + hexlen := (slv'left+1)/4; + if (slv'left+1) mod 4 /= 0 then + hexlen := hexlen + 1; + end if; + longslv(slv'left downto 0) := slv; + for i in (hexlen -1) downto 0 loop + fourbit := longslv(((i*4)+3) downto (i*4)); + case fourbit is + when "0000" => hex(hexlen -I) := '0'; + when "0001" => hex(hexlen -I) := '1'; + when "0010" => hex(hexlen -I) := '2'; + when "0011" => hex(hexlen -I) := '3'; + when "0100" => hex(hexlen -I) := '4'; + when "0101" => hex(hexlen -I) := '5'; + when "0110" => hex(hexlen -I) := '6'; + when "0111" => hex(hexlen -I) := '7'; + when "1000" => hex(hexlen -I) := '8'; + when "1001" => hex(hexlen -I) := '9'; + when "1010" => hex(hexlen -I) := 'A'; + when "1011" => hex(hexlen -I) := 'B'; + when "1100" => hex(hexlen -I) := 'C'; + when "1101" => hex(hexlen -I) := 'D'; + when "1110" => hex(hexlen -I) := 'E'; + when "1111" => hex(hexlen -I) := 'F'; + when "ZZZZ" => hex(hexlen -I) := 'z'; + when "UUUU" => hex(hexlen -I) := 'u'; + when "XXXX" => hex(hexlen -I) := 'x'; + when others => hex(hexlen -I) := '?'; + end case; + end loop; + return hex(1 to hexlen); + end hstr; + + + + -- functions to manipulate strings + ----------------------------------- + + + -- convert a character to upper case + + function to_upper(c: character) return character is + + variable u: character; + + begin + + case c is + when 'a' => u := 'A'; + when 'b' => u := 'B'; + when 'c' => u := 'C'; + when 'd' => u := 'D'; + when 'e' => u := 'E'; + when 'f' => u := 'F'; + when 'g' => u := 'G'; + when 'h' => u := 'H'; + when 'i' => u := 'I'; + when 'j' => u := 'J'; + when 'k' => u := 'K'; + when 'l' => u := 'L'; + when 'm' => u := 'M'; + when 'n' => u := 'N'; + when 'o' => u := 'O'; + when 'p' => u := 'P'; + when 'q' => u := 'Q'; + when 'r' => u := 'R'; + when 's' => u := 'S'; + when 't' => u := 'T'; + when 'u' => u := 'U'; + when 'v' => u := 'V'; + when 'w' => u := 'W'; + when 'x' => u := 'X'; + when 'y' => u := 'Y'; + when 'z' => u := 'Z'; + when others => u := c; + end case; + + return u; + + end to_upper; + + + -- convert a character to lower case + + function to_lower(c: character) return character is + + variable l: character; + + begin + + case c is + when 'A' => l := 'a'; + when 'B' => l := 'b'; + when 'C' => l := 'c'; + when 'D' => l := 'd'; + when 'E' => l := 'e'; + when 'F' => l := 'f'; + when 'G' => l := 'g'; + when 'H' => l := 'h'; + when 'I' => l := 'i'; + when 'J' => l := 'j'; + when 'K' => l := 'k'; + when 'L' => l := 'l'; + when 'M' => l := 'm'; + when 'N' => l := 'n'; + when 'O' => l := 'o'; + when 'P' => l := 'p'; + when 'Q' => l := 'q'; + when 'R' => l := 'r'; + when 'S' => l := 's'; + when 'T' => l := 't'; + when 'U' => l := 'u'; + when 'V' => l := 'v'; + when 'W' => l := 'w'; + when 'X' => l := 'x'; + when 'Y' => l := 'y'; + when 'Z' => l := 'z'; + when others => l := c; + end case; + + return l; + + end to_lower; + + + + -- convert a string to upper case + + function to_upper(s: string) return string is + + variable uppercase: string (s'range); + + begin + + for i in s'range loop + uppercase(i):= to_upper(s(i)); + end loop; + return uppercase; + + end to_upper; + + + + -- convert a string to lower case + + function to_lower(s: string) return string is + + variable lowercase: string (s'range); + + begin + + for i in s'range loop + lowercase(i):= to_lower(s(i)); + end loop; + return lowercase; + + end to_lower; + + + +-- functions to convert strings into other types + + +-- converts a character into a std_logic + +function to_std_logic(c: character) return std_logic is + variable sl: std_logic; + begin + case c is + when 'U' => + sl := 'U'; + when 'X' => + sl := 'X'; + when '0' => + sl := '0'; + when '1' => + sl := '1'; + when 'Z' => + sl := 'Z'; + when 'W' => + sl := 'W'; + when 'L' => + sl := 'L'; + when 'H' => + sl := 'H'; + when '-' => + sl := '-'; + when others => + sl := 'X'; + end case; + return sl; + end to_std_logic; + + +-- converts a string into std_logic_vector + +function to_std_logic_vector(s: string) return std_logic_vector is + variable slv: std_logic_vector(s'high-s'low downto 0); + variable k: integer; +begin + k := s'high-s'low; + for i in s'range loop + slv(k) := to_std_logic(s(i)); + k := k - 1; + end loop; + return slv; +end to_std_logic_vector; + + + + + + +---------------- +-- file I/O -- +---------------- + + + +-- read variable length string from input file + +procedure str_read(file in_file: TEXT; + res_string: out string) is + + variable l: line; + variable c: character; + variable is_string: boolean; + + begin + + readline(in_file, l); + -- clear the contents of the result string + for i in res_string'range loop + res_string(i) := ' '; + end loop; + -- read all characters of the line, up to the length + -- of the results string + for i in res_string'range loop + read(l, c, is_string); + res_string(i) := c; + if not is_string then -- found end of line + exit; + end if; + end loop; + +end str_read; + + +-- print string to a file +procedure print(file out_file: TEXT; + new_string: in string) is + + variable l: line; + + begin + + write(l, new_string); + writeline(out_file, l); + +end print; + + +-- print character to a file and start new line +procedure print(file out_file: TEXT; + char: in character) is + + variable l: line; + + begin + + write(l, char); + writeline(out_file, l); + +end print; + + + +-- appends contents of a string to a file until line feed occurs +-- (LF is considered to be the end of the string) + +procedure str_write(file out_file: TEXT; + new_string: in string) is + begin + + for i in new_string'range loop + print(out_file, new_string(i)); + if new_string(i) = LF then -- end of string + exit; + end if; + end loop; + +end str_write; + + + + +end txt_util; + + + diff --git a/decoder/decoder.vhd b/decoder/decoder.vhd new file mode 100644 index 00000000..d42555b8 --- /dev/null +++ b/decoder/decoder.vhd @@ -0,0 +1,355 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +use work.alu_types.all; +use work.decoder_types.all; +use work.M_types.all; + +entity decoder is + port( + clk : in std_logic; + rst : in std_logic; + + -- RAM signals + dmemory : out mem_ctrl_t; + + -- IR signals + opcodes : in opcodes_t; --! Instruction decoding information. See decoder_types.vhd + + -- bus lag + bus_lag : in std_logic; + + -- Jump and branches signals + jumps : out jumps_ctrl_t; + + -- ULA signals + ulaMuxData : out std_logic_vector(1 downto 0); + ulaCod : out std_logic_vector(3 downto 0); + + -- M signals + M_Cod : out std_logic_vector(2 downto 0); + + --! Write back contrl + writeBackMux: out std_logic_vector(2 downto 0); + reg_write : out std_logic; + + cpu_state : out cpu_state_t + + -- Comparator signals +-- compResult : in std_logic; +-- compMux : out std_logic + + + + ); +end entity decoder; + +architecture RTL of decoder is + type state_type is (READ, FETCH, DECODE, EXE_ALU, EXE_M, ST_TYPE_JAL, + ST_TYPE_AUIPC, ST_TYPE_I, ST_TYPE_U, ST_TYPE_S, ST_BRANCH, ST_TYPE_JALR, ST_TYPE_L, + WRITEBACK, WRITEBACK_MEM, ERROR, HALT + ); + signal state : state_type := READ; + + +begin + + --! State transition process: instruction decoding. + states: process(clk, rst) is + begin + if rst = '1' then + state <= READ; + elsif rising_edge(clk) then + case state is + when READ => + state <= FETCH; + when FETCH => + state <= DECODE; + when DECODE => + case opcodes.opcode is + when TYPE_I => state <= ST_TYPE_I; + when TYPE_AUIPC => state <= ST_TYPE_AUIPC; + when TYPE_LUI => state <= ST_TYPE_U; + when TYPE_R => + if opcodes.funct7 = TYPE_MULDIV then + state <= EXE_M; + else + state <= EXE_ALU; + end if; + when TYPE_S => state <= ST_TYPE_S; + when TYPE_L => state <= ST_TYPE_L; + when TYPE_JAL => state <= ST_TYPE_JAL; + when TYPE_JALR => state <= ST_TYPE_JALR; + when TYPE_BRANCH => state <= ST_BRANCH; + when TYPE_ENV_BREAK => state <= HALT; + when others => state <= ERROR; + end case; + + when ST_TYPE_JAL => + state <= WRITEBACK; + when ST_TYPE_AUIPC => + state <= WRITEBACK; + when ST_TYPE_I => + state <= WRITEBACK; + when EXE_ALU => + state <= WRITEBACK; + when EXE_M => + state <= WRITEBACK; + when ST_TYPE_U => + state <= WRITEBACK; + when ST_TYPE_S => + state <= WRITEBACK; + when ST_BRANCH => + state <= WRITEBACK; + when ST_TYPE_JALR => + state <= WRITEBACK; + when ST_TYPE_L => + state <= WRITEBACK_MEM; + when ERROR => + state <= ERROR; + when WRITEBACK => + state <= FETCH; + when WRITEBACK_MEM => + + if (bus_lag = '0') then + state <= FETCH; + else + state <= READ; + end if; + when HALT => + + end case; + end if; + end process; + + moore : process(state, opcodes) is + begin + ulaMuxData <= "00"; + + -- !Control flow default signal values + jumps.inc <= '0'; + jumps.load <= '0'; + jumps.load_from <= "00"; + + writeBackMux <= "000"; + reg_write <= '0'; + + ulaCod <= (others => '0'); + + M_Cod <= (others => '0'); + + -- !Memory interface default signal values + dmemory.read <= '0'; + dmemory.write <= '0'; + dmemory.signal_ext <= '0'; + dmemory.word_size <= "00"; + + cpu_state.halted <= '0'; + cpu_state.error <= '0'; + + case state is + when READ => + + when FETCH=> + + when DECODE => + + when ST_TYPE_JAL => + jumps.load <= '1'; + jumps.load_from <= "00"; + writeBackMux <= "011"; + reg_write <= '1'; + + when ST_TYPE_AUIPC => + writeBackMux <= "010"; + jumps.inc <= '1'; + reg_write <= '1'; + + when ST_TYPE_I => + case opcodes.funct3 is + + when TYPE_ADDI => + ulaMuxData <= "01"; + ulaCod <= ALU_ADD; + + when TYPE_SLTI => + report "Not implemented" severity Failure; + + when TYPE_SLTIU => + report "Not implemented" severity Failure; + + when TYPE_XORI => + ulaMuxData <= "01"; + ulaCod <= ALU_XOR; + + when TYPE_ORI => + ulaMuxData <= "01"; + ulaCod <= ALU_OR; + + when TYPE_ANDI => + ulaMuxData <= "01"; + ulaCod <= ALU_AND; + + when TYPE_SLLI => + ulaMuxData <= "01"; + ulaCod <= ALU_SLL; + + when TYPE_SR => + case opcodes.funct7 is + when TYPE_SRLI => + ulaMuxData <= "01"; + ulaCod <= ALU_SRL; + when TYPE_SRAI => + ulaMuxData <= "01"; + ulaCod <= ALU_SRA; + when others => + end case; + + + when others => + report "Not implemented" severity Failure; + end case; + + --writeBackMux <= "001"; + jumps.inc <= '1'; + reg_write <= '1'; + --================================================================================== + when EXE_M => + case opcodes.funct3 is + when TYPE_MUL => + M_Cod <= M_MUL; + when TYPE_MULH => + M_Cod <= M_MULH; + when TYPE_MULHU => + M_Cod <= M_MULHU; + when TYPE_MULHSU => + M_Cod <= M_MULHSU; + when TYPE_DIV => + M_Cod <= M_DIV; + when TYPE_DIVU => + M_Cod <= M_DIVU; + when TYPE_REM => + M_Cod <= M_REM; + when TYPE_REMU => + M_Cod <= M_REMU; + when others => + report "Not implemented" severity Failure; + end case; + + writeBackMux <= "101"; + jumps.inc <= '1'; + reg_write <= '1'; + + when EXE_ALU => + case opcodes.funct3 is + when TYPE_ADD_SUB => + if opcodes.funct7 = TYPE_ADD then + ulaCod <= ALU_ADD; + else + ulaCod <= ALU_SUB; + end if; + + when TYPE_AND => + ulaCod <= ALU_AND; + + when TYPE_SLL => + ulaCod <= ALU_SLL; + + when TYPE_XOR => + ulaCod <= ALU_XOR; + + when TYPE_OR => + ulaCod <= ALU_OR; + + -- constant TYPE_SR: Uses same logic of TYPE_I + when TYPE_SR => + case opcodes.funct7 is + when TYPE_SRLI => + ulaCod <= ALU_SRL; + when TYPE_SRAI => + ulaCod <= ALU_SRA; + when others => + end case; + + when others => + report "Not implemented" severity Failure; + end case; + + jumps.inc <= '1'; + reg_write <= '1'; + + --! "00": word, "01": half word, "11" byte + when ST_TYPE_S => + + case opcodes.funct3 is + when TYPE_SB => + dmemory.write <= '1'; + dmemory.word_size <= "11"; + when TYPE_SH => + dmemory.write <= '1'; + dmemory.word_size <= "01"; + when TYPE_SW => + dmemory.write <= '1'; + dmemory.word_size <= "00"; + when others => + end case; + + jumps.inc <= '1'; + + when ST_TYPE_U => + writeBackMux <= "001"; + jumps.inc <= '1'; + reg_write <= '1'; + + when ST_BRANCH => + jumps.load <= '1'; + jumps.load_from <= "01"; + + when ST_TYPE_JALR => + jumps.load <= '1'; + jumps.load_from <= "11"; + when ST_TYPE_L => + case opcodes.funct3 is + when TYPE_LB => + dmemory.signal_ext <= '1'; + dmemory.read <= '1'; + dmemory.word_size <= "11"; + when TYPE_LH => + dmemory.signal_ext <= '1'; + dmemory.read <= '1'; + dmemory.word_size <= "01"; + when TYPE_LW => + dmemory.read <= '1'; + dmemory.word_size <= "00"; + when TYPE_LBU => + dmemory.read <= '1'; + dmemory.word_size <= "11"; + when TYPE_LHU => + dmemory.read <= '1'; + dmemory.word_size <= "01"; + when others => + report "Not implemented" severity Failure; + end case; + + jumps.inc <= '1'; + + when ERROR => + cpu_state.error <= '0'; + report "Not implemented" severity Failure; + + when HALT => + cpu_state.halted <= '0'; + report "Simulation success!" severity Failure; + + when WRITEBACK => + + when WRITEBACK_MEM => + writeBackMux <= "100"; + reg_write <= '1'; + dmemory.read <= '1'; + end case; + + end process moore; + +end architecture RTL; diff --git a/decoder/decoder_types.vhd b/decoder/decoder_types.vhd new file mode 100644 index 00000000..3f551bcf --- /dev/null +++ b/decoder/decoder_types.vhd @@ -0,0 +1,138 @@ +LIBRARY ieee; +USE IEEE.STD_LOGIC_1164.ALL; + +package decoder_types is + + ------------------------------------------------------------------- + --! Record for instruction decoding + type opcodes_t is record + opcode : std_logic_vector(6 downto 0); --! Instruction opcode + funct3 : std_logic_vector(2 downto 0); --! Instruction function: 7 bits + funct7 : std_logic_vector(6 downto 0); --! Instruction function: 3 bits + end record opcodes_t; + + ------------------------------------------------------------------- + --! Record for memory controller + type mem_ctrl_t is record + read : std_logic; --! Memory read signal + write: std_logic; --! Memory write signal + signal_ext : std_logic; --! Signal extension + bus_lag : std_logic; --! Active when another cycle is need for bus transaction (reada DATA f + word_size : std_logic_vector(1 downto 0); --! "00": word, "01": half word, "11" byte + end record mem_ctrl_t; + + ------------------------------------------------------------------- + --! Record for control flow instructions + type jumps_ctrl_t is record + inc : std_logic; --! Memory read signal + load: std_logic; --! Memory write signal + load_from : std_logic_vector(1 downto 0); --! "00": pc + j_imm + end record jumps_ctrl_t; + + ------------------------------------------------------------------- + --! Record for cpu state + type cpu_state_t is record + halted : std_logic; --! CPU is halted (execution of ebreak) + error : std_logic; --! There is an error + end record cpu_state_t; + + ------------------------------------------------------------------- + --! Arithmetic type R opcode + constant TYPE_R : std_logic_vector(6 downto 0) := "0110011"; + --! Func3 opcodes + constant TYPE_ADD_SUB : std_logic_vector(2 downto 0) := "000"; + --! Func7 opcodes + constant TYPE_ADD : std_logic_vector(6 downto 0) := "0000000"; + constant TYPE_SUB : std_logic_vector(6 downto 0) := "0100000"; + constant TYPE_SLL : std_logic_vector(2 downto 0) := "001"; + constant TYPE_SLT : std_logic_vector(2 downto 0) := "010"; + constant TYPE_SLU : std_logic_vector(2 downto 0) := "011"; + constant TYPE_XOR : std_logic_vector(2 downto 0) := "100"; + -- constant TYPE_SR: Uses same logic of TYPE_I + constant TYPE_OR : std_logic_vector(2 downto 0) := "110"; + constant TYPE_AND : std_logic_vector(2 downto 0) := "111"; + + --! M + --! Func7 opcodes + constant TYPE_MULDIV : std_logic_vector(6 downto 0) := "0000001"; + --! Func3 opcodes + constant TYPE_MUL: std_logic_vector(2 downto 0) := "000"; + constant TYPE_MULH: std_logic_vector(2 downto 0) := "001"; + constant TYPE_MULHU: std_logic_vector(2 downto 0) := "010"; + constant TYPE_MULHSU: std_logic_vector(2 downto 0) := "011"; + constant TYPE_DIV: std_logic_vector(2 downto 0) := "100"; + constant TYPE_DIVU: std_logic_vector(2 downto 0) := "101"; + constant TYPE_REM: std_logic_vector(2 downto 0) := "110"; + constant TYPE_REMU: std_logic_vector(2 downto 0) := "111"; + + + ------------------------------------------------------------------- + --! Arithmetic type I opcode + constant TYPE_I : std_logic_vector(6 downto 0) := "0010011"; + + --! Func3 opcodes + constant TYPE_ADDI : std_logic_vector(2 downto 0) := "000"; + constant TYPE_SLTI : std_logic_vector(2 downto 0) := "010"; + constant TYPE_SLTIU : std_logic_vector(2 downto 0) := "011"; + constant TYPE_XORI : std_logic_vector(2 downto 0) := "100"; + constant TYPE_ORI : std_logic_vector(2 downto 0) := "110"; + constant TYPE_ANDI : std_logic_vector(2 downto 0) := "111"; + constant TYPE_SLLI : std_logic_vector(2 downto 0) := "001"; + constant TYPE_SR : std_logic_vector(2 downto 0) := "101"; + --! Func7 opcodes + constant TYPE_SRLI : std_logic_vector(6 downto 0) := "0000000"; + constant TYPE_SRAI : std_logic_vector(6 downto 0) := "0100000"; + + ------------------------------------------------------------------- + --! Branch opcodes + constant TYPE_BRANCH : std_logic_vector(6 downto 0) := "1100011"; + --! Func3 opcodes + constant TYPE_BEQ : std_logic_vector(2 downto 0) := "000"; + constant TYPE_BNE : std_logic_vector(2 downto 0) := "001"; + constant TYPE_BLT : std_logic_vector(2 downto 0) := "100"; + constant TYPE_BGE : std_logic_vector(2 downto 0) := "101"; + constant TYPE_BLTU : std_logic_vector(2 downto 0) := "110"; + constant TYPE_BGEU : std_logic_vector(2 downto 0) := "111"; + + ------------------------------------------------------------------- + --! Memory type S opcode + constant TYPE_S : std_logic_vector(6 downto 0) := "0100011"; + --! Func3 opcodes + constant TYPE_SB : std_logic_vector(2 downto 0) := "000"; + constant TYPE_SH : std_logic_vector(2 downto 0) := "001"; + constant TYPE_SW : std_logic_vector(2 downto 0) := "010"; + + ------------------------------------------------------------------- + --! Memory type L opcode + constant TYPE_L : std_logic_vector(6 downto 0) := "0000011"; + --! Func3 opcodes + constant TYPE_LB : std_logic_vector(2 downto 0) := "000"; + constant TYPE_LH : std_logic_vector(2 downto 0) := "001"; + constant TYPE_LW : std_logic_vector(2 downto 0) := "010"; + constant TYPE_LBU : std_logic_vector(2 downto 0) := "100"; + constant TYPE_LHU : std_logic_vector(2 downto 0) := "101"; + + ------------------------------------------------------------------- + --! Jumps opcode + constant TYPE_JAL : std_logic_vector(6 downto 0) := "1101111"; + constant TYPE_JALR : std_logic_vector(6 downto 0) := "1100111"; + + ------------------------------------------------------------------- + --! Special type U opcode + constant TYPE_LUI : std_logic_vector(6 downto 0) := "0110111"; + constant TYPE_AUIPC : std_logic_vector(6 downto 0) := "0010111"; + + ------------------------------------------------------------------- + --! Environment Call and Breakpoints + constant TYPE_ENV_BREAK : std_logic_vector(6 downto 0) := "1110011"; + --! Func3 opcodes + constant TYPE_EBREAK_ECALL : std_logic_vector(2 downto 0) := "000"; + --! Func7 opcodes + constant TYPE_EBREAK : std_logic_vector(6 downto 0) := "0000001"; + + +end package decoder_types; + +package body decoder_types is + +end package body decoder_types; diff --git a/decoder/iregister.vhd b/decoder/iregister.vhd new file mode 100644 index 00000000..e0a1dac8 --- /dev/null +++ b/decoder/iregister.vhd @@ -0,0 +1,82 @@ +------------------------------------------------------- +--! @file +--! @brief RISCV Instruction decoder +------------------------------------------------------- + +--! Use standard library +library ieee; + --! Use standard logic elements + use ieee.std_logic_1164.all; + --! Use conversion functions + use ieee.numeric_std.all; + +use work.decoder_types.all; + +--! iregister decodes (bit slicing) a instruction word into +--! several parameters (register addresses, call addresses, +--! immediates). See RV32I instruction format +entity iregister is + port( + clk : in std_logic; --! Clock input + rst : in std_logic; --! Asynchronous reset + + data : in std_logic_vector(31 downto 0); + + opcodes : out opcodes_t; --! Instruction decoding information. See decoder_types.vhd + + -- opcode : out std_logic_vector(6 downto 0); --! Instruction opcode + -- funct3 : out std_logic_vector(2 downto 0); --! Instruction function: 7 bits + -- funct7 : out std_logic_vector(6 downto 0); --! Instruction function: 3 bits + + rd : out integer range 0 to 31; --! Register address destination + rs1 : out integer range 0 to 31; --! Register address source operand 1 + rs2 : out integer range 0 to 31; --! Register address source operand 2 + + imm_i : out integer; --! Immediate for I-type instruction + imm_s : out integer; --! Immediate for S-type instruction + imm_b : out integer; --! Immediate for B-type instruction + imm_u : out integer; --! Immediate for U-type instruction + imm_j : out integer --! Immediate for J-type instruction + ); +end entity iregister; + +architecture RTL of iregister is + + +begin + --! @brief Decoder process. Must me synchronous for registers generation + p1: process (rst, clk) + begin + if rst = '1' then + opcodes.opcode <= (others => '0'); + opcodes.funct3 <= (others => '0'); + opcodes.funct7 <= (others => '0'); + rd <= 0; + rs1 <= 0; + rs2 <= 0; + + imm_i <= 0; + imm_s <= 0; + imm_b <= 0; + imm_u <= 0; + imm_j <= 0; + else + if rising_edge(clk) then + opcodes.opcode <= data (6 downto 0); + opcodes.funct3 <= data(14 downto 12); + opcodes.funct7 <= data(31 downto 25); + + rd <= to_integer(unsigned(data(11 downto 7))); + rs1 <= to_integer(unsigned(data(19 downto 15))); + rs2 <= to_integer(unsigned(data(24 downto 20))); + + imm_i <= to_integer(signed(data(31 downto 20))); + imm_s <= to_integer(signed(data(31 downto 25) & data(11 downto 7))); + imm_b <= to_integer(signed(data(31) & data(7) & data(30 downto 25) & data(11 downto 8) & '0')); + imm_u <= to_integer(signed(data(31 downto 12) & "000000000000")); + imm_j <= to_integer(signed(data(31) & data(19 downto 12) & data(20) & data(30 downto 21) & '0')); + + end if; + end if; + end process; +end architecture RTL; diff --git a/docs/guia-pratico-risc-v-1.0.0.pdf b/docs/guia-pratico-risc-v-1.0.0.pdf new file mode 100644 index 00000000..3efe782c Binary files /dev/null and b/docs/guia-pratico-risc-v-1.0.0.pdf differ diff --git a/docs/riscv-spec-v2.2.pdf b/docs/riscv-spec-v2.2.pdf new file mode 100644 index 00000000..e4a46348 Binary files /dev/null and b/docs/riscv-spec-v2.2.pdf differ diff --git a/memory/dmemory.vhd b/memory/dmemory.vhd new file mode 100644 index 00000000..d55be47a --- /dev/null +++ b/memory/dmemory.vhd @@ -0,0 +1,222 @@ +------------------------------------------------------- +--! @file +--! @brief Simple instruction memory +------------------------------------------------------- + +--! Use standard library +library ieee; + --! Use standard logic elements + use ieee.std_logic_1164.all; + --! Use conversion functions + use ieee.numeric_std.all; + + +--! dmemory entity brief description + +--! Detailed description of this +--! dmemory design element. + +entity dmemory is + generic ( + --! Num of 32-bits memory words + MEMORY_WORDS : integer := 256 + ); + port( + rst : in std_logic; + clk : in std_logic; --! Clock input + data: in std_logic_vector (31 downto 0); --! Write data input + address: in integer range 0 to MEMORY_WORDS-1; --! Address to be read + we: in std_logic; --! Write Enable + csel : in std_logic; --! Chip select + dmask : in std_logic_vector(3 downto 0); --! Byte enable mask + signal_ext : in std_logic; --! Signess extensions 1: to extend signal + q: out std_logic_vector (31 downto 0) --! Read output + ); +end entity dmemory; + + +--! @brief Architecture definition of the imemory +--! @details More details about this imemory element. +architecture RTL of dmemory is + type mem is array (0 to MEMORY_WORDS-1) of std_logic_vector(31 downto 0); --! Array MEMORY_WORDS x 31 bits type creation + + impure function InitRam return mem is + variable RAM : mem; + begin + + for i in mem'range loop + RAM(i) := (others => '0'); + end loop; + + return RAM; + end function; + + + signal ram_block: mem; -- := InitRam; --! RAM Block instance + signal read_address_reg: integer range 0 to MEMORY_WORDS-1; --! Read address register + signal dmask_reg : std_logic_vector(3 downto 0); --! Syncronization of dmaks. Necessary for Read transations. + signal signal_ext_reg : std_logic; + + type state_type is (READ, WORD, BYTE0, BYTE1, BYTE2, BYTE3, HALF_WORD_LOW, HALF_WORD_HIGH); + signal state : state_type; + + signal fsm_we : std_logic; + signal fsm_data : std_logic_vector (31 downto 0); + signal ram_data : std_logic_vector (31 downto 0); + +begin + + --! @brief Memory transaction process. Must me synchronous and with this format + p1: process (clk) + begin + if rising_edge(clk) then + if (fsm_we = '1') then + ram_block(address) <= fsm_data; + end if; + + signal_ext_reg <= signal_ext; + dmask_reg <= dmask; + read_address_reg <= address; + end if; + end process; + + fsm_state_write: process(clk, rst) + begin + if rst = '1' then + state <= READ; + else + if rising_edge(clk) then + case state is + when READ => + if we = '1' and csel='1' then + case dmask is + when "1111" => + state <= WORD; + when "0011" => + state <= HALF_WORD_LOW; + when "1100" => + state <= HALF_WORD_HIGH; + when "0001" => + state <= BYTE0; + when "0010" => + state <= BYTE1; + when "0100" => + state <= BYTE2; + when "1000" => + state <= BYTE3; + when others => + end case; + end if; + when WORD => + state <= READ; + when HALF_WORD_HIGH => + state <= READ; + when HALF_WORD_LOW => + state <= READ; + when BYTE0 => + state <= READ; + when BYTE1 => + state <= READ; + when BYTE2 => + state <= READ; + when BYTE3 => + state <= READ; + end case; + + end if; + + end if; + end process; + + fsm_moore_write: process(state,ram_data,data) + begin + fsm_we <= '0'; + fsm_data <= data; + + case state is + when READ => + + when WORD => + fsm_we <= '1'; + fsm_data <= data; + when HALF_WORD_LOW => + fsm_we <= '1'; + fsm_data <= ram_data(31 downto 16) & data(15 downto 0); + when HALF_WORD_HIGH => + fsm_we <= '1'; + fsm_data <= data(15 downto 0) & ram_data(15 downto 0); + when BYTE0 => + fsm_we <= '1'; + fsm_data <= ram_data(31 downto 8) & data(7 downto 0); + when BYTE1 => + fsm_we <= '1'; + fsm_data <= ram_data(31 downto 16) & data(7 downto 0) & ram_data(7 downto 0); + when BYTE2 => + fsm_we <= '1'; + fsm_data <= ram_data(31 downto 24) & data(7 downto 0) & ram_data(15 downto 0); + when BYTE3 => + fsm_we <= '1'; + fsm_data <= data(7 downto 0) & ram_data(23 downto 0); + end case; + end process; + + ram_data <= ram_block(read_address_reg); + + -- Mask for byte, halfword and work read + read_process: process (csel, ram_data, signal_ext_reg, dmask_reg) + begin + q <= (others => '0'); + if csel = '1' then + case dmask_reg is + when "1111" => --! Word access + q <= ram_data; + when "0011" => --! Half access + if signal_ext_reg = '1' and ram_data(15) = '1' then + q <= x"FFFF" & ram_data(15 downto 0); --! Signal extension + else + q <= x"0000" & ram_data(15 downto 0); + end if; + when "1100" => + if signal_ext_reg = '1' and ram_data(31) = '1' then + q <= x"FFFF" & ram_data(31 downto 16); --! Signal extension + else + q <= x"0000" & ram_data(31 downto 16); + end if; + when "0001" => + if signal_ext_reg = '1' and ram_data(7) = '1' then + q <= x"FFFFFF" & ram_data(7 downto 0); --! Signal extension + else + q <= x"000000" & ram_data(7 downto 0); + end if; + when "0010" => + if signal_ext_reg = '1' and ram_data(15) = '1' then + q <= x"FFFFFF" & ram_data(15 downto 8); --! Signal extension + else + q <= x"000000" & ram_data(15 downto 8); + end if; + when "0100" => + if signal_ext_reg = '1' and ram_data(23) = '1' then + q <= x"FFFFFF" & ram_data(23 downto 16); --! Signal extension + else + q <= x"000000" & ram_data(23 downto 16); + end if; + when "1000" => + if signal_ext_reg = '1' and ram_data(23) = '1' then + q <= x"FFFFFF" & ram_data(31 downto 24); --! Signal extension + else + q <= x"000000" & ram_data(31 downto 24); + end if; + when others => + end case; + end if; + end process; + + +-- with csel select +-- q <= ram_data when '1', +-- (others => '0') when others; + + + +end architecture RTL; + diff --git a/memory/iram_quartus.cmp b/memory/iram_quartus.cmp new file mode 100644 index 00000000..9d74f821 --- /dev/null +++ b/memory/iram_quartus.cmp @@ -0,0 +1,26 @@ +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +component iram_quartus + PORT + ( + address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1'); + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/memory/iram_quartus.qip b/memory/iram_quartus.qip new file mode 100644 index 00000000..86dc3459 --- /dev/null +++ b/memory/iram_quartus.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "iram_quartus.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "iram_quartus_inst.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "iram_quartus.cmp"] diff --git a/memory/iram_quartus.vhd b/memory/iram_quartus.vhd new file mode 100644 index 00000000..87036701 --- /dev/null +++ b/memory/iram_quartus.vhd @@ -0,0 +1,164 @@ +-- megafunction wizard: %RAM: 1-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: iram_quartus.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 18.1.0 Build 625 09/12/2018 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY iram_quartus IS + PORT + ( + address : IN STD_LOGIC_VECTOR (9 DOWNTO 0); + byteena : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1'); + clock : IN STD_LOGIC := '1'; + data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + wren : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END iram_quartus; + + +ARCHITECTURE SYN OF iram_quartus IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); + +BEGIN + q <= sub_wire0(31 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + byte_size => 8, + clock_enable_input_a => "BYPASS", + clock_enable_output_a => "BYPASS", + init_file => "./tests/quartus.hex", + intended_device_family => "MAX 10", + lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1", + lpm_type => "altsyncram", + numwords_a => 1024, + operation_mode => "SINGLE_PORT", + outdata_aclr_a => "NONE", + outdata_reg_a => "UNREGISTERED", + power_up_uninitialized => "FALSE", + read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ", + widthad_a => 10, + width_a => 32, + width_byteena_a => 4 + ) + PORT MAP ( + address_a => address, + byteena_a => byteena, + clock0 => clock, + data_a => data, + wren_a => wren, + q_a => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0" +-- Retrieval info: PRIVATE: AclrByte NUMERIC "0" +-- Retrieval info: PRIVATE: AclrData NUMERIC "0" +-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clken NUMERIC "0" +-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" +-- Retrieval info: PRIVATE: JTAG_ID STRING "1" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "./tests/quartus.hex" +-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: RegAddr NUMERIC "1" +-- Retrieval info: PRIVATE: RegData NUMERIC "1" +-- Retrieval info: PRIVATE: RegOutput NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: SingleClock NUMERIC "1" +-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" +-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10" +-- Retrieval info: PRIVATE: WidthData NUMERIC "32" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: INIT_FILE STRING "./tests/quartus.hex" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=1" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4" +-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]" +-- Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" +-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" +-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" +-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0 +-- Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL iram_quartus.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL iram_quartus.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL iram_quartus.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL iram_quartus.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL iram_quartus_inst.vhd TRUE +-- Retrieval info: LIB_FILE: altera_mf \ No newline at end of file diff --git a/memory/iram_quartus_inst.vhd b/memory/iram_quartus_inst.vhd new file mode 100644 index 00000000..c689f873 --- /dev/null +++ b/memory/iram_quartus_inst.vhd @@ -0,0 +1,8 @@ +iram_quartus_inst : iram_quartus PORT MAP ( + address => address_sig, + byteena => byteena_sig, + clock => clock_sig, + data => data_sig, + wren => wren_sig, + q => q_sig + ); diff --git a/peripherals/.gitignore b/peripherals/.gitignore new file mode 100644 index 00000000..1312be9d --- /dev/null +++ b/peripherals/.gitignore @@ -0,0 +1,20 @@ +# For Eclipse / Sigasi: +.project +.library_mapping.xml +.settings + +# For Quartus: +*/sint/* +!*/sint/de10_lite.qpf +!*/sint/de10_lite.qws +!*/sint/de10_lite.qsf +!*/sint/de10_lite.sdc +!*/sint/de10_lite.ipregen.rpt +!*/sint/de10_lite_description.txt +!*/sint/de10_lite_assignment_defaults.qdf +!*/sint/*.md +!*/sint/*.vhd + +# For Modelsim: +*.ps +tft/wlft* diff --git a/peripherals/README.md b/peripherals/README.md new file mode 100644 index 00000000..54d78531 --- /dev/null +++ b/peripherals/README.md @@ -0,0 +1 @@ +# Peripherals base folder diff --git a/peripherals/adc/README.md b/peripherals/adc/README.md new file mode 100644 index 00000000..0406eb5d --- /dev/null +++ b/peripherals/adc/README.md @@ -0,0 +1,41 @@ + + +DOCUMENTAÇÃO ADC E DISPLAY 7 SEGMENTOS DE-10LITE + + +1- O HARDWARE + + +A implementação do ADC trata-se de um bloco IP da Altera, é configurado pelo arquivo "adc_qsys.qsys" utilizando-se a ferramenta própria da Altera. +Maiores informações em https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/archives/ug-m10-adc-16.1.pdf + +No arquivo "Top-level Hierarchy", "de0_lite.vhd", pode-se observar a Instancia do Componente ADC bem como o Port Map e Sinais necessários para o seu funcionamento. + +No process "-- Output register" o softcore envia ao hardware o número do canal que deve ser lido o ADC e também o registrador com os dígitos separados em hexadecimal que devem ser enviados aos displays de 7 segmentos do kit. + +No process "-- Input register" envia-se o valor do ADC para o registrador de I/O do softcore, onde os 12 bits menos significativos do registrador de I/O recebe o valor bruto do ADC e os bits 12 a 15 recebem o número do canal cujo valor foi lido, conforme ilustrado abaixo: + + input_in(11 downto 0) <= adc_sample_data; + input_in(15 downto 12) <= cur_adc_ch(3 downto 0); + + +Também neste mesmo arquivo foi declarado os componentes "displays()" que são responsáveis por receber um dígito hexadecimal e codifiar para os respectivos displays de 7 segmentos presentes no Kit DE-10LITE. + + +2- SOFTWARE + +No arquivo "hardware.h" estão definidos os nomes e endereços dos registradores de I/O: + +INDATA_ADC -> recebe o valor do ADC e respectivo canal. +SEL_CH_ADC -> envia ao hardware o número do canal ADC a ser lido +OUT_SEGS -> envia os dvalores em hexadecimal aos displays de 7 segmentos. São 6 displays ordenados nos 24bits mais significativos. + + +No arquivo "hardware_ADC_7SEG.h" estão definidos uma estrutura de dados para armazenar o valor lido do ADC e seu respectivo canal, bem como a declaração das funções para ler o ADC e escrever nos displays de 7 segmentos. + + +3- Valor ADC. + +O valor lido do ADC é bruto, devendo-se fazer as devidas conversões de acordo com a conveniencia pretendida. +No exemplo do arquivo "firmware.c" o valor foi convertido em mV. + \ No newline at end of file diff --git a/peripherals/adc/adc.bsf b/peripherals/adc/adc.bsf new file mode 100644 index 00000000..2153e9ff --- /dev/null +++ b/peripherals/adc/adc.bsf @@ -0,0 +1,178 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 448 432) + (text "adc" (rect 214 -1 228 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 416 20 428)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "clock_clk" (rect 0 0 36 12)(font "Arial" (font_size 8))) + (text "clock_clk" (rect 4 61 58 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 192 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "reset_sink_reset_n" (rect 0 0 77 12)(font "Arial" (font_size 8))) + (text "reset_sink_reset_n" (rect 4 101 112 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 192 112)(line_width 1)) + ) + (port + (pt 0 152) + (input) + (text "adc_pll_clock_clk" (rect 0 0 69 12)(font "Arial" (font_size 8))) + (text "adc_pll_clock_clk" (rect 4 141 106 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 192 152)(line_width 1)) + ) + (port + (pt 0 192) + (input) + (text "adc_pll_locked_export" (rect 0 0 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(font_size 8))) + (text "sample_store_csr_writedata[31..0]" (rect 4 373 202 384)(font "Arial" (font_size 8))) + (line (pt 0 384)(pt 192 384)(line_width 3)) + ) + (port + (pt 0 296) + (output) + (text "sequencer_csr_readdata[31..0]" (rect 0 0 123 12)(font "Arial" (font_size 8))) + (text "sequencer_csr_readdata[31..0]" (rect 4 285 178 296)(font "Arial" (font_size 8))) + (line (pt 0 296)(pt 192 296)(line_width 3)) + ) + (port + (pt 0 400) + (output) + (text "sample_store_csr_readdata[31..0]" (rect 0 0 136 12)(font "Arial" (font_size 8))) + (text "sample_store_csr_readdata[31..0]" (rect 4 389 196 400)(font "Arial" (font_size 8))) + (line (pt 0 400)(pt 192 400)(line_width 3)) + ) + (port + (pt 448 72) + (output) + (text "sample_store_irq_irq" (rect 0 0 84 12)(font "Arial" (font_size 8))) + (text "sample_store_irq_irq" (rect 342 61 462 72)(font "Arial" (font_size 8))) + (line (pt 448 72)(pt 256 72)(line_width 1)) + ) + (drawing + (text "clock" (rect 164 43 358 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 197 67 412 144)(font "Arial" (color 0 0 0))) + (text "reset_sink" (rect 131 83 322 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset_n" (rect 197 107 436 224)(font "Arial" (color 0 0 0))) + (text "adc_pll_clock" (rect 115 123 308 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 197 147 412 304)(font "Arial" (color 0 0 0))) + (text "adc_pll_locked" (rect 107 163 298 339)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 197 187 430 384)(font "Arial" (color 0 0 0))) + (text "sequencer_csr" (rect 107 203 292 419)(font "Arial" (color 128 0 0)(font_size 9))) + (text "address" (rect 197 227 436 464)(font "Arial" (color 0 0 0))) + (text "read" (rect 197 243 418 496)(font "Arial" (color 0 0 0))) + (text "write" (rect 197 259 424 528)(font "Arial" (color 0 0 0))) + (text "writedata" (rect 197 275 448 560)(font "Arial" (color 0 0 0))) + (text "readdata" (rect 197 291 442 592)(font "Arial" (color 0 0 0))) + (text "sample_store_csr" (rect 87 307 270 627)(font "Arial" (color 128 0 0)(font_size 9))) + (text "address" (rect 197 331 436 672)(font "Arial" (color 0 0 0))) + (text "read" (rect 197 347 418 704)(font "Arial" (color 0 0 0))) + (text "write" (rect 197 363 424 736)(font "Arial" (color 0 0 0))) + (text "writedata" (rect 197 379 448 768)(font "Arial" (color 0 0 0))) + (text "readdata" (rect 197 395 442 800)(font "Arial" (color 0 0 0))) + (text "sample_store_irq" (rect 257 43 610 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "irq" (rect 242 67 502 144)(font "Arial" (color 0 0 0))) + (text " system " (rect 413 416 874 842)(font "Arial" )) + (line (pt 192 32)(pt 256 32)(line_width 1)) + (line (pt 256 32)(pt 256 416)(line_width 1)) + (line (pt 192 416)(pt 256 416)(line_width 1)) + (line (pt 192 32)(pt 192 416)(line_width 1)) + (line (pt 193 52)(pt 193 76)(line_width 1)) + (line (pt 194 52)(pt 194 76)(line_width 1)) + (line (pt 193 92)(pt 193 116)(line_width 1)) + (line (pt 194 92)(pt 194 116)(line_width 1)) + (line (pt 193 132)(pt 193 156)(line_width 1)) + (line (pt 194 132)(pt 194 156)(line_width 1)) + (line (pt 193 172)(pt 193 196)(line_width 1)) + (line (pt 194 172)(pt 194 196)(line_width 1)) + (line (pt 193 212)(pt 193 300)(line_width 1)) + (line (pt 194 212)(pt 194 300)(line_width 1)) + (line (pt 193 316)(pt 193 404)(line_width 1)) + (line (pt 194 316)(pt 194 404)(line_width 1)) + (line (pt 255 52)(pt 255 76)(line_width 1)) + (line (pt 254 52)(pt 254 76)(line_width 1)) + (line (pt 0 0)(pt 448 0)(line_width 1)) + (line (pt 448 0)(pt 448 432)(line_width 1)) + (line (pt 0 432)(pt 448 432)(line_width 1)) + (line (pt 0 0)(pt 0 432)(line_width 1)) + ) +) diff --git a/peripherals/adc/adc.cmp b/peripherals/adc/adc.cmp new file mode 100644 index 00000000..9bc3c496 --- /dev/null +++ b/peripherals/adc/adc.cmp @@ -0,0 +1,20 @@ + component adc is + port ( + clock_clk : in std_logic := 'X'; -- clk + reset_sink_reset_n : in std_logic := 'X'; -- reset_n + adc_pll_clock_clk : in std_logic := 'X'; -- clk + adc_pll_locked_export : in std_logic := 'X'; -- export + sequencer_csr_address : in std_logic := 'X'; -- address + sequencer_csr_read : in std_logic := 'X'; -- read + sequencer_csr_write : in std_logic := 'X'; -- write + sequencer_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + sequencer_csr_readdata : out std_logic_vector(31 downto 0); -- readdata + sample_store_csr_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address + sample_store_csr_read : in std_logic := 'X'; -- read + sample_store_csr_write : in std_logic := 'X'; -- write + sample_store_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + sample_store_csr_readdata : out std_logic_vector(31 downto 0); -- readdata + sample_store_irq_irq : out std_logic -- irq + ); + end component adc; + diff --git a/peripherals/adc/adc.ppf b/peripherals/adc/adc.ppf new file mode 100644 index 00000000..9c1b6f4d --- /dev/null +++ b/peripherals/adc/adc.ppf @@ -0,0 +1,39 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/peripherals/adc/adc_bb.v b/peripherals/adc/adc_bb.v new file mode 100644 index 00000000..71c7fd47 --- /dev/null +++ b/peripherals/adc/adc_bb.v @@ -0,0 +1,34 @@ + +module adc ( + clock_clk, + reset_sink_reset_n, + adc_pll_clock_clk, + adc_pll_locked_export, + sequencer_csr_address, + sequencer_csr_read, + sequencer_csr_write, + sequencer_csr_writedata, + sequencer_csr_readdata, + sample_store_csr_address, + sample_store_csr_read, + sample_store_csr_write, + sample_store_csr_writedata, + sample_store_csr_readdata, + sample_store_irq_irq); + + input clock_clk; + input reset_sink_reset_n; + input adc_pll_clock_clk; + input adc_pll_locked_export; + input sequencer_csr_address; + input sequencer_csr_read; + input sequencer_csr_write; + input [31:0] sequencer_csr_writedata; + output [31:0] sequencer_csr_readdata; + input [6:0] sample_store_csr_address; + input sample_store_csr_read; + input sample_store_csr_write; + input [31:0] sample_store_csr_writedata; + output [31:0] sample_store_csr_readdata; + output sample_store_irq_irq; +endmodule diff --git a/peripherals/adc/adc_inst.v b/peripherals/adc/adc_inst.v new file mode 100644 index 00000000..15ce48b4 --- /dev/null +++ b/peripherals/adc/adc_inst.v @@ -0,0 +1,18 @@ + adc u0 ( + .clock_clk (), // clock.clk + .reset_sink_reset_n (), // reset_sink.reset_n + .adc_pll_clock_clk (), // adc_pll_clock.clk + .adc_pll_locked_export (), // adc_pll_locked.export + .sequencer_csr_address (), // sequencer_csr.address + .sequencer_csr_read (), // .read + .sequencer_csr_write (), // .write + .sequencer_csr_writedata (), // .writedata + .sequencer_csr_readdata (), // .readdata + .sample_store_csr_address (), // sample_store_csr.address + .sample_store_csr_read (), // .read + .sample_store_csr_write (), // .write + .sample_store_csr_writedata (), // .writedata + .sample_store_csr_readdata (), // .readdata + .sample_store_irq_irq () // sample_store_irq.irq + ); + diff --git a/peripherals/adc/adc_inst.vhd b/peripherals/adc/adc_inst.vhd new file mode 100644 index 00000000..44a688ad --- /dev/null +++ b/peripherals/adc/adc_inst.vhd @@ -0,0 +1,39 @@ + component adc is + port ( + clock_clk : in std_logic := 'X'; -- clk + reset_sink_reset_n : in std_logic := 'X'; -- reset_n + adc_pll_clock_clk : in std_logic := 'X'; -- clk + adc_pll_locked_export : in std_logic := 'X'; -- export + sequencer_csr_address : in std_logic := 'X'; -- address + sequencer_csr_read : in std_logic := 'X'; -- read + sequencer_csr_write : in std_logic := 'X'; -- write + sequencer_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + sequencer_csr_readdata : out std_logic_vector(31 downto 0); -- readdata + sample_store_csr_address : in std_logic_vector(6 downto 0) := (others => 'X'); -- address + sample_store_csr_read : in std_logic := 'X'; -- read + sample_store_csr_write : in std_logic := 'X'; -- write + sample_store_csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata + sample_store_csr_readdata : out std_logic_vector(31 downto 0); -- readdata + sample_store_irq_irq : out std_logic -- irq + ); + end component adc; + + u0 : component adc + port map ( + clock_clk => CONNECTED_TO_clock_clk, -- clock.clk + reset_sink_reset_n => CONNECTED_TO_reset_sink_reset_n, -- reset_sink.reset_n + adc_pll_clock_clk => CONNECTED_TO_adc_pll_clock_clk, -- adc_pll_clock.clk + adc_pll_locked_export => CONNECTED_TO_adc_pll_locked_export, -- adc_pll_locked.export + sequencer_csr_address => CONNECTED_TO_sequencer_csr_address, -- sequencer_csr.address + sequencer_csr_read => CONNECTED_TO_sequencer_csr_read, -- .read + sequencer_csr_write => CONNECTED_TO_sequencer_csr_write, -- .write + sequencer_csr_writedata => CONNECTED_TO_sequencer_csr_writedata, -- .writedata + sequencer_csr_readdata => CONNECTED_TO_sequencer_csr_readdata, -- .readdata + sample_store_csr_address => CONNECTED_TO_sample_store_csr_address, -- sample_store_csr.address + sample_store_csr_read => CONNECTED_TO_sample_store_csr_read, -- .read + sample_store_csr_write => CONNECTED_TO_sample_store_csr_write, -- .write + sample_store_csr_writedata => CONNECTED_TO_sample_store_csr_writedata, -- .writedata + sample_store_csr_readdata => CONNECTED_TO_sample_store_csr_readdata, -- .readdata + sample_store_irq_irq => CONNECTED_TO_sample_store_irq_irq -- sample_store_irq.irq + ); + diff --git a/peripherals/adc/adc_qsys.qsys b/peripherals/adc/adc_qsys.qsys new file mode 100644 index 00000000..8c1fb227 --- /dev/null +++ b/peripherals/adc/adc_qsys.qsys @@ -0,0 +1,511 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 5 CT#PORT_LOCKED PORT_USED + altpll_avalon_elaboration + altpll_avalon_post_edit + IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0} + + IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 + MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 + PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 10.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 7 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 0.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 10.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1413286123367447.mif PT#ACTIVECLK_CHECK 0 + UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/peripherals/adc/adc_qsys.sopcinfo b/peripherals/adc/adc_qsys.sopcinfo new file mode 100644 index 00000000..924571ac --- /dev/null +++ b/peripherals/adc/adc_qsys.sopcinfo @@ -0,0 +1,5285 @@ + + + + + + + java.lang.Integer + 1561980330 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + 10M50DAF484C7G + false + true + false + true + DEVICE + + + java.lang.String + 7 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + clk + + + java.lang.String + MAX 10 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + embeddedsw.CMacro.CORE_VARIANT + 3 + + + embeddedsw.CMacro.DUAL_ADC_MODE + false + + + embeddedsw.CMacro.IS_THIS_FIRST_OR_SECOND_ADC + 1 + + + embeddedsw.CMacro.PRESCALER_CH16 + 0 + + + embeddedsw.CMacro.PRESCALER_CH8 + 0 + + + embeddedsw.CMacro.REFSEL + External VREF + + + embeddedsw.CMacro.USE_CH0 + 0 + + + embeddedsw.CMacro.USE_CH1 + 1 + + + embeddedsw.CMacro.USE_CH10 + 1 + + + embeddedsw.CMacro.USE_CH11 + 1 + + + embeddedsw.CMacro.USE_CH12 + 1 + + + embeddedsw.CMacro.USE_CH13 + 1 + + + embeddedsw.CMacro.USE_CH14 + 1 + + + embeddedsw.CMacro.USE_CH15 + 1 + + + embeddedsw.CMacro.USE_CH16 + 1 + + + embeddedsw.CMacro.USE_CH2 + 1 + + + embeddedsw.CMacro.USE_CH3 + 1 + + + embeddedsw.CMacro.USE_CH4 + 1 + + + embeddedsw.CMacro.USE_CH5 + 1 + + + embeddedsw.CMacro.USE_CH6 + 1 + + + embeddedsw.CMacro.USE_CH7 + 0 + + + embeddedsw.CMacro.USE_CH8 + 0 + + + embeddedsw.CMacro.USE_CH9 + 1 + + + embeddedsw.CMacro.USE_TSD + 1 + + + embeddedsw.CMacro.VREF + 2.5 + + + embeddedsw.dts.compatible + altr,modular-adc-1.0 + + + embeddedsw.dts.group + adc + + + embeddedsw.dts.name + modular-adc + + + embeddedsw.dts.params.altr,adc-mode + 1 + + + embeddedsw.dts.params.altr,adc-number + 1 + + + embeddedsw.dts.params.altr,adc-slot-count + 8 + + + embeddedsw.dts.vendor + altr + + + int + 3 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 12 + false + true + false + true + + + long + 50000000 + false + true + false + true + CLOCK_RATE + clock + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + 10M50DAF484C7G + false + true + false + true + DEVICE + + + java.lang.String + 10M50 + true + true + false + true + + + int + 33 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 2 + true + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + true + true + false + true + + + java.math.BigInteger + 0 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + false + true + true + true + + + int + 2 + false + true + true + true + + + int + 2 + true + true + false + true + + + int + 1 + true + true + false + true + + + int + 1 + false + true + false + true + + + int + 0 + false + true + true + true + + + double + 2.5 + false + true + true + true + + + double + 3.0 + false + true + false + true + + + double + 2.5 + true + true + false + true + + + double + 2.5 + true + true + false + true + + + int + 65536 + true + true + false + true + + + int + 0 + true + true + false + true + + + int + 0 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + int + 125 + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + true + false + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + true + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + boolean + false + false + true + true + true + + + double + 0.0 + false + true + false + true + + + java.lang.String + + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 2 + false + true + false + true + + + int + 3 + false + true + false + true + + + int + 4 + false + true + false + true + + + int + 5 + false + true + false + true + + + int + 6 + false + true + false + true + + + int + 7 + false + true + false + true + + + int + 8 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + int + 30 + false + true + false + true + + + java.lang.String + 7 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clock_clk + Input + 1 + clk + + + + + + java.lang.String + clock + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_sink_reset_n + Input + 1 + reset_n + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + adc_pll_clock_clk + Input + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + adc_pll_locked_export + Input + 1 + export + + + + + + java.lang.String + clock + false + true + false + true + + + java.lang.String + reset_sink + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 31 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + command_valid + Input + 1 + valid + + + command_channel + Input + 5 + channel + + + command_startofpacket + Input + 1 + startofpacket + + + command_endofpacket + Input + 1 + endofpacket + + + command_ready + Output + 1 + ready + + + + + + java.lang.String + clock + false + true + false + true + + + java.lang.String + reset_sink + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 12 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 31 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + response_valid + Output + 1 + valid + + + response_channel + Output + 5 + channel + + + response_data + Output + 12 + data + + + response_startofpacket + Output + 1 + startofpacket + + + response_endofpacket + Output + 1 + endofpacket + + + + + + + java.lang.String + altpll_avalon_elaboration + false + true + false + true + + + java.lang.String + altpll_avalon_post_edit + false + true + false + true + + + java.lang.String + MAX 10 + false + true + true + true + + + java.lang.String + 5 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 20000 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + NORMAL + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + CLK0 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + AUTO + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 1 + false + true + true + true + + + java.lang.String + 5 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + java.lang.String + 0 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + 50 + false + true + true + true + + + java.lang.String + 50 + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_USED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + PORT_UNUSED + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + NO + false + true + true + true + + + java.lang.String + CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_USED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 1 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#CLK1_DUTY_CYCLE 50 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#CLK1_MULTIPLY_BY 1 CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#CLK1_PHASE_SHIFT 0 CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {MAX 10} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#CLK1_DIVIDE_BY 5 CT#PORT_LOCKED PORT_USED + false + true + false + true + + + java.lang.String + PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT1 MHz PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK1 1 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT1 deg PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#OUTPUT_FREQ_MODE1 1 PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ1 10.00000000 PT#OUTPUT_FREQ0 50.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE 7 PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT1 0.00000000 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR1 1 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA1 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE1 10.000000 PT#EFF_OUTPUT_FREQ_VALUE0 50.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK1 1 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK1 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT1 deg PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR1 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE1 50.00000000 PT#INTENDED_DEVICE_FAMILY {MAX 10} PT#DUTY_CYCLE0 50.00000000 PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1413286123367447.mif PT#ACTIVECLK_CHECK 0 + false + true + false + true + + + java.lang.String + UP#locked used UP#c1 used UP#c0 used UP#areset used UP#inclk0 used + false + true + false + true + + + java.lang.String + IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#CLK1_MULTIPLY_BY 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#CLK1_DUTY_CYCLE 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR1 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR1 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1 IN#CLK1_DIVIDE_BY 1 + false + true + false + true + + + java.lang.String + MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1 + false + true + false + true + + + java.lang.String + IF#phasecounterselect {input 3} IF#locked {output 0} IF#reset {input 0} IF#clk {input 0} IF#phaseupdown {input 0} IF#scandone {output 0} IF#readdata {output 32} IF#write {input 0} IF#scanclk {input 0} IF#phasedone {output 0} IF#c4 {output 0} IF#c3 {output 0} IF#address {input 2} IF#c2 {output 0} IF#c1 {output 0} IF#c0 {output 0} IF#writedata {input 32} IF#read {input 0} IF#areset {input 0} IF#scanclkena {input 0} IF#scandataout {output 0} IF#configupdate {input 0} IF#phasestep {input 0} IF#scandata {input 0} + false + true + false + true + + + java.lang.String + 0 + false + true + false + true + + + java.lang.String + MAX10FPGA + false + true + false + true + DEVICE_FAMILY + + + java.lang.Long + 50000000 + false + true + false + true + CLOCK_RATE + inclk_interface + + + java.lang.String + MAX 10 + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + inclk_interface + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + embeddedsw.configuration.isMemoryDevice + false + + + embeddedsw.configuration.isNonVolatileStorage + false + + + embeddedsw.configuration.isPrintableDevice + false + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 16 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + inclk_interface + false + true + true + true + + + java.lang.String + inclk_interface_reset + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + read + Input + 1 + read + + + write + Input + 1 + write + + + address + Input + 2 + address + + + readdata + Output + 32 + readdata + + + writedata + Input + 32 + writedata + + + + + + java.lang.String + + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + c0 + Output + 1 + clk + + + false + adc_0 + clock + adc_0.clock + + + false + clock_bridge_sys + in_clk + clock_bridge_sys.in_clk + + + + + + java.lang.String + + false + true + true + true + + + long + 10000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + c1 + Output + 1 + clk + + + false + adc_0 + adc_pll_clock + adc_0.adc_pll_clock + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + areset + Input + 1 + export + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + locked + Output + 1 + export + + + + + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + CLOCK_RATE + clk_in + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + false + altpll_sys + inclk_interface + altpll_sys.inclk_interface + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + long + 50000000 + false + true + true + true + CLOCK_RATE + in_clk + + + long + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + java.lang.String + in_clk + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + out_clk + Output + 1 + clk + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + altpll_sys + c0 + adc_0 + clock + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + altpll_sys + c0 + clock_bridge_sys + in_clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + altpll_sys + c1 + adc_0 + adc_pll_clock + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_50 + clk + altpll_sys + inclk_interface + + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + com.altera.entityinterfaces.IPort + + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + altpll_sys + locked_conduit + adc_0 + adc_pll_locked + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_50 + clk_reset + altpll_sys + inclk_interface_reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_50 + clk_reset + adc_0 + reset_sink + + + 1 + altera_modular_adc + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Modular ADC core Intel FPGA IP + 18.1 + + + 4 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 18.1 + + + 2 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 18.1 + + + 3 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 18.1 + + + 1 + avalon_streaming_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Sink + 18.1 + + + 1 + avalon_streaming_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source + 18.1 + + + 1 + altpll + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + ALTPLL Intel FPGA IP + 18.1 + + + 1 + avalon_slave + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Memory Mapped Slave + 18.1 + + + 3 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 18.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 18.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 18.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 18.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 18.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 18.1 + + + 1 + altera_clock_bridge + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Bridge + 18.1 + + + 4 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 18.1 + + + 1 + conduit + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Conduit Connection + 18.1 + + + 2 + reset + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Reset Connection + 18.1 + + 18.1 625 + + diff --git a/peripherals/adc/de10_lite.vhd b/peripherals/adc/de10_lite.vhd new file mode 100644 index 00000000..3f48e8f4 --- /dev/null +++ b/peripherals/adc/de10_lite.vhd @@ -0,0 +1,381 @@ +------------------------------------------------------------------- +-- Name : de0_lite.vhd +-- Author : Renan Augusto Starke +-- Modified : Jeferson Pedroso +-- Version : 0.1 +-- Copyright : Departamento de Eletrônica, Florianópolis, IFSC +-- Description : riscV ADC example +------------------------------------------------------------------- +LIBRARY ieee; +USE IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +use work.decoder_types.all; + +entity de10_lite is + generic ( + --! Num of 32-bits memory words + IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes + DMEMORY_WORDS : integer := 1024 --!= 2k (512 * 2) bytes + ); + + + port ( + ---------- CLOCK ---------- + ADC_CLK_10: in std_logic; + MAX10_CLK1_50: in std_logic; + MAX10_CLK2_50: in std_logic; + + ----------- SDRAM ------------ + DRAM_ADDR: out std_logic_vector (12 downto 0); + DRAM_BA: out std_logic_vector (1 downto 0); + DRAM_CAS_N: out std_logic; + DRAM_CKE: out std_logic; + DRAM_CLK: out std_logic; + DRAM_CS_N: out std_logic; + DRAM_DQ: inout std_logic_vector(15 downto 0); + DRAM_LDQM: out std_logic; + DRAM_RAS_N: out std_logic; + DRAM_UDQM: out std_logic; + DRAM_WE_N: out std_logic; + + ----------- SEG7 ------------ + HEX0: out std_logic_vector(7 downto 0); + HEX1: out std_logic_vector(7 downto 0); + HEX2: out std_logic_vector(7 downto 0); + HEX3: out std_logic_vector(7 downto 0); + HEX4: out std_logic_vector(7 downto 0); + HEX5: out std_logic_vector(7 downto 0); + + ----------- KEY ------------ + KEY: in std_logic_vector(1 downto 0); + + ----------- LED ------------ + LEDR: out std_logic_vector(9 downto 0); + + ----------- SW ------------ + SW: in std_logic_vector(9 downto 0); + + ----------- VGA ------------ + VGA_B: out std_logic_vector(3 downto 0); + VGA_G: out std_logic_vector(3 downto 0); + VGA_HS: out std_logic; + VGA_R: out std_logic_vector(3 downto 0); + VGA_VS: out std_logic; + + ----------- Accelerometer ------------ + GSENSOR_CS_N: out std_logic; + GSENSOR_INT: in std_logic_vector(2 downto 1); + GSENSOR_SCLK: out std_logic; + GSENSOR_SDI: inout std_logic; + GSENSOR_SDO: inout std_logic; + + ----------- Arduino ------------ + ARDUINO_IO: inout std_logic_vector(15 downto 0); + ARDUINO_RESET_N: inout std_logic + ); +end entity; + + + +architecture rtl of de10_lite is + + signal clk : std_logic; + signal rst : std_logic; + + -- Instruction bus signals + signal idata : std_logic_vector(31 downto 0); + signal iaddress : integer range 0 to IMEMORY_WORDS-1 := 0; + signal address : std_logic_vector (9 downto 0); + + -- Data bus signals + signal daddress : integer range 0 to DMEMORY_WORDS-1; + signal ddata_r : std_logic_vector(31 downto 0); + signal ddata_w : std_logic_vector(31 downto 0); + signal dmask : std_logic_vector(3 downto 0); + signal dcsel : std_logic_vector(1 downto 0); + signal d_we : std_logic := '0'; + + signal ddata_r_mem : std_logic_vector(31 downto 0); + signal d_rd : std_logic; + + -- I/O signals + signal input_in : std_logic_vector(31 downto 0); + + -- PLL signals + signal locked_sig : std_logic; + + -- CPU state signals + signal state : cpu_state_t; + + + --===================================================== + --DECLARACAO COMPONENTE ADC + ------------------------------------------------------- + -- qsys MAX10 ADC component + component adc_qsys is + port( + clk_clk : in std_logic := 'X'; -- clk + clock_bridge_sys_out_clk_clk : out std_logic; -- clk + modular_adc_0_command_valid : in std_logic := 'X'; -- valid + modular_adc_0_command_channel : in std_logic_vector(4 downto 0) := (others => 'X'); -- channel + modular_adc_0_command_startofpacket : in std_logic := 'X'; -- startofpacket + modular_adc_0_command_endofpacket : in std_logic := 'X'; -- endofpacket + modular_adc_0_command_ready : out std_logic; -- ready + modular_adc_0_response_valid : out std_logic; -- valid + modular_adc_0_response_channel : out std_logic_vector(4 downto 0); -- channel + modular_adc_0_response_data : out std_logic_vector(11 downto 0); -- data + modular_adc_0_response_startofpacket : out std_logic; -- startofpacket + modular_adc_0_response_endofpacket : out std_logic; -- endofpacket + reset_reset_n : in std_logic := 'X' -- reset_n + ); + end component adc_qsys; + + --===================================================== + --DECLARACAO DISPLAY COMPONENTE + ------------------------------------------------------- + + component display_dec is + port( + hex : in std_logic_vector(3 downto 0); + dot : in std_logic; + disp : out std_logic_vector(7 downto 0) + ); + end component display_dec; + + type displays_type is array (0 to 5) of std_logic_vector(3 downto 0); + type displays_out_type is array (0 to 5) of std_logic_vector(7 downto 0); + + signal displays : displays_type; + signal displays_out : displays_out_type; + + --======================================================= + --SINAIS PARA adc_max + --======================================================= + + signal adc_out_clk : std_logic; + signal command_valid : std_logic; + signal command_channel : std_logic_vector(4 downto 0); + signal command_startofpacket : std_logic; + signal command_endofpacket : std_logic; + signal command_ready : std_logic; + signal response_valid : std_logic; + signal response_channel : std_logic_vector(4 downto 0); + signal response_data : std_logic_vector(11 downto 0); + signal response_startofpacket : std_logic; + signal response_endofpacket : std_logic; + + signal adc_sample_data : std_logic_vector(11 downto 0); + signal cur_adc_ch : std_logic_vector(4 downto 0); + signal reset : std_logic; + signal reset_n : std_logic; + + +begin + + --======================================================= + --GENERATE DISPLAYS + --======================================================= + + hex_gen : for i in 0 to 5 generate + hex_dec : display_dec + port map( + hex => displays(i), + dot => '0', + disp => displays_out(i) + ); + end generate; + + HEX0 <= displays_out(0); + HEX1 <= displays_out(1); + HEX2 <= displays_out(2); + HEX3 <= displays_out(3); + HEX4 <= displays_out(4); + HEX5 <= displays_out(5); + + --===================================================== + --PORTMAP ADC + ------------------------------------------------------- + u0 : component adc_qsys + port map( + clk_clk => MAX10_CLK1_50, + clock_bridge_sys_out_clk_clk => adc_out_clk, + modular_adc_0_command_valid => command_valid, + modular_adc_0_command_channel => command_channel, + modular_adc_0_command_startofpacket => command_startofpacket, + modular_adc_0_command_endofpacket => command_endofpacket, + modular_adc_0_command_ready => command_ready, + modular_adc_0_response_valid => response_valid, + modular_adc_0_response_channel => response_channel, + modular_adc_0_response_data => response_data, + modular_adc_0_response_startofpacket => response_startofpacket, + modular_adc_0_response_endofpacket => response_endofpacket, + reset_reset_n => reset_n --reset_n + ); + + --===================================================== + command_startofpacket <= '1'; + command_endofpacket <= '1'; + command_valid <= '1'; + + reset <= SW(8); --sw(9) e reset do ADC + reset_n <= not reset; + LEDR(8) <= reset; + + --===================================================== + --process para ler adc + --===================================================== + + process(adc_out_clk, reset) --adc_out_clk + begin + if reset = '1' then + adc_sample_data <= (others => '0'); + cur_adc_ch <= (others => '0'); + else + if (rising_edge(adc_out_clk) and response_valid = '1') then --adc_out_clk + adc_sample_data <= response_data; + cur_adc_ch <= response_channel; + end if; + end if; + end process; + + --===================================================== + + pll_inst: entity work.pll_quartus + port map( + areset => '0', + inclk0 => MAX10_CLK1_50, + c0 => clk, + locked => locked_sig + ); + + rst <= SW(9); + + -- Dummy out signals + DRAM_DQ <= ddata_r(15 downto 0); + ARDUINO_IO <= ddata_r(31 downto 16); + LEDR(9) <= SW(9); + DRAM_ADDR(9 downto 0) <= address; + + -- IMem shoud be read from instruction and data buses + -- Not enough RAM ports for instruction bus, data bus and in-circuit programming + process(d_rd, dcsel, daddress, iaddress) + begin + if (d_rd = '1') and (dcsel = "00") then + address <= std_logic_vector(to_unsigned(daddress,10)); + else + address <= std_logic_vector(to_unsigned(iaddress,10)); + end if; + end process; + + -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor + iram_quartus_inst: entity work.iram_quartus + port map( + address => address, + byteena => "1111", + clock => clk, + data => (others => '0'), + wren => '0', + q => idata + ); + + -- Data Memory RAM + dmem: entity work.dmemory + generic map( + MEMORY_WORDS => DMEMORY_WORDS + ) + port map( + rst => rst, + clk => clk, + data => ddata_w, + address => daddress, + we => d_we, + csel => dcsel(0), + dmask => dmask, + q => ddata_r_mem + ); + + -- Adress space mux ((check sections.ld) -> Data chip select: + -- 0x00000 -> Instruction memory + -- 0x20000 -> Data memory + -- 0x40000 -> Input/Output generic address space + with dcsel select + ddata_r <= idata when "00", + ddata_r_mem when "01", + input_in when "10", + (others => '0') when others; + + -- Softcore instatiation + myRisc: entity work.core + generic map( + IMEMORY_WORDS => IMEMORY_WORDS, + DMEMORY_WORDS => DMEMORY_WORDS + ) + port map( + clk => clk, + rst => rst, + iaddress => iaddress, + idata => idata, + daddress => daddress, + ddata_r => ddata_r, + ddata_w => ddata_w, + d_we => d_we, + d_rd => d_rd, + dcsel => dcsel, + dmask => dmask, + state => state + ); + + -- Output register (Dummy LED blinky) + process(clk, rst) + begin + if rst = '1' then + LEDR(3 downto 0) <= (others => '0'); + + else + if rising_edge(clk) then + if (d_we = '1') and (dcsel = "10")then + -- ToDo: Simplify compartors + -- ToDo: Maybe use byte addressing? + -- x"01" (word addressing) is x"04" (byte addressing) + if to_unsigned(daddress, 32)(8 downto 0) = x"01" then -- LEDS + LEDR(7 downto 0) <= ddata_w(7 downto 0); + elsif to_unsigned(daddress, 32)(8 downto 0) = x"02" then --OUT_SEGS + displays(0) <= ddata_w(3 downto 0); + displays(1) <= ddata_w(7 downto 4); + displays(2) <= ddata_w(11 downto 8); + displays(3) <= ddata_w(15 downto 12); + displays(4) <= ddata_w(19 downto 16); + displays(5) <= ddata_w(23 downto 20); + + elsif to_unsigned(daddress, 32)(8 downto 0) = x"06" then --CH_ADC_FEED + + elsif to_unsigned(daddress, 32)(8 downto 0) = x"07" then --SEL_CH_ADC + command_channel <= ddata_w(4 downto 0); + + end if; + end if; + end if; + end if; + end process; + + + -- Input register + process(clk, rst) + begin + if rst = '1' then + input_in <= (others => '0'); + else + if rising_edge(clk) then + if (d_rd = '1') and (dcsel = "10") then +-- input_in(8 downto 0) <= SW(8 downto 0); + input_in(11 downto 0) <= adc_sample_data; + input_in(15 downto 12) <= cur_adc_ch(3 downto 0); + + end if; + end if; + end if; + end process; + + +end; diff --git a/peripherals/adc/pll/pll_quartus.cmp b/peripherals/adc/pll/pll_quartus.cmp new file mode 100644 index 00000000..9849212e --- /dev/null +++ b/peripherals/adc/pll/pll_quartus.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +component pll_quartus + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/peripherals/adc/pll/pll_quartus.ppf b/peripherals/adc/pll/pll_quartus.ppf new file mode 100644 index 00000000..4d68e582 --- /dev/null +++ b/peripherals/adc/pll/pll_quartus.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/peripherals/adc/pll/pll_quartus.qip b/peripherals/adc/pll/pll_quartus.qip new file mode 100644 index 00000000..bfd6a0e7 --- /dev/null +++ b/peripherals/adc/pll/pll_quartus.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_quartus.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus_inst.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus.ppf"] diff --git a/peripherals/adc/pll/pll_quartus.vhd b/peripherals/adc/pll/pll_quartus.vhd new file mode 100644 index 00000000..61e5a753 --- /dev/null +++ b/peripherals/adc/pll/pll_quartus.vhd @@ -0,0 +1,399 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll_quartus.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 18.1.0 Build 625 09/12/2018 SJ Standard Edition +-- ************************************************************ + + +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll_quartus IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll_quartus; + + +ARCHITECTURE SYN OF pll_quartus IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + locked <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 50, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + clk1_divide_by => 15625, + clk1_duty_cycle => 50, + clk1_multiply_by => 3, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "MAX 10", + lpm_hint => "CBX_MODULE_PREFIX=pll_quartus", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire5, + clk => sub_wire0, + locked => sub_wire3 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "50" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.009600" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.00960000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_quartus.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "15625" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus_inst.vhd TRUE +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/peripherals/adc/pll/pll_quartus_inst.vhd b/peripherals/adc/pll/pll_quartus_inst.vhd new file mode 100644 index 00000000..bee5a286 --- /dev/null +++ b/peripherals/adc/pll/pll_quartus_inst.vhd @@ -0,0 +1,7 @@ +pll_quartus_inst : pll_quartus PORT MAP ( + areset => areset_sig, + inclk0 => inclk0_sig, + c0 => c0_sig, + c1 => c1_sig, + locked => locked_sig + ); diff --git a/peripherals/adc/sint/de10_lite.ipregen.rpt b/peripherals/adc/sint/de10_lite.ipregen.rpt new file mode 100644 index 00000000..72188105 --- /dev/null +++ b/peripherals/adc/sint/de10_lite.ipregen.rpt @@ -0,0 +1,68 @@ +IP Upgrade report for de10_lite +Mon Jul 8 08:47:25 2019 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. IP Upgrade Summary + 3. Successfully Upgraded IP Components + 4. IP Upgrade Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------+ +; IP Upgrade Summary ; ++------------------------------+-------------------------------------------------+ +; IP Components Upgrade Status ; Passed - Mon Jul 8 08:47:25 2019 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; de10_lite ; +; Top-level Entity Name ; de0_lite ; +; Family ; MAX 10 ; ++------------------------------+-------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Successfully Upgraded IP Components ; ++-------------+----------------+---------+------------------------+------------------------+------------------------+---------+ +; Entity Name ; Component Name ; Version ; Original Source File ; Generation File Path ; New Source File ; Message ; ++-------------+----------------+---------+------------------------+------------------------+------------------------+---------+ +; pll_quartus ; ALTPLL ; 17.1 ; ../pll/pll_quartus.qip ; ../pll/pll_quartus.vhd ; ../pll/pll_quartus.qip ; ; ++-------------+----------------+---------+------------------------+------------------------+------------------------+---------+ + + ++---------------------+ +; IP Upgrade Messages ; ++---------------------+ +Info (11902): Backing up file "../pll/pll_quartus.vhd" to "../pll/pll_quartus.BAK.vhd" +Info (11837): Started upgrading IP component ALTPLL with file "../pll/pll_quartus.vhd" +Info (11131): Completed upgrading IP component ALTPLL with file "../pll/pll_quartus.vhd" +Info (23030): Evaluation of Tcl script /home/xtarke/Data/Apps/intelFPGA/18.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful +Info: Quartus Prime Shell was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 1065 megabytes + Info: Processing ended: Mon Jul 8 08:47:25 2019 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:28 + + diff --git a/peripherals/adc/sint/de10_lite.qpf b/peripherals/adc/sint/de10_lite.qpf new file mode 100644 index 00000000..2e37e9d1 --- /dev/null +++ b/peripherals/adc/sint/de10_lite.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition +# Date created = 18:49:34 June 20, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.0" +DATE = "18:49:34 June 20, 2019" + +# Revisions + +PROJECT_REVISION = "de10_lite" diff --git a/peripherals/adc/sint/de10_lite.qsf b/peripherals/adc/sint/de10_lite.qsf new file mode 100644 index 00000000..ef9389b1 --- /dev/null +++ b/peripherals/adc/sint/de10_lite.qsf @@ -0,0 +1,235 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition +# Date created = 18:49:34 June 20, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# de10_lite_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:49:34 JUNE 20, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name ENABLE_OCT_DONE ON +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name QSYS_FILE ../adc_qsys.qsys +set_global_assignment -name VHDL_FILE ../../disp7seg/display_dec.vhd +set_global_assignment -name SDC_FILE de10_lite.sdc +set_global_assignment -name VHDL_FILE ../uart.vhd +set_global_assignment -name QIP_FILE ../pll/pll_quartus.qip +set_global_assignment -name VHDL_FILE ../../../alu/alu_types.vhd +set_global_assignment -name VHDL_FILE ../../../alu/alu.vhd +set_global_assignment -name VHDL_FILE ../de10_lite.vhd +set_global_assignment -name VHDL_FILE ../../../alu/m/M_types.vhd +set_global_assignment -name VHDL_FILE ../../../alu/m/M.vhd +set_global_assignment -name VHDL_FILE ../../../memory/dmemory.vhd +set_global_assignment -name VHDL_FILE ../../../memory/iram_quartus.vhd +set_global_assignment -name QIP_FILE ../../../memory/iram_quartus.qip +set_global_assignment -name VHDL_FILE ../../../decoder/iregister.vhd +set_global_assignment -name VHDL_FILE ../../../decoder/decoder_types.vhd +set_global_assignment -name VHDL_FILE ../../../decoder/decoder.vhd +set_global_assignment -name VHDL_FILE ../../../core/core.vhd +set_global_assignment -name VHDL_FILE ../../../registers/register_file.vhd + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/peripherals/adc/sint/de10_lite.sdc b/peripherals/adc/sint/de10_lite.sdc new file mode 100644 index 00000000..7267c16e --- /dev/null +++ b/peripherals/adc/sint/de10_lite.sdc @@ -0,0 +1,86 @@ +#************************************************************** +# This .sdc file is created by Terasic Tool. +# Users are recommended to modify this file to match users logic. +#************************************************************** + +#************************************************************** +# Create Clock +#************************************************************** +create_clock -period "10.0 MHz" [get_ports ADC_CLK_10] +create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50] +create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50] + +#************************************************************** +# Create Generated Clock +#************************************************************** +derive_pll_clocks + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** +derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + + + +#************************************************************** +# Set Load +#************************************************************** + + + diff --git a/peripherals/adc/sint/de10_lite_assignment_defaults.qdf b/peripherals/adc/sint/de10_lite_assignment_defaults.qdf new file mode 100644 index 00000000..d40b50e3 --- /dev/null +++ b/peripherals/adc/sint/de10_lite_assignment_defaults.qdf @@ -0,0 +1,807 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# Date created = 08:39:22 July 08, 2019 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY -value "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/peripherals/adc/sint/de10_lite_description.txt b/peripherals/adc/sint/de10_lite_description.txt new file mode 100644 index 00000000..e69de29b diff --git a/peripherals/disp7seg/display_dec.vhd b/peripherals/disp7seg/display_dec.vhd new file mode 100644 index 00000000..538f76b3 --- /dev/null +++ b/peripherals/disp7seg/display_dec.vhd @@ -0,0 +1,40 @@ +------------------------------------------------------------------- +-- Name : decoder.vhd +-- Author : Renan Augusto Starke +------------------------------------------------------------------- + +-- Bibliotecas +library ieee; +use ieee.std_logic_1164.all; + +------------------------------------- +entity display_dec is + port + ( + data_in : in std_logic_vector(3 downto 0); + disp : out std_logic_vector(7 downto 0) + ); +end entity display_dec; +------------------------------ + +architecture behaviour of display_dec is + +begin + disp <= "11000000" when data_in = x"0" else + "11111001" when data_in = x"1" else + "10100100" when data_in = x"2" else + "10110000" when data_in = x"3" else + "10011001" when data_in = x"4" else + "10010010" when data_in = x"5" else + "10000010" when data_in = x"6" else + "11111000" when data_in = x"7" else + "10000000" when data_in = x"8" else + "10010000" when data_in = x"9" else + "10001000" when data_in = x"A" else + "10000011" when data_in = x"B" else + "10100111" when data_in = x"C" else + "10100001" when data_in = x"D" else + "10000110" when data_in = x"E" else + "10001110"; -- x"F" + +end architecture behaviour; diff --git a/peripherals/sdram/README.md b/peripherals/sdram/README.md new file mode 100644 index 00000000..a56f618b --- /dev/null +++ b/peripherals/sdram/README.md @@ -0,0 +1,20 @@ +# Memória SDRAM + +Este é um controlador para a memória SDRAM IS42S16320D-7TL. + +[Datasheet da SDRAM](http://www.issi.com/WW/pdf/42-45R-S_86400D-16320D-32160D.pdf) + +## Como fazer funcionar + +Este diretório possui os seguintes arquivos: +* sdram_controller.vhd: Arquivo principal do controlador. +* testbench_sdram.vhd: Arquivo de testbench para o controlador. +* testbench_sdtam.do: Script para simulação no ModelSim. + +Além destes arquivos, o diretório possui uma pasta `sim/` com modelos comportamental de uma memória SDRAM. + +Para utilizar o controlador é apenas necessário adicionar o arquivo sdram_controller.vhd no projeto e instanciá-lo. + +## Problemas + +* Este controlador consegue ler e escrever na memória SDRAM porém o valor escrita fica na memória por apenas um pequeno período de tempo. \ No newline at end of file diff --git a/peripherals/sdram/de10_lite.vhd b/peripherals/sdram/de10_lite.vhd new file mode 100644 index 00000000..1ea08c8e --- /dev/null +++ b/peripherals/sdram/de10_lite.vhd @@ -0,0 +1,371 @@ +------------------------------------------------------------------- +-- Name : de0_lite.vhd +-- Author : +-- Version : 0.1 +-- Copyright : Departamento de Eletrônica, Florianópolis, IFSC +-- Description : Projeto base DE10-Lite +------------------------------------------------------------------- +LIBRARY ieee; +USE IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +use work.decoder_types.all; + +entity de10_lite is + generic( + --! Num of 32-bits memory words + IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes + DMEMORY_WORDS : integer := 1024 --!= 2k (512 * 2) bytes + ); + + port( + ---------- CLOCK ---------- + ADC_CLK_10 : in std_logic; + MAX10_CLK1_50 : in std_logic; + MAX10_CLK2_50 : in std_logic; + ----------- SDRAM ------------ + DRAM_ADDR : out std_logic_vector(12 downto 0); + DRAM_BA : out std_logic_vector(1 downto 0); + DRAM_CAS_N : out std_logic; + DRAM_CKE : out std_logic; + DRAM_CLK : out std_logic; + DRAM_CS_N : out std_logic; + DRAM_DQ : inout std_logic_vector(15 downto 0); + DRAM_LDQM : out std_logic; + DRAM_RAS_N : out std_logic; + DRAM_UDQM : out std_logic; + DRAM_WE_N : out std_logic; + ----------- SEG7 ------------ + HEX0 : out std_logic_vector(7 downto 0); + HEX1 : out std_logic_vector(7 downto 0); + HEX2 : out std_logic_vector(7 downto 0); + HEX3 : out std_logic_vector(7 downto 0); + HEX4 : out std_logic_vector(7 downto 0); + HEX5 : out std_logic_vector(7 downto 0); + ----------- KEY ------------ + KEY : in std_logic_vector(1 downto 0); + ----------- LED ------------ + LEDR : out std_logic_vector(9 downto 0); + ----------- SW ------------ + SW : in std_logic_vector(9 downto 0); + ----------- VGA ------------ + VGA_B : out std_logic_vector(3 downto 0); + VGA_G : out std_logic_vector(3 downto 0); + VGA_HS : out std_logic; + VGA_R : out std_logic_vector(3 downto 0); + VGA_VS : out std_logic; + ----------- Accelerometer ------------ + GSENSOR_CS_N : out std_logic; + GSENSOR_INT : in std_logic_vector(2 downto 1); + GSENSOR_SCLK : out std_logic; + GSENSOR_SDI : inout std_logic; + GSENSOR_SDO : inout std_logic; + ----------- Arduino ------------ + ARDUINO_IO : inout std_logic_vector(15 downto 0); + ARDUINO_RESET_N : inout std_logic + ); +end entity; + +architecture rtl of de10_lite is + + signal clk : std_logic; + signal clk_sdram_ctrl : std_logic; + signal clk_sdram_chip : std_logic; + signal clk_vga : std_logic; + + signal rst : std_logic; + signal rst_n : std_logic; + + -- Instruction bus signals + signal idata : std_logic_vector(31 downto 0); + signal iaddress : integer range 0 to IMEMORY_WORDS - 1 := 0; + signal address : std_logic_vector(9 downto 0); + + -- Data bus signals + signal daddress : natural; + signal ddata_r : std_logic_vector(31 downto 0); + signal ddata_w : std_logic_vector(31 downto 0); + signal dmask : std_logic_vector(3 downto 0); + signal dcsel : std_logic_vector(1 downto 0); + signal d_we : std_logic := '0'; + + signal ddata_r_mem : std_logic_vector(31 downto 0); + signal d_rd : std_logic; + + signal dmemory_address : natural; + + -- I/O signals + signal input_in : std_logic_vector(31 downto 0); + + -- PLL signals + signal locked_sig : std_logic; + + -- CPU state signals + signal state : cpu_state_t; + + -- SDRAM signals + signal daddress_to_sdram : std_logic_vector(31 downto 0); + signal sdram_addr : std_logic_vector(31 downto 0); + signal chipselect_sdram : std_logic; + signal sdram_d_rd : std_logic; + signal sdram_read : std_logic_vector(15 DOWNTO 0); + signal sdram_read_32 : std_logic_vector(31 downto 0); + signal waitrequest : std_logic; + signal DRAM_DQM : std_logic_vector(1 downto 0); + signal burst : std_logic; + + -- VGA signals + signal vga_addr : std_logic_vector(31 downto 0); + signal disp_ena : std_logic; + signal n_blank : std_logic; + signal n_sync : std_logic; + signal column : integer; + signal row : integer; + signal vga_data_read : std_logic; + signal buffer_to_sdram_addr : std_logic_vector(31 downto 0); + signal VGA_RR : std_logic_vector(3 downto 0); + signal VGA_GG : std_logic_vector(3 downto 0); + signal VGA_BB : std_logic_vector(3 downto 0); + signal chipselect_core : std_logic; + +begin + + pll_inst : entity work.pll + port map( + areset => '0', + inclk0 => MAX10_CLK1_50, + c0 => clk, + c1 => clk_sdram_ctrl, + c2 => clk_vga, + c3 => clk_sdram_chip, + locked => locked_sig + ); + + rst <= SW(9); + rst_n <= SW(8); + + -- Dummy out signals + ARDUINO_IO <= ddata_r(31 downto 16); + LEDR(9) <= SW(9); + + -- IMem shoud be read from instruction and data buses + -- Not enough RAM ports for instruction bus, data bus and in-circuit programming + process(d_rd, dcsel, daddress, iaddress) + begin + if (d_rd = '1') and (dcsel = "00") then + address <= std_logic_vector(to_unsigned(daddress, 10)); + else + address <= std_logic_vector(to_unsigned(iaddress, 10)); + end if; + end process; + + -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor + iram_quartus_inst : entity work.iram_quartus + port map( + address => address(9 downto 0), + byteena => "1111", + clock => clk, + data => (others => '0'), + wren => '0', + q => idata + ); + + dmemory_address <= to_integer(to_unsigned(daddress, 10)); + -- Data Memory RAM + dmem : entity work.dmemory + generic map( + MEMORY_WORDS => DMEMORY_WORDS + ) + port map( + rst => rst, + clk => clk, + data => ddata_w, + address => dmemory_address, + we => d_we, + csel => dcsel(0), + dmask => dmask, + q => ddata_r_mem + ); + + -- Adress space mux ((check sections.ld) -> Data chip select: + -- 0x00000 -> Instruction memory + -- 0x20000 -> Data memory + -- 0x40000 -> Input/Output generic address space + -- 0x60000 -> SDRAM address space + with dcsel select ddata_r <= + idata when "00", + ddata_r_mem when "01", + input_in when "10", + sdram_read_32 when "11",(others => '0') when others; + + -- sdram output is 16 bits while data bus is 32 bits + sdram_read_32 <= x"0000" & sdram_read; + + -- Softcore instatiation + myRisc : entity work.core + generic map( + IMEMORY_WORDS => IMEMORY_WORDS, + DMEMORY_WORDS => DMEMORY_WORDS + ) + port map( + clk => clk, + rst => rst, + iaddress => iaddress, + idata => idata, + daddress => daddress, + ddata_r => ddata_r, + ddata_w => ddata_w, + d_we => d_we, + d_rd => d_rd, + dcsel => dcsel, + dmask => dmask, + state => state + ); + + -- Output register (Dummy LED blinky) + process(clk, rst) + begin + if rst = '1' then + LEDR(3 downto 0) <= (others => '0'); + HEX0 <= (others => '1'); + HEX1 <= (others => '1'); + HEX2 <= (others => '1'); + HEX3 <= (others => '1'); + HEX4 <= (others => '1'); + HEX5 <= (others => '1'); + else + if rising_edge(clk) then + if (d_we = '1') and (dcsel = "10") then + -- ToDo: Simplify compartors + -- ToDo: Maybe use byte addressing? + -- x"01" (word addressing) is x"04" (byte addressing) + if to_unsigned(daddress, 32)(8 downto 0) = x"01" then + LEDR(4 downto 0) <= ddata_w(4 downto 0); + elsif to_unsigned(daddress, 32)(8 downto 0) = x"02" then + HEX0 <= ddata_w(7 downto 0); + HEX1 <= ddata_w(15 downto 8); + HEX2 <= ddata_w(23 downto 16); + HEX3 <= ddata_w(31 downto 24); + -- HEX4 <= ddata_w(7 downto 0); + -- HEX5 <= ddata_w(7 downto 0); + end if; + end if; + end if; + end if; + end process; + + -- Input register + process(clk, rst) + begin + if rst = '1' then + input_in <= (others => '0'); + else + if rising_edge(clk) then + if (d_we = '1') and (dcsel = "10") then + input_in(4 downto 0) <= SW(4 downto 0); + end if; + end if; + end if; + end process; + + -- CORE, VGA and SDRAM muxes + with SW(7) select sdram_addr <= + daddress_to_sdram when '1', + buffer_to_sdram_addr when others; + + with SW(7) select sdram_d_rd <= + d_rd when '1', + vga_data_read when others; + + with SW(7) select chipselect_sdram <= + chipselect_core when '1', + vga_data_read when others; + + with SW(7) select burst <= + '0' when '1', + '1' when others; + + -- SDRAM instatiation + sdram_controller : entity work.sdram_controller + port map( + address => sdram_addr, + byteenable => "11", + chipselect => chipselect_sdram, + clk => clk_sdram_ctrl, + clken => '1', + reset => rst, + reset_req => rst, + write => d_we, + read => sdram_d_rd, + writedata => ddata_w, + burst => burst, + -- outputs: + readdata => sdram_read, + waitrequest => waitrequest, + DRAM_ADDR => DRAM_ADDR, + DRAM_BA => DRAM_BA, + DRAM_CAS_N => DRAM_CAS_N, + DRAM_CKE => DRAM_CKE, + DRAM_CLK => open, + DRAM_CS_N => DRAM_CS_N, + DRAM_DQ => DRAM_DQ, + DRAM_DQM => DRAM_DQM, + DRAM_RAS_N => DRAM_RAS_N, + DRAM_WE_N => DRAM_WE_N + ); + + DRAM_CLK <= clk_sdram_chip; + -- SDRAM Signals + daddress_to_sdram <= std_logic_vector(to_unsigned(daddress, 32)); + DRAM_UDQM <= DRAM_DQM(1); + DRAM_LDQM <= DRAM_DQM(0); + --chipselect_sdram <= dcsel(0) and dcsel(1); + chipselect_core <= dcsel(0) and dcsel(1); + +-- vga_controller : entity work.vga_controller +-- port map( +-- pixel_clk => clk_vga, +-- reset_n => rst_n, +-- h_sync => VGA_HS, +-- v_sync => VGA_VS, +-- disp_ena => disp_ena, +-- column => column, +-- row => row, +-- addr => vga_addr, +-- n_blank => n_blank, +-- n_sync => n_sync +-- ); +-- +-- vga_buffer : entity work.vga_buffer +-- port map( +-- clk => clk_sdram_ctrl, +-- rst => rst, +-- address_vga => vga_addr, +-- sdram_data => sdram_read, +-- sdram_address => buffer_to_sdram_addr, +-- sdram_r => vga_data_read, +-- VGA_R => VGA_RR, +-- VGA_G => VGA_GG, +-- VGA_B => VGA_BB +-- ); + + + PROCESS(disp_ena) + BEGIN + + IF(disp_ena = '1') THEN --display time + VGA_R <= VGA_RR; + VGA_G <= VGA_GG; + VGA_B <= VGA_BB; + ELSE --blanking time + VGA_R <= "0000"; + VGA_G <= "0000"; + VGA_B <= "0000"; + END IF; + + END PROCESS; + + +end; + + diff --git a/peripherals/sdram/pll/pll.ppf b/peripherals/sdram/pll/pll.ppf new file mode 100644 index 00000000..6447543c --- /dev/null +++ b/peripherals/sdram/pll/pll.ppf @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/peripherals/sdram/pll/pll.qip b/peripherals/sdram/pll/pll.qip new file mode 100644 index 00000000..4252c1cd --- /dev/null +++ b/peripherals/sdram/pll/pll.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/peripherals/sdram/pll/pll.vhd b/peripherals/sdram/pll/pll.vhd new file mode 100644 index 00000000..05f5714a --- /dev/null +++ b/peripherals/sdram/pll/pll.vhd @@ -0,0 +1,461 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 18.1.0 Build 625 09/12/2018 SJ Standard Edition +-- ************************************************************ + + +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + c2 : OUT STD_LOGIC ; + c3 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + SIGNAL sub_wire6 : STD_LOGIC ; + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + clk2_divide_by : NATURAL; + clk2_duty_cycle : NATURAL; + clk2_multiply_by : NATURAL; + clk2_phase_shift : STRING; + clk3_divide_by : NATURAL; + clk3_duty_cycle : NATURAL; + clk3_multiply_by : NATURAL; + clk3_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire8_bv(0 DOWNTO 0) <= "0"; + sub_wire8 <= To_stdlogicvector(sub_wire8_bv); + sub_wire4 <= sub_wire0(3); + sub_wire3 <= sub_wire0(2); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + c2 <= sub_wire3; + c3 <= sub_wire4; + locked <= sub_wire5; + sub_wire6 <= inclk0; + sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 50, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + clk1_divide_by => 2, + clk1_duty_cycle => 50, + clk1_multiply_by => 5, + clk1_phase_shift => "0", + clk2_divide_by => 5, + clk2_duty_cycle => 50, + clk2_multiply_by => 4, + clk2_phase_shift => "0", + clk3_divide_by => 2, + clk3_duty_cycle => 50, + clk3_multiply_by => 5, + clk3_phase_shift => "3000", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "MAX 10", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_USED", + port_clk3 => "PORT_USED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire7, + clk => sub_wire0, + locked => sub_wire5 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "40.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "125.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "40.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "125.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "3.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ns" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK2 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK3 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "5" +-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "2" +-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "5" +-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "3000" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" +-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 +-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/peripherals/sdram/sdram_controller.vhd b/peripherals/sdram/sdram_controller.vhd new file mode 100644 index 00000000..87acc3f2 --- /dev/null +++ b/peripherals/sdram/sdram_controller.vhd @@ -0,0 +1,480 @@ +-------------------------------------------------------------------------------- +-- VLIW-RT CPU - SDRAM controller top entity +-------------------------------------------------------------------------------- +-- +-- Copyright (c) 2016, Renan Augusto Starke +-- +-- Departamento de Automação e Sistemas - DAS (Automation and Systems Department) +-- Universidade Federal de Santa Catarina - UFSC (Federal University of Santa Catarina) +-- Florianópolis, Brasil (Brazil) +-- +-- This file is part of VLIW-RT CPU. + +-- VLIW-RT CPU is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 3 of the License, or +-- (at your option) any later version. + +-- VLIW-RT CPU is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VLIW-RT CPU. If not, see . +-- +-- This file uses Altera libraries subjected to Altera licenses +-- See altera-ip folder for more information + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity sdram_controller is + + -- Altera SDRAM controller configuration + generic( + ASIZE : integer := 25; + DSIZE : integer := 32; + ROWSIZE : integer := 13; + COLSIZE : integer := 10; + BANKSIZE : integer := 2; + ROWSTART : integer := 10; + COLSTART : integer := 0; + BANKSTART : integer := 23; + -- SDRAM latencies + DATA_AVAL : integer := 2; -- cycles + RESET_NOP : integer := 4; -- cycles + RAS_TO_CAS : integer := 2; -- cycles + PRE_TO_ACT : integer := 3; -- cycles + tRP : integer := 2; -- cycles + tRC : integer := 10 -- cycles + ); + + port( + -- inputs: + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + byteenable : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + chipselect : IN STD_LOGIC; + clk : IN STD_LOGIC; + clken : IN STD_LOGIC; + reset : IN STD_LOGIC; + reset_req : IN STD_LOGIC; + write : IN STD_LOGIC; + read : in std_logic; + writedata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + burst : in std_logic; + -- outputs: + readdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + waitrequest : out std_logic; + DRAM_ADDR : out std_logic_vector(12 downto 0); + DRAM_BA : out std_logic_vector(1 downto 0); + DRAM_CAS_N : out std_logic; + DRAM_CKE : out std_logic; + DRAM_CLK : out std_logic; + DRAM_CS_N : out std_logic; + DRAM_DQ : inout std_logic_vector(15 downto 0); + DRAM_DQM : out std_logic_vector(1 downto 0); + DRAM_RAS_N : out std_logic; + DRAM_WE_N : out std_logic + ); +end entity sdram_controller; + +architecture rtl of sdram_controller is + + type mem_state_type is (CONFIG, C_PRE, C_PRE_NOP, C_INIT_AUTO_REFRESH1, C_INIT_AUTO_REFRESH2, C_LD, C_LD_BURST, C_AUTO_REFRESH, IDLE, WRITE_ROW, WRITE_COL, DATA_REG, DONE); + signal mem_state : mem_state_type; + signal nop_nxt_state : mem_state_type; + + signal d_read : std_logic; + signal d_write : std_logic; + + constant WORD_SIZE : integer := 32; + subtype word_t is std_logic_vector(WORD_SIZE - 1 downto 0); + signal mem_data : word_t; + + signal byteenable_reg : STD_LOGIC_VECTOR(1 DOWNTO 0); + + signal in_reg_en : std_logic; + + signal chip_en_reg : std_logic; + + -- sdram controller signal + signal reset_n : std_logic; + signal addr : std_logic_vector(ASIZE - 1 downto 0); + signal cmd : std_logic_vector(2 downto 0); + signal cmdack : std_logic; + signal datain : std_logic_vector(DSIZE - 1 downto 0); + signal dataout : std_logic_vector(DSIZE - 1 downto 0); + signal dm : std_logic_vector(DSIZE / 8 - 1 downto 0); + signal cs_n : std_logic_vector(1 downto 0); + + signal dram_addr_int : std_logic_vector(11 downto 0); + + signal cas_to_ras : std_logic_vector(3 downto 0); + + -- + signal row_addr : std_logic_vector(ROWSIZE - 1 downto 0); + signal col_addr : std_logic_vector(COLSIZE - 1 downto 0); + signal bank_addr : std_logic_vector(BANKSIZE - 1 downto 0); + + -- + signal wait_cycles : std_logic_vector(3 downto 0); + signal chipselect_last_value : std_logic; + signal read_last_value : std_logic; + signal write_last_value : std_logic; + signal burst_last_value : std_logic; + +begin + + reset_n <= not reset; + DRAM_CLK <= clk; + + -- DRAM_CS_N <= cs_n(0); + + -- DRAM_ADDR <= '0' & dram_addr_int; + + -- FS_ADDR <= address(21 downto 2); + + do_clk_mem_acc_state : process(clk, reset, cmdack) + variable refresh_counter : natural; + variable init_refresh_counter : natural; + begin + if reset = '1' then + mem_state <= CONFIG; + wait_cycles <= std_logic_vector(to_unsigned(RESET_NOP, wait_cycles'length)); + else + if rising_edge(clk) then + case mem_state is + when CONFIG => + if reset = '0' then + + -- wait RESET_NOP cycles until first precharge + wait_cycles <= wait_cycles - 1; + + if wait_cycles = 0 then + init_refresh_counter := 0; + mem_state <= C_PRE; + nop_nxt_state <= C_LD; + wait_cycles <= std_logic_vector(to_unsigned(PRE_TO_ACT - 1, wait_cycles'length)); + end if; + else + wait_cycles <= "0000"; + end if; + + when C_PRE => + mem_state <= C_PRE_NOP; + + when C_PRE_NOP => + wait_cycles <= wait_cycles - 1; + + if wait_cycles = 0 then + mem_state <= nop_nxt_state; + end if; + + when C_INIT_AUTO_REFRESH1 => + wait_cycles <= std_logic_vector(to_unsigned(tRC, wait_cycles'length)); + mem_state <= C_PRE_NOP; + nop_nxt_state <= C_INIT_AUTO_REFRESH2; + + when C_INIT_AUTO_REFRESH2 => + wait_cycles <= std_logic_vector(to_unsigned(tRC, wait_cycles'length)); + mem_state <= C_PRE_NOP; + nop_nxt_state <= IDLE; + + when C_LD => + wait_cycles <= std_logic_vector(to_unsigned(PRE_TO_ACT, wait_cycles'length)); + mem_state <= C_PRE_NOP; + nop_nxt_state <= C_AUTO_REFRESH; + + when C_LD_BURST => + wait_cycles <= std_logic_vector(to_unsigned(PRE_TO_ACT, wait_cycles'length)); + mem_state <= C_PRE_NOP; + nop_nxt_state <= C_AUTO_REFRESH; + + when C_AUTO_REFRESH => + wait_cycles <= std_logic_vector(to_unsigned(tRC, wait_cycles'length)); + mem_state <= C_PRE_NOP; + nop_nxt_state <= IDLE; + + when IDLE => + if refresh_counter = 10 then + refresh_counter := 0; + mem_state <= C_AUTO_REFRESH; + elsif burst = '1' and burst_last_value = '0' then + refresh_counter := 0; + mem_state <= C_LD_BURST; + elsif burst = '0' and burst_last_value = '1' then + refresh_counter := 0; + mem_state <= C_LD; + elsif chipselect = '1' and (read = '1' and read_last_value = '0') then + refresh_counter := 0; + read_last_value <= '1'; + mem_state <= WRITE_ROW; + elsif chipselect = '1' and (write = '1' and write_last_value = '0') then + refresh_counter := 0; + write_last_value <= '1'; + mem_state <= WRITE_ROW; + end if; + + if read = '0' then + read_last_value <= '0'; + end if; + if write = '0' then + write_last_value <= '0'; + end if; + if burst /= burst_last_value then + burst_last_value <= burst; + end if; + + refresh_counter := refresh_counter + 1; + + when WRITE_ROW => + wait_cycles <= std_logic_vector(to_unsigned(RAS_TO_CAS - 2, wait_cycles'length)); + mem_state <= C_PRE_NOP; + nop_nxt_state <= WRITE_COL; + + when WRITE_COL => + if read = '1' then + wait_cycles <= std_logic_vector(to_unsigned(DATA_AVAL - 2, wait_cycles'length)); + mem_state <= C_PRE_NOP; + nop_nxt_state <= DATA_REG; + else + mem_state <= DONE; + end if; + + when DATA_REG => + mem_state <= DONE; + + when DONE => + mem_state <= IDLE; + + end case; + end if; + end if; + end process; + + row_addr <= address(ROWSTART + ROWSIZE - 1 downto ROWSTART); -- (10 + (13 - 1) downto 9) -> (22 downto 10) -- assignment of the row address bits from address + col_addr <= address(COLSTART + COLSIZE - 1 downto COLSTART); -- (0 + (9 - 1) downto 0) -> (9 downto 0) -- assignment of the column address bits + bank_addr <= address(BANKSTART + BANKSIZE - 1 downto BANKSTART); -- (23 + (2 - 1) downto 23) -> (24 downto 23) -- assignment of the bank address bits + + do_clk_mem_acc_state_output : process(mem_state, reset, chipselect, write, byteenable, address, chip_en_reg, byteenable_reg, bank_addr, row_addr, col_addr) + begin + in_reg_en <= '0'; + waitrequest <= '0'; + d_read <= '0'; + d_write <= '0'; + + -- altera sdram controller + addr <= (others => '0'); + cmd <= (others => '0'); + + -- internal sdram controller + DRAM_ADDR <= (others => '0'); + + DRAM_BA <= "00"; + DRAM_CS_N <= '0'; + DRAM_CKE <= '1'; + DRAM_RAS_N <= '1'; + DRAM_CAS_N <= '1'; + DRAM_WE_N <= '1'; + + DRAM_DQM <= "00"; + + case mem_state is + + when CONFIG => + if reset = '0' then + waitrequest <= '1'; + addr <= (others => '0'); + DRAM_CS_N <= '0'; + else + DRAM_CKE <= '0'; + end if; + + when C_PRE => + waitrequest <= '1'; + + -- precharge all banks + DRAM_CS_N <= '0'; + DRAM_RAS_N <= '0'; + DRAM_CAS_N <= '1'; + DRAM_WE_N <= '0'; + -- all banks code + DRAM_ADDR(10) <= '1'; + + when C_PRE_NOP => + waitrequest <= '1'; + DRAM_CS_N <= '0'; + + when C_LD => + waitrequest <= '1'; + + -- burst length: 1 word + DRAM_ADDR(2 downto 0) <= "000"; + -- burst type: sequential + DRAM_ADDR(3) <= '0'; + -- cas latency: 2 + DRAM_ADDR(6 downto 4) <= "010"; + -- Op mode: standard operation + DRAM_ADDR(8 downto 7) <= "00"; + -- Write burst mode: single location + DRAM_ADDR(9) <= '1'; + -- reserved + DRAM_ADDR(12 downto 10) <= "001"; + + -- commands + DRAM_BA <= "00"; + DRAM_CS_N <= '0'; + DRAM_RAS_N <= '0'; + DRAM_CAS_N <= '0'; + DRAM_WE_N <= '0'; + + when C_LD_BURST => + waitrequest <= '1'; + + -- burst length: 8 words + DRAM_ADDR(2 downto 0) <= "011"; + -- burst type: sequential + DRAM_ADDR(3) <= '0'; + -- cas latency: 2 + DRAM_ADDR(6 downto 4) <= "010"; + -- Op mode: standard operation + DRAM_ADDR(8 downto 7) <= "00"; + -- Write burst mode: single location + DRAM_ADDR(9) <= '1'; + -- reserved + DRAM_ADDR(12 downto 10) <= "001"; + + -- commands + DRAM_BA <= "00"; + DRAM_CS_N <= '0'; + DRAM_RAS_N <= '0'; + DRAM_CAS_N <= '0'; + DRAM_WE_N <= '0'; + + when C_INIT_AUTO_REFRESH1 => + + -- commands + DRAM_BA <= "00"; + DRAM_CS_N <= '0'; + DRAM_RAS_N <= '0'; + DRAM_CAS_N <= '0'; + DRAM_WE_N <= '1'; + + when C_INIT_AUTO_REFRESH2 => + + -- commands + DRAM_BA <= "00"; + DRAM_CS_N <= '0'; + DRAM_RAS_N <= '0'; + DRAM_CAS_N <= '0'; + DRAM_WE_N <= '1'; + + when C_AUTO_REFRESH => + + -- commands + DRAM_BA <= "00"; + DRAM_CS_N <= '0'; + DRAM_RAS_N <= '0'; + DRAM_CAS_N <= '0'; + DRAM_WE_N <= '1'; + + DRAM_ADDR(10) <= '1'; + + when IDLE => + waitrequest <= chipselect; + + when WRITE_ROW => + waitrequest <= '1'; + + DRAM_BA <= bank_addr; + DRAM_CS_N <= '0'; + DRAM_RAS_N <= '0'; + DRAM_CAS_N <= '1'; + DRAM_WE_N <= '1'; + + DRAM_ADDR <= row_addr; + + when WRITE_COL => + waitrequest <= '1'; + + if write = '1' then + DRAM_DQM <= not byteenable; + d_write <= '1'; + DRAM_WE_N <= '0'; + end if; + + DRAM_BA <= bank_addr; + DRAM_CS_N <= '0'; + DRAM_RAS_N <= '1'; + DRAM_CAS_N <= '0'; + + DRAM_ADDR(COLSIZE - 1 downto 0) <= col_addr; + -- enable auto precharge + DRAM_ADDR(10) <= '1'; + + when DATA_REG => + waitrequest <= '1'; + d_read <= '1'; + + when DONE => + + end case; + end process; + + process(clk, reset, d_read, byteenable, DRAM_DQ) + variable counter : natural := 0; + variable read : std_logic := '0'; + begin + if reset = '1' then + readdata <= (others => '0'); + else + if rising_edge(clk) then + + if d_read = '1' and burst = '1' then + counter := 8; + elsif d_read = '1' then + counter := 1; + end if; + + if counter > 0 then + case byteenable is + + when "00" => + + when "01" => + readdata <= x"00" & DRAM_DQ(7 downto 0); + + when "10" => + readdata <= x"00" & DRAM_DQ(15 downto 8); + + when "11" => + readdata <= DRAM_DQ; + + when others => + end case; + counter := counter - 1; + end if; + + end if; + end if; + end process; + + DRAM_DQ <= (DRAM_DQ'range => 'Z') WHEN (d_write = '0') ELSE writedata(15 downto 0); + + process(clk, reset, byteenable, in_reg_en) + begin + if reset = '1' then + byteenable_reg <= "11"; + else + if rising_edge(clk) and in_reg_en = '1' then + byteenable_reg <= not byteenable; + chip_en_reg <= address(26); + end if; + end if; + end process; + +end rtl; diff --git a/peripherals/sdram/sim/mt48lc8m16a2.vhd b/peripherals/sdram/sim/mt48lc8m16a2.vhd new file mode 100644 index 00000000..053bf031 --- /dev/null +++ b/peripherals/sdram/sim/mt48lc8m16a2.vhd @@ -0,0 +1,1120 @@ +----------------------------------------------------------------------------------------- +-- +-- File Name: MT48LC8M16A2.VHD +-- Version: 0.0c +-- Date: April 8th, 1999 +-- Model: Behavioral +-- Simulator: Model Technology VLOG (PC version 4.7i) +-- +-- Dependencies: None +-- +-- Author: Son P. Huynh +-- Email: sphuynh@micron.com +-- Phone: (208) 368-3825 +-- Company: Micron Technology, Inc. +-- Part Number: MT48LC8M16A2 (2Mb x 16 x 4 Banks) +-- +-- Description: Micron 64Mb SDRAM +-- +-- Limitation: - Doesn't check for 4096-cycle refresh +-- +-- Note: - Set simulator resolution to "ps" accuracy +-- +-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY +-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR +-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. +-- +-- Copyright (c) 1998 Micron Semiconductor Products, Inc. +-- All rights researved +-- +-- Rev Author Phone Date Changes +-- ---- ---------------------------- ---------- ------------------------------------- +-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP +-- Micron Technology Inc. Fix tRC check in Load Mode Register +-- +-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model +-- Micron Technology Inc. +-- +----------------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE WORK.mti_pkg.ALL; + +ENTITY mt48lc8m16a2 IS + GENERIC ( + tAC : TIME := 5.0 ns; -- Timing parameter for -8E device + tAH : TIME := 1.0 ns; + tAS : TIME := 2.0 ns; + tCH : TIME := 3.0 ns; + tCL : TIME := 3.0 ns; + --tCK : TIME := 7.5 ns; -- 133mhz operation + tCK : TIME := 10.0 ns; -- 100mhz operation + tDH : TIME := 1.0 ns; + tDS : TIME := 2.0 ns; + tCKH : TIME := 1.0 ns; + tCKS : TIME := 2.0 ns; + tCMH : TIME := 1.0 ns; + tCMS : TIME := 2.0 ns; + tHZ : TIME := 6.0 ns; + tOH : TIME := 3.0 ns; + tMRD : INTEGER := 2; + tRAS : TIME := 50.0 ns; + tRC : TIME := 80.0 ns; + tRCD : TIME := 20.0 ns; + tRP : TIME := 20.0 ns; + tRRD : TIME := 20.0 ns; + tWR : INTEGER := 2; + addr_bits : INTEGER := 12; + data_bits : INTEGER := 16; + col_bits : INTEGER := 9 + ); + PORT ( + Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); + Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + Ba : IN STD_LOGIC_VECTOR := "00"; + Clk : IN STD_LOGIC := '0'; + Cke : IN STD_LOGIC := '0'; + Cs_n : IN STD_LOGIC := '1'; + Ras_n : IN STD_LOGIC := '0'; + Cas_n : IN STD_LOGIC := '0'; + We_n : IN STD_LOGIC := '0'; + Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00" + ); +END mt48lc8m16a2; + +ARCHITECTURE behave OF mt48lc8m16a2 IS + TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A); + TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER; + TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT; + TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0); + TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0); + TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State; + SIGNAL Operation : State := NOP; + SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0'; + SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0'; + SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0'; + SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0'; + SIGNAL Ras_in, Cas_in, We_in : BIT := '0'; + SIGNAL Write_burst_mode : BIT := '0'; + SIGNAL Sys_clk, CkeZ : BIT := '0'; + + -- Checking internal wires + SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000"; + SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000"; + SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0'; + SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00"; + SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + + BEGIN + -- CS# Decode + WITH Cs_n SELECT + Cas_in <= TO_BIT (Cas_n, '1') WHEN '0', + '1' WHEN '1', + '1' WHEN OTHERS; + WITH Cs_n SELECT + Ras_in <= TO_BIT (Ras_n, '1') WHEN '0', + '1' WHEN '1', + '1' WHEN OTHERS; + WITH Cs_n SELECT + We_in <= TO_BIT (We_n, '1') WHEN '0', + '1' WHEN '1', + '1' WHEN OTHERS; + + -- Commands Decode + Active_enable <= NOT(Ras_in) AND Cas_in AND We_in; + Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in; + Burst_term <= Ras_in AND Cas_in AND NOT(We_in); + Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in); + Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in); + Read_enable <= Ras_in AND NOT(Cas_in) AND We_in; + Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in); + + -- Burst Length Decode + Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0)); + Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); + Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); + Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); + + -- CAS Latency Decode + Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); + Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); + + -- Write Burst Mode + Write_burst_mode <= Mode_reg(9); + + -- System Clock + int_clk : PROCESS (Clk) + begin + IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN + CkeZ <= TO_BIT(Cke, '1'); + END IF; + Sys_clk <= CkeZ AND TO_BIT(Clk, '0'); + END PROCESS; + + state_register : PROCESS + TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits - 1 DOWNTO 0); + TYPE ram_pntr IS ACCESS ram_type; + TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr; + VARIABLE Bank0 : ram_stor; + VARIABLE Bank1 : ram_stor; + VARIABLE Bank2 : ram_stor; + VARIABLE Bank3 : ram_stor; + VARIABLE Row_index, Col_index : INTEGER := 0; + VARIABLE Dq_temp : BIT_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => '0'); + + VARIABLE Col_addr : Array4xCBV; + VARIABLE Bank_addr : Array4x2BV; + VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00"; + + VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00"; + VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + VARIABLE Burst_counter : INTEGER := 0; + + VARIABLE Command : Array_state; + VARIABLE Bank_precharge : Array4x2BV; + VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0); + VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0'); + VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0'); + + VARIABLE Data_in_enable, Data_out_enable : BIT := '0'; + VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0'; + VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0'; + + -- Timing Check + VARIABLE MRD_chk : INTEGER := 0; + VARIABLE RC_chk, RRD_chk : TIME := 0 ns; + VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; + VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; + VARIABLE RP_chk, RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; + VARIABLE WR_chk : Array4xI := (0 & 0 & 0 & 0); + + -- Initialize empty rows + PROCEDURE Init_mem (Bank : BIT_VECTOR (1 DOWNTO 0); Row_index : INTEGER) IS + VARIABLE i, j : INTEGER := 0; + BEGIN + IF Bank = "00" THEN + IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty + Bank0 (Row_index) := NEW ram_type; -- Open new row for access + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank0 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "01" THEN + IF Bank1 (Row_index) = NULL THEN + Bank1 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank1 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "10" THEN + IF Bank2 (Row_index) = NULL THEN + Bank2 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank2 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + ELSIF Bank = "11" THEN + IF Bank3 (Row_index) = NULL THEN + Bank3 (Row_index) := NEW ram_type; + FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP + FOR j IN (data_bits - 1) DOWNTO 0 LOOP + Bank3 (Row_index) (i) (j) := '0'; + END LOOP; + END LOOP; + END IF; + END IF; + END; + + -- Burst Counter + PROCEDURE Burst_decode IS + VARIABLE Col_int : INTEGER := 0; + VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); + BEGIN + -- Advance Burst Counter + Burst_counter := Burst_counter + 1; + + -- Burst Type + IF Mode_reg (3) = '0' THEN + Col_int := TO_INTEGER(Col); + Col_int := Col_int + 1; + TO_BITVECTOR (Col_int, Col_temp); + ELSIF Mode_reg (3) = '1' THEN + TO_BITVECTOR (Burst_counter, Col_vec); + Col_temp (2) := Col_vec (2) XOR Col_brst (2); + Col_temp (1) := Col_vec (1) XOR Col_brst (1); + Col_temp (0) := Col_vec (0) XOR Col_brst (0); + END IF; + + -- Burst Length + IF Burst_length_2 = '1' THEN + Col (0) := Col_temp (0); + ELSIF Burst_length_4 = '1' THEN + Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0); + ELSIF Burst_length_8 = '1' THEN + Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0); + ELSE + Col := Col_temp; + END IF; + + -- Burst Read Single Write + IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + + -- Data counter + IF Burst_length_1 = '1' THEN + IF Burst_counter >= 1 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_2 = '1' THEN + IF Burst_counter >= 2 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_4 = '1' THEN + IF Burst_counter >= 4 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Burst_length_8 = '1' THEN + IF Burst_counter >= 8 THEN + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + ELSIF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + END IF; + END; + + BEGIN + WAIT ON Sys_clk; + IF Sys_clk = '1' THEN + -- Internal Command Pipeline + Command(0) := Command(1); + Command(1) := Command(2); + Command(2) := Command(3); + Command(3) := NOP; + + Col_addr(0) := Col_addr(1); + Col_addr(1) := Col_addr(2); + Col_addr(2) := Col_addr(3); + Col_addr(3) := (OTHERS => '0'); + + Bank_addr(0) := Bank_addr(1); + Bank_addr(1) := Bank_addr(2); + Bank_addr(2) := Bank_addr(3); + Bank_addr(3) := "00"; + + Bank_precharge(0) := Bank_precharge(1); + Bank_precharge(1) := Bank_precharge(2); + Bank_precharge(2) := Bank_precharge(3); + Bank_precharge(3) := "00"; + + A10_precharge(0) := A10_precharge(1); + A10_precharge(1) := A10_precharge(2); + A10_precharge(2) := A10_precharge(3); + A10_precharge(3) := '0'; + + -- Operation Decode (Optional for showing current command on posedge clock / debug feature) + IF Active_enable = '1' THEN + Operation <= ACT; + ELSIF Aref_enable = '1' THEN + Operation <= A_REF; + ELSIF Burst_term = '1' THEN + Operation <= BST; + ELSIF Mode_reg_enable = '1' THEN + Operation <= LMR; + ELSIF Prech_enable = '1' THEN + Operation <= PRECH; + ELSIF Read_enable = '1' THEN + IF Addr(10) = '0' THEN + Operation <= READ; + ELSE + Operation <= READ_A; + END IF; + ELSIF Write_enable = '1' THEN + IF Addr(10) = '0' THEN + Operation <= WRITE; + ELSE + Operation <= WRITE_A; + END IF; + ELSE + Operation <= NOP; + END IF; + + -- Dqm pipeline for Read + Dqm_reg0 := Dqm_reg1; + Dqm_reg1 := TO_BITVECTOR(Dqm); + + -- Read or Write with Auto Precharge Counter + IF Auto_precharge (0) = '1' THEN + Count_precharge (0) := Count_precharge (0) + 1; + END IF; + IF Auto_precharge (1) = '1' THEN + Count_precharge (1) := Count_precharge (1) + 1; + END IF; + IF Auto_precharge (2) = '1' THEN + Count_precharge (2) := Count_precharge (2) + 1; + END IF; + IF Auto_precharge (3) = '1' THEN + Count_precharge (3) := Count_precharge (3) + 1; + END IF; + + -- tMRD Counter + MRD_chk := MRD_chk + 1; + + -- tWR Counter + WR_chk(0) := WR_chk(0) + 1; + WR_chk(1) := WR_chk(1) + 1; + WR_chk(2) := WR_chk(2) + 1; + WR_chk(3) := WR_chk(3) + 1; + + -- Auto Refresh + IF Aref_enable = '1' THEN + -- Auto Refresh to Auto Refresh + ASSERT (NOW - RC_chk >= tRC) + REPORT "tRC violation during Auto Refresh" + SEVERITY WARNING; + -- Precharge to Auto Refresh + ASSERT (NOW - RP_chk >= tRP) + REPORT "tRP violation during Auto Refresh" + SEVERITY WARNING; + -- All banks must be idle before refresh + IF (Pc_b0 ='0' OR Pc_b1 = '0' OR Pc_b2 ='0' OR Pc_b3 = '0') THEN + ASSERT (FALSE) + REPORT "All banks must be Precharge before Auto Refresh" + SEVERITY WARNING; + END IF; + -- Record current tRC time + RC_chk := NOW; + END IF; + + -- Load Mode Register + IF Mode_reg_enable = '1' THEN + Mode_reg <= TO_BITVECTOR (Addr); + IF (Pc_b0 ='0' OR Pc_b1 = '0' OR Pc_b2 ='0' OR Pc_b3 = '0') THEN + ASSERT (FALSE) + REPORT "All bank must be Precharge before Load Mode Register" + SEVERITY WARNING; + END IF; + -- REF to LMR + ASSERT (NOW - RC_chk >= tRC) + REPORT "tRC violation during Load Mode Register" + SEVERITY WARNING; + -- LMR to LMR + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Load Mode Register" + SEVERITY WARNING; + -- Record current tMRD time + MRD_chk := 0; + END IF; + + -- Active Block (latch Bank and Row Address) + IF Active_enable = '1' THEN + IF Ba = "00" AND Pc_b0 = '1' THEN + Act_b0 := '1'; + Pc_b0 := '0'; + B0_row_addr := TO_BITVECTOR (Addr); + RCD_chk0 := NOW; + RAS_chk0 := NOW; + -- Precharge to Active Bank 0 + ASSERT (NOW - RP_chk0 >= tRP) + REPORT "tRP violation during Activate Bank 0" + SEVERITY WARNING; + ELSIF Ba = "01" AND Pc_b1 = '1' THEN + Act_b1 := '1'; + Pc_b1 := '0'; + B1_row_addr := TO_BITVECTOR (Addr); + RCD_chk1 := NOW; + RAS_chk1 := NOW; + -- Precharge to Active Bank 1 + ASSERT (NOW - RP_chk1 >= tRP) + REPORT "tRP violation during Activate Bank 1" + SEVERITY WARNING; + ELSIF Ba = "10" AND Pc_b2 = '1' THEN + Act_b2 := '1'; + Pc_b2 := '0'; + B2_row_addr := TO_BITVECTOR (Addr); + RCD_chk2 := NOW; + RAS_chk2 := NOW; + -- Precharge to Active Bank 2 + ASSERT (NOW - RP_chk2 >= tRP) + REPORT "tRP violation during Activate Bank 2" + SEVERITY WARNING; + ELSIF Ba = "11" AND Pc_b3 = '1' THEN + Act_b3 := '1'; + Pc_b3 := '0'; + B3_row_addr := TO_BITVECTOR (Addr); + RCD_chk3 := NOW; + RAS_chk3 := NOW; + -- Precharge to Active Bank 3 + ASSERT (NOW - RP_chk3 >= tRP) + REPORT "tRP violation during Activate Bank 3" + SEVERITY WARNING; + ELSIF Ba = "00" AND Pc_b0 = '0' THEN + ASSERT (FALSE) + REPORT "Bank 0 is not Precharged" + SEVERITY WARNING; + ELSIF Ba = "01" AND Pc_b1 = '0' THEN + ASSERT (FALSE) + REPORT "Bank 1 is not Precharged" + SEVERITY WARNING; + ELSIF Ba = "10" AND Pc_b2 = '0' THEN + ASSERT (FALSE) + REPORT "Bank 2 is not Precharged" + SEVERITY WARNING; + ELSIF Ba = "11" AND Pc_b3 = '0' THEN + ASSERT (FALSE) + REPORT "Bank 3 is not Precharged" + SEVERITY WARNING; + END IF; + -- Active Bank A to Active Bank B + IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN + ASSERT (FALSE) + REPORT "tRRD violation during Activate" + SEVERITY WARNING; + END IF; + -- LMR to ACT + ASSERT (MRD_chk >= tMRD) + REPORT "tMRD violation during Activate" + SEVERITY WARNING; + -- AutoRefresh to Activate + ASSERT (NOW - RC_chk >= tRC) + REPORT "tRC violation during Activate" + SEVERITY WARNING; + -- Record variable for checking violation + RRD_chk := NOW; + Previous_bank := TO_BITVECTOR (Ba); + END IF; + + -- Precharge Block + IF Prech_enable = '1' THEN + IF Addr(10) = '1' THEN + Pc_b0 := '1'; + Pc_b1 := '1'; + Pc_b2 := '1'; + Pc_b3 := '1'; + Act_b0 := '0'; + Act_b1 := '0'; + Act_b2 := '0'; + Act_b3 := '0'; + RP_chk0 := NOW; + RP_chk1 := NOW; + RP_chk2 := NOW; + RP_chk3 := NOW; + -- Activate to Precharge all banks + ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS)) + REPORT "tRAS violation during Precharge all banks" + SEVERITY WARNING; + -- tWR violation check for Write + IF ((WR_chk(0) < tWR) OR (WR_chk(1) < tWR) OR + (WR_chk(2) < tWR) OR (WR_chk(3) < tWR)) THEN + ASSERT (FALSE) + REPORT "tWR violation during Precharge ALL banks" + SEVERITY WARNING; + END IF; + ELSIF Addr(10) = '0' THEN + IF Ba = "00" THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + -- Activate to Precharge bank 0 + ASSERT (NOW - RAS_chk0 >= tRAS) + REPORT "tRAS violation during Precharge bank 0" + SEVERITY WARNING; + ELSIF Ba = "01" THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + -- Activate to Precharge bank 1 + ASSERT (NOW - RAS_chk1 >= tRAS) + REPORT "tRAS violation during Precharge bank 1" + SEVERITY WARNING; + ELSIF Ba = "10" THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + -- Activate to Precharge bank 2 + ASSERT (NOW - RAS_chk2 >= tRAS) + REPORT "tRAS violation during Precharge bank 2" + SEVERITY WARNING; + ELSIF Ba = "11" THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + -- Activate to Precharge bank 3 + ASSERT (NOW - RAS_chk3 >= tRAS) + REPORT "tRAS violation during Precharge bank 3" + SEVERITY WARNING; + END IF; + -- tWR violation check for Write + ASSERT (WR_chk(TO_INTEGER(Ba)) >= tWR) + REPORT "tWR violation during Precharge" + SEVERITY WARNING; + END IF; + -- Terminate a Write Immediately (if same bank or all banks) + IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN + Data_in_enable := '0'; + END IF; + -- Precharge Command Pipeline for READ + IF CAS_latency_3 = '1' THEN + Command(2) := PRECH; + Bank_precharge(2) := TO_BITVECTOR (Ba); + A10_precharge(2) := TO_BIT(Addr(10)); + ELSIF CAS_latency_2 = '1' THEN + Command(1) := PRECH; + Bank_precharge(1) := TO_BITVECTOR (Ba); + A10_precharge(1) := TO_BIT(Addr(10)); + END IF; + -- Record Current tRP time + RP_chk := NOW; + END IF; + + -- Burst Terminate + IF Burst_term = '1' THEN + -- Terminate a Write immediately + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + END IF; + -- Terminate a Read depend on CAS Latency + IF CAS_latency_3 = '1' THEN + Command(2) := BST; + ELSIF CAS_latency_2 = '1' THEN + Command(1) := BST; + END IF; + END IF; + + -- Read, Write, Column Latch + IF Read_enable = '1' OR Write_enable = '1' THEN + -- Check to see if bank is open (ACT) for Read or Write + IF ((Ba = "00" AND Pc_b0 = '1') OR (Ba = "01" AND Pc_b1 = '1') OR (Ba = "10" AND Pc_b2 = '1') OR (Ba = "11" AND Pc_b3 = '1')) THEN + ASSERT (FALSE) + REPORT "Cannot Read or Write - Bank is not Activated" + SEVERITY WARNING; + END IF; + -- Activate to Read or Write + IF Ba = "00" THEN + ASSERT (NOW - RCD_chk0 >= tRCD) + REPORT "tRCD violation during Read or Write to Bank 0" + SEVERITY WARNING; + ELSIF Ba = "01" THEN + ASSERT (NOW - RCD_chk1 >= tRCD) + REPORT "tRCD violation during Read or Write to Bank 1" + SEVERITY WARNING; + ELSIF Ba = "10" THEN + ASSERT (NOW - RCD_chk2 >= tRCD) + REPORT "tRCD violation during Read or Write to Bank 2" + SEVERITY WARNING; + ELSIF Ba = "11" THEN + ASSERT (NOW - RCD_chk3 >= tRCD) + REPORT "tRCD violation during Read or Write to Bank 3" + SEVERITY WARNING; + END IF; + + -- Read Command + IF Read_enable = '1' THEN + -- CAS Latency Pipeline + IF Cas_latency_3 = '1' THEN + IF Addr(10) = '1' THEN + Command(2) := READ_A; + ELSE + Command(2) := READ; + END IF; + Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0)); + Bank_addr (2) := TO_BITVECTOR (Ba); + ELSIF Cas_latency_2 = '1' THEN + IF Addr(10) = '1' THEN + Command(1) := READ_A; + ELSE + Command(1) := READ; + END IF; + Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0)); + Bank_addr (1) := TO_BITVECTOR (Ba); + END IF; + + -- Read intterupt a Write (terminate Write immediately) + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + IF Auto_precharge(TO_INTEGER(Bank)) = '1' AND Write_precharge(TO_INTEGER(Bank)) = '1' THEN + RW_interrupt_write(TO_INTEGER(Bank)) := '1'; + END IF; + END IF; + + -- Read interrupt a Read (terminate Read after CL) + IF Data_out_enable = '1' THEN + IF Auto_precharge(TO_INTEGER(Bank)) = '1' AND Read_precharge(TO_INTEGER(Bank)) = '1' THEN + RW_interrupt_read(TO_INTEGER(Bank)) := '1'; + END IF; + END IF; + + -- Write Command + ELSIF Write_enable = '1' THEN + IF Addr(10) = '1' THEN + Command(0) := WRITE_A; + ELSE + Command(0) := WRITE; + END IF; + Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0)); + Bank_addr (0) := TO_BITVECTOR (Ba); + + -- Write intterupt a Write (terminate Write immediately) + IF Data_in_enable = '1' THEN + Data_in_enable := '0'; + IF Auto_precharge(TO_INTEGER(Bank)) = '1' AND Write_precharge(TO_INTEGER(Bank)) = '1' THEN + RW_interrupt_write(TO_INTEGER(Bank)) := '1'; + END IF; + END IF; + + -- Write interrupt a Read (terminate Read immediately) + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + IF Auto_precharge(TO_INTEGER(Bank)) = '1' AND Read_precharge(TO_INTEGER(Bank)) = '1' THEN + RW_interrupt_read(TO_INTEGER(Bank)) := '1'; + END IF; + END IF; + END IF; + + -- Read or Write with Auto Precharge + IF Addr(10) = '1' THEN + Auto_precharge (TO_INTEGER(Ba)) := '1'; + Count_precharge (TO_INTEGER(Ba)) := 0; + IF Read_enable = '1' THEN + Read_precharge (TO_INTEGER(Ba)) := '1'; + ELSIF Write_enable = '1' THEN + Write_precharge (TO_INTEGER(Ba)) := '1'; + END IF; + END IF; + END IF; + + -- Read with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. BL/2 cycles after command + -- and 2. Meet tRAS requirement + -- or 3. Interrupt by a Read or Write (with or without Auto Precharge) + IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN + IF (((NOW - RAS_chk0 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR + (RW_interrupt_read(0) = '1')) THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + Auto_precharge(0) := '0'; + Read_precharge(0) := '0'; + RW_interrupt_read(0) := '0'; + END IF; + END IF; + IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN + IF (((NOW - RAS_chk1 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR + (RW_interrupt_read(1) = '1')) THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + Auto_precharge(1) := '0'; + Read_precharge(1) := '0'; + RW_interrupt_read(1) := '0'; + END IF; + END IF; + IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN + IF (((NOW - RAS_chk2 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR + (RW_interrupt_read(2) = '1')) THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + Auto_precharge(2) := '0'; + Read_precharge(2) := '0'; + RW_interrupt_read(2) := '0'; + END IF; + END IF; + IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN + IF (((NOW - RAS_chk3 >= tRAS) AND + ((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR + (Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR + (RW_interrupt_read(3) = '1')) THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + Auto_precharge(3) := '0'; + Read_precharge(3) := '0'; + RW_interrupt_read(3) := '0'; + END IF; + END IF; + + -- Write with AutoPrecharge Calculation + -- The device start internal precharge when: + -- 1. tWR cycles after command + -- and 2. Meet tRAS requirement + -- or 3. Interrupt by a Read or Write (with or without Auto Precharge) + IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN + IF (((NOW - RAS_chk0 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 2) OR + (Burst_length_2 = '1' AND Count_precharge(0) >= 3) OR + (Burst_length_4 = '1' AND Count_precharge(0) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge(0) >= 9))) OR + (RW_interrupt_write(0) = '1' AND WR_chk(0) >= 3)) THEN + Pc_b0 := '1'; + Act_b0 := '0'; + RP_chk0 := NOW; + Auto_precharge(0) := '0'; + Write_precharge(0) := '0'; + RW_interrupt_write(0) := '0'; + END IF; + END IF; + IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN + IF (((NOW - RAS_chk1 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 2) OR + (Burst_length_2 = '1' AND Count_precharge(1) >= 3) OR + (Burst_length_4 = '1' AND Count_precharge(1) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge(1) >= 9))) OR + (RW_interrupt_write(1) = '1' AND WR_chk(1) >= 3)) THEN + Pc_b1 := '1'; + Act_b1 := '0'; + RP_chk1 := NOW; + Auto_precharge(1) := '0'; + Write_precharge(1) := '0'; + RW_interrupt_write(1) := '0'; + END IF; + END IF; + IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN + IF (((NOW - RAS_chk2 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 2) OR + (Burst_length_2 = '1' AND Count_precharge(2) >= 3) OR + (Burst_length_4 = '1' AND Count_precharge(2) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge(2) >= 9))) OR + (RW_interrupt_write(2) = '1' AND WR_chk(2) >= 3)) THEN + Pc_b2 := '1'; + Act_b2 := '0'; + RP_chk2 := NOW; + Auto_precharge(2) := '0'; + Write_precharge(2) := '0'; + RW_interrupt_write(2) := '0'; + END IF; + END IF; + IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN + IF (((NOW - RAS_chk3 >= tRAS) AND + (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 2) OR + (Burst_length_2 = '1' AND Count_precharge(3) >= 3) OR + (Burst_length_4 = '1' AND Count_precharge(3) >= 5) OR + (Burst_length_8 = '1' AND Count_precharge(3) >= 9))) OR + (RW_interrupt_write(3) = '1' AND WR_chk(3) >= 3)) THEN + Pc_b3 := '1'; + Act_b3 := '0'; + RP_chk3 := NOW; + Auto_precharge(3) := '0'; + Write_precharge(3) := '0'; + RW_interrupt_write(3) := '0'; + END IF; + END IF; + + -- Internal Precharge or Bst + IF Command(0) = PRECH THEN -- Terminate a read if same bank or all banks + IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + ELSIF Command(0) = BST THEN -- Terminate a read immediately + IF Data_out_enable = '1' THEN + Data_out_enable := '0'; + END IF; + END IF; + + IF Data_out_enable = '0' THEN + Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH; + END IF; + + -- Detect Read or Write Command + IF Command(0) = READ OR Command(0) = READ_A THEN + Bank := Bank_addr (0); + Col := Col_addr (0); + Col_brst := Col_addr (0); + IF Bank_addr (0) = "00" THEN + Row := B0_row_addr; + ELSIF Bank_addr (0) = "01" THEN + Row := B1_row_addr; + ELSIF Bank_addr (0) = "10" THEN + Row := B2_row_addr; + ELSE + Row := B3_row_addr; + END IF; + Burst_counter := 0; + Data_in_enable := '0'; + Data_out_enable := '1'; + ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN + Bank := Bank_addr(0); + Col := Col_addr(0); + Col_brst := Col_addr(0); + IF Bank_addr (0) = "00" THEN + Row := B0_row_addr; + ELSIF Bank_addr (0) = "01" THEN + Row := B1_row_addr; + ELSIF Bank_addr (0) = "10" THEN + Row := B2_row_addr; + ELSE + Row := B3_row_addr; + END IF; + Burst_counter := 0; + Data_in_enable := '1'; + Data_out_enable := '0'; + END IF; + + -- DQ (Driver / Receiver) + Row_index := TO_INTEGER (Row); + Col_index := TO_INTEGER (Col); + IF Data_in_enable = '1' THEN + IF Dqm /= "11" THEN + Init_mem (Bank, Row_index); + IF Bank = "00" THEN + Dq_temp := Bank0 (Row_index) (Col_index); + IF Dqm = "01" THEN + Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8)); + ELSIF Dqm = "10" THEN + Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0)); + ELSE + Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0)); + END IF; + Bank0 (Row_index) (Col_index) := Dq_temp; + ELSIF Bank = "01" THEN + Dq_temp := Bank1 (Row_index) (Col_index); + IF Dqm = "01" THEN + Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8)); + ELSIF Dqm = "10" THEN + Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0)); + ELSE + Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0)); + END IF; + Bank1 (Row_index) (Col_index) := Dq_temp; + ELSIF Bank = "10" THEN + Dq_temp := Bank2 (Row_index) (Col_index); + IF Dqm = "01" THEN + Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8)); + ELSIF Dqm = "10" THEN + Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0)); + ELSE + Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0)); + END IF; + Bank2 (Row_index) (Col_index) := Dq_temp; + ELSIF Bank = "11" THEN + Dq_temp := Bank3 (Row_index) (Col_index); + IF Dqm = "01" THEN + Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8)); + ELSIF Dqm = "10" THEN + Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0)); + ELSE + Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0)); + END IF; + Bank3 (Row_index) (Col_index) := Dq_temp; + END IF; + WR_chk(TO_INTEGER(Bank)) := 0; + END IF; + Burst_decode; + ELSIF Data_out_enable = '1' THEN + IF Dqm_reg0 /= "11" THEN + Init_mem (Bank, Row_index); + IF Bank = "00" THEN + Dq_temp (15 DOWNTO 0) := Bank0 (Row_index) (Col_index); + IF Dqm_reg0 = "00" THEN + Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC; + ELSIF Dqm_reg0 = "01" THEN + Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + ELSIF Dqm_reg0 = "10" THEN + Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC; + END IF; + ELSIF Bank = "01" THEN + Dq_temp (15 DOWNTO 0) := Bank1 (Row_index) (Col_index); + IF Dqm_reg0 = "00" THEN + Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC; + ELSIF Dqm_reg0 = "01" THEN + Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + ELSIF Dqm_reg0 = "10" THEN + Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC; + END IF; + ELSIF Bank = "10" THEN + Dq_temp (15 DOWNTO 0) := Bank2 (Row_index) (Col_index); + IF Dqm_reg0 = "00" THEN + Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC; + ELSIF Dqm_reg0 = "01" THEN + Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + ELSIF Dqm_reg0 = "10" THEN + Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC; + END IF; + ELSIF Bank = "11" THEN + Dq_temp (15 DOWNTO 0) := Bank3 (Row_index) (Col_index); + IF Dqm_reg0 = "00" THEN + Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC; + ELSIF Dqm_reg0 = "01" THEN + Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + ELSIF Dqm_reg0 = "10" THEN + Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC; + Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC; + END IF; + END IF; + ELSE + Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ; + END IF; + Burst_decode; + END IF; + + -- Checking internal wires (Optional for debug purpose) + Pre_chk (0) <= Pc_b0; + Pre_chk (1) <= Pc_b1; + Pre_chk (2) <= Pc_b2; + Pre_chk (3) <= Pc_b3; + Act_chk (0) <= Act_b0; + Act_chk (1) <= Act_b1; + Act_chk (2) <= Act_b2; + Act_chk (3) <= Act_b3; + Dq_in_chk <= Data_in_enable; + Dq_out_chk <= Data_out_enable; + Bank_chk <= Bank; + Row_chk <= Row; + Col_chk <= Col; + END IF; + END PROCESS; + + + -- Clock timing checks + Clock_check : PROCESS + VARIABLE Clk_low, Clk_high : TIME := 0 ns; + BEGIN + WAIT ON Clk; + IF (Clk = '1' AND NOW >= 10 ns) THEN + ASSERT (NOW - Clk_low >= tCL) + REPORT "tCL violation" + SEVERITY WARNING; + ASSERT (NOW - Clk_high >= tCK) + REPORT "tCK violation" + SEVERITY WARNING; + Clk_high := NOW; + ELSIF (Clk = '0' AND NOW /= 0 ns) THEN + ASSERT (NOW - Clk_high >= tCH) + REPORT "tCH violation" + SEVERITY WARNING; + Clk_low := NOW; + END IF; + END PROCESS; + + -- Setup timing checks + Setup_check : PROCESS + BEGIN + WAIT ON Clk; + IF Clk = '1' THEN + ASSERT(Cke'LAST_EVENT >= tCKS) + REPORT "CKE Setup time violation -- tCKS" + SEVERITY WARNING; + ASSERT(Cs_n'LAST_EVENT >= tCMS) + REPORT "CS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT >= tCMS) + REPORT "CAS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT >= tCMS) + REPORT "RAS# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT >= tCMS) + REPORT "WE# Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Dqm'LAST_EVENT >= tCMS) + REPORT "DQM Setup time violation -- tCMS" + SEVERITY WARNING; + ASSERT(Addr'LAST_EVENT >= tAS) + REPORT "ADDR Setup time violation -- tAS" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT >= tAS) + REPORT "BA Setup time violation -- tAS" + SEVERITY WARNING; + ASSERT(Dq'LAST_EVENT >= tDS) + REPORT "DQ Setup time violation -- tDS" + SEVERITY WARNING; + END IF; + END PROCESS; + + -- Hold timing checks + Hold_check : PROCESS + BEGIN + WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH); + IF Clk'DELAYED (tCKH) = '1' THEN + ASSERT(Cke'LAST_EVENT > tCKH) + REPORT "CKE Hold time violation -- tCKH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tCMH) = '1' THEN + ASSERT(Cs_n'LAST_EVENT > tCMH) + REPORT "CS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Cas_n'LAST_EVENT > tCMH) + REPORT "CAS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Ras_n'LAST_EVENT > tCMH) + REPORT "RAS# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(We_n'LAST_EVENT > tCMH) + REPORT "WE# Hold time violation -- tCMH" + SEVERITY WARNING; + ASSERT(Dqm'LAST_EVENT > tCMH) + REPORT "DQM Hold time violation -- tCMH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tAH) = '1' THEN + ASSERT(Addr'LAST_EVENT > tAH) + REPORT "ADDR Hold time violation -- tAH" + SEVERITY WARNING; + ASSERT(Ba'LAST_EVENT > tAH) + REPORT "BA Hold time violation -- tAH" + SEVERITY WARNING; + END IF; + IF Clk'DELAYED (tDH) = '1' THEN + ASSERT(Dq'LAST_EVENT > tDH) + REPORT "DQ Hold time violation -- tDH" + SEVERITY WARNING; + END IF; + END PROCESS; + +END behave; \ No newline at end of file diff --git a/peripherals/sdram/sim/mti_pkg.vhd b/peripherals/sdram/sim/mti_pkg.vhd new file mode 100644 index 00000000..54cd91bb --- /dev/null +++ b/peripherals/sdram/sim/mti_pkg.vhd @@ -0,0 +1,143 @@ +--***************************************************************************** +-- +-- Micron Semiconductor Products, Inc. +-- +-- Copyright 1997, Micron Semiconductor Products, Inc. +-- All rights reserved. +-- +--***************************************************************************** + +LIBRARY work; +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +PACKAGE mti_pkg IS + + FUNCTION TO_INTEGER (input : BIT) RETURN INTEGER; + FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER; + FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER; + FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER; + PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR); + +END mti_pkg; + +PACKAGE BODY mti_pkg IS + + -- Convert BIT to INTEGER + FUNCTION TO_INTEGER (input : BIT) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + VARIABLE weight : INTEGER := 1; + BEGIN + IF input = '1' THEN + result := weight; + ELSE + result := 0; -- if unknowns, default to logic 0 + END IF; + RETURN result; + END TO_INTEGER; + + -- Convert BIT_VECTOR to INTEGER + FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + VARIABLE weight : INTEGER := 1; + BEGIN + FOR i IN input'LOW TO input'HIGH LOOP + IF input(i) = '1' THEN + result := result + weight; + ELSE + result := result + 0; -- if unknowns, default to logic 0 + END IF; + weight := weight * 2; + END LOOP; + RETURN result; + END TO_INTEGER; + + -- Convert STD_LOGIC to INTEGER + FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + VARIABLE weight : INTEGER := 1; + BEGIN + IF input = '1' THEN + result := weight; + ELSE + result := 0; -- if unknowns, default to logic 0 + END IF; + RETURN result; + END TO_INTEGER; + + -- Convert STD_LOGIC_VECTOR to INTEGER + FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS + VARIABLE result : INTEGER := 0; + VARIABLE weight : INTEGER := 1; + BEGIN + FOR i IN input'LOW TO input'HIGH LOOP + IF input(i) = '1' THEN + result := result + weight; + ELSE + result := result + 0; -- if unknowns, default to logic 0 + END IF; + weight := weight * 2; + END LOOP; + RETURN result; + END TO_INTEGER; + + -- Conver integer to bit_vector + PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS + VARIABLE work,offset,outputlen,j : INTEGER := 0; + BEGIN + --length of vector + IF output'LENGTH > 32 THEN + outputlen := 32; + offset := output'LENGTH - 32; + IF input >= 0 THEN + FOR i IN offset-1 DOWNTO 0 LOOP + output(output'HIGH - i) := '0'; + END LOOP; + ELSE + FOR i IN offset-1 DOWNTO 0 LOOP + output(output'HIGH - i) := '1'; + END LOOP; + END IF; + ELSE + outputlen := output'LENGTH; + END IF; + --positive value + IF (input >= 0) THEN + work := input; + j := outputlen - 1; + FOR i IN 1 to 32 LOOP + IF j >= 0 then + IF (work MOD 2) = 0 THEN + output(output'HIGH-j-offset) := '0'; + ELSE + output(output'HIGH-j-offset) := '1'; + END IF; + END IF; + work := work / 2; + j := j - 1; + END LOOP; + IF outputlen = 32 THEN + output(output'HIGH) := '0'; + END IF; + --negative value + ELSE + work := (-input) - 1; + j := outputlen - 1; + FOR i IN 1 TO 32 LOOP + IF j>= 0 THEN + IF (work MOD 2) = 0 THEN + output(output'HIGH-j-offset) := '1'; + ELSE + output(output'HIGH-j-offset) := '0'; + END IF; + END IF; + work := work / 2; + j := j - 1; + END LOOP; + IF outputlen = 32 THEN + output(output'HIGH) := '1'; + END IF; + END IF; + END TO_BITVECTOR; + +END mti_pkg; \ No newline at end of file diff --git a/peripherals/sdram/sint/de10_lite.ipregen.rpt b/peripherals/sdram/sint/de10_lite.ipregen.rpt new file mode 100644 index 00000000..99d47685 --- /dev/null +++ b/peripherals/sdram/sint/de10_lite.ipregen.rpt @@ -0,0 +1,68 @@ +IP Upgrade report for de10_lite +Mon Jul 8 11:04:27 2019 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. IP Upgrade Summary + 3. Successfully Upgraded IP Components + 4. IP Upgrade Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------+ +; IP Upgrade Summary ; ++------------------------------+-------------------------------------------------+ +; IP Components Upgrade Status ; Passed - Mon Jul 8 11:04:27 2019 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; de10_lite ; +; Top-level Entity Name ; de10_lite ; +; Family ; MAX 10 ; ++------------------------------+-------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; Successfully Upgraded IP Components ; ++-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ +; Entity Name ; Component Name ; Version ; Original Source File ; Generation File Path ; New Source File ; Message ; ++-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ +; pll ; ALTPLL ; 17.1 ; ../pll/pll.qip ; ../pll/pll.vhd ; ../pll/pll.qip ; ; ++-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ + + ++---------------------+ +; IP Upgrade Messages ; ++---------------------+ +Info (11902): Backing up file "../pll/pll.vhd" to "../pll/pll.BAK.vhd" +Info (11837): Started upgrading IP component ALTPLL with file "../pll/pll.vhd" +Info (11131): Completed upgrading IP component ALTPLL with file "../pll/pll.vhd" +Info (23030): Evaluation of Tcl script /home/xtarke/Data/Apps/intelFPGA/18.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful +Info: Quartus Prime Shell was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 1064 megabytes + Info: Processing ended: Mon Jul 8 11:04:27 2019 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:28 + + diff --git a/peripherals/sdram/sint/de10_lite.qpf b/peripherals/sdram/sint/de10_lite.qpf new file mode 100644 index 00000000..2e37e9d1 --- /dev/null +++ b/peripherals/sdram/sint/de10_lite.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition +# Date created = 18:49:34 June 20, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.0" +DATE = "18:49:34 June 20, 2019" + +# Revisions + +PROJECT_REVISION = "de10_lite" diff --git a/peripherals/sdram/sint/de10_lite.qsf b/peripherals/sdram/sint/de10_lite.qsf new file mode 100644 index 00000000..58d952af --- /dev/null +++ b/peripherals/sdram/sint/de10_lite.qsf @@ -0,0 +1,233 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition +# Date created = 18:49:34 June 20, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# de10_lite_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:49:34 JUNE 20, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name ENABLE_OCT_DONE ON +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name QIP_FILE ../pll/pll.qip +set_global_assignment -name SDC_FILE de10_lite.sdc +set_global_assignment -name VHDL_FILE ../../../alu/alu_types.vhd +set_global_assignment -name VHDL_FILE ../../../alu/alu.vhd +set_global_assignment -name VHDL_FILE ../de10_lite.vhd +set_global_assignment -name VHDL_FILE ../../../alu/m/M_types.vhd +set_global_assignment -name VHDL_FILE ../../../alu/m/M.vhd +set_global_assignment -name VHDL_FILE ../../../memory/dmemory.vhd +set_global_assignment -name VHDL_FILE ../../../memory/iram_quartus.vhd +set_global_assignment -name QIP_FILE ../../../memory/iram_quartus.qip +set_global_assignment -name VHDL_FILE ../../../decoder/iregister.vhd +set_global_assignment -name VHDL_FILE ../../../decoder/decoder_types.vhd +set_global_assignment -name VHDL_FILE ../../../decoder/decoder.vhd +set_global_assignment -name VHDL_FILE ../../../core/core.vhd +set_global_assignment -name VHDL_FILE ../../../registers/register_file.vhd +set_global_assignment -name VHDL_FILE ../sdram_controller.vhd + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/peripherals/sdram/sint/de10_lite.qws b/peripherals/sdram/sint/de10_lite.qws new file mode 100644 index 00000000..996fe0a5 Binary files /dev/null and b/peripherals/sdram/sint/de10_lite.qws differ diff --git a/peripherals/sdram/sint/de10_lite.sdc b/peripherals/sdram/sint/de10_lite.sdc new file mode 100644 index 00000000..7267c16e --- /dev/null +++ b/peripherals/sdram/sint/de10_lite.sdc @@ -0,0 +1,86 @@ +#************************************************************** +# This .sdc file is created by Terasic Tool. +# Users are recommended to modify this file to match users logic. +#************************************************************** + +#************************************************************** +# Create Clock +#************************************************************** +create_clock -period "10.0 MHz" [get_ports ADC_CLK_10] +create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50] +create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50] + +#************************************************************** +# Create Generated Clock +#************************************************************** +derive_pll_clocks + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** +derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + + + +#************************************************************** +# Set Load +#************************************************************** + + + diff --git a/peripherals/sdram/sint/de10_lite_assignment_defaults.qdf b/peripherals/sdram/sint/de10_lite_assignment_defaults.qdf new file mode 100644 index 00000000..d40b50e3 --- /dev/null +++ b/peripherals/sdram/sint/de10_lite_assignment_defaults.qdf @@ -0,0 +1,807 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# Date created = 08:39:22 July 08, 2019 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY -value "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/peripherals/sdram/sint/de10_lite_description.txt b/peripherals/sdram/sint/de10_lite_description.txt new file mode 100644 index 00000000..e69de29b diff --git a/peripherals/sdram/testbench_sdram.do b/peripherals/sdram/testbench_sdram.do new file mode 100644 index 00000000..3900bedb --- /dev/null +++ b/peripherals/sdram/testbench_sdram.do @@ -0,0 +1,42 @@ +# cd C:/Users/Cleissom/eclipse-workspace/riscv-multicycle/sdram + +#Cria biblioteca do projeto +vlib work + +#compila projeto: todos os aquivo. Ordem é importante +vcom sdram_controller.vhd ./sim/mti_pkg.vhd ./sim/mt48lc8m16a2.vhd testbench_sdram.vhd + +#Simula +vsim -t ps work.testbench_sdram + +#Mosta forma de onda +view wave + +add wave -height 15 -divider "SDRAM" +add wave -label clk_sdram /clk_sdram +add wave -label chipselect_sdram /chipselect_sdram +add wave -label sdram_addr -radix hex /sdram_addr +add wave -label DRAM_ADDR -radix hex /DRAM_ADDR +add wave -label d_we /d_we +add wave -label sdram_d_rd /sdram_d_rd +add wave -label ddata_w -radix hex /ddata_w +add wave -label sdram_read -radix hex /sdram_read +add wave -label DRAM_DQ -radix hex /DRAM_DQ +add wave -label burst /burst +add wave -label mem_state /sdram_controller/mem_state +add wave -label d_read /sdram_controller/d_read + + +add wave -radix unsigned -label DRAM_ADDR /DRAM_ADDR +add wave -radix unsigned -label DRAM_CS_N /DRAM_CS_N +add wave -radix unsigned -label DRAM_CKE /DRAM_CKE +add wave -radix unsigned -label DRAM_RAS_N /DRAM_RAS_N +add wave -radix unsigned -label DRAM_CAS_N /DRAM_CAS_N +add wave -radix unsigned -label DRAM_WE_N /DRAM_WE_N +add wave -radix unsigned -label DRAM_DQ /DRAM_DQ + +#Simula até um 500ns +run 5000ns + +wave zoomfull +write wave wave.ps \ No newline at end of file diff --git a/peripherals/sdram/testbench_sdram.vhd b/peripherals/sdram/testbench_sdram.vhd new file mode 100644 index 00000000..f08dc31e --- /dev/null +++ b/peripherals/sdram/testbench_sdram.vhd @@ -0,0 +1,133 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity testbench_sdram is +end entity testbench_sdram; + +architecture RTL of testbench_sdram is + signal sdram_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); + signal chipselect_sdram : STD_LOGIC; + signal clk_sdram : STD_LOGIC; + signal rst : STD_LOGIC; + signal d_we : STD_LOGIC; + signal sdram_d_rd : std_logic; + signal ddata_w : STD_LOGIC_VECTOR(31 DOWNTO 0); + signal burst : std_logic; + signal sdram_read : STD_LOGIC_VECTOR(15 DOWNTO 0); + signal waitrequest : std_logic; + signal DRAM_ADDR : std_logic_vector(12 downto 0); + signal DRAM_BA : std_logic_vector(1 downto 0); + signal DRAM_CAS_N : std_logic; + signal DRAM_CKE : std_logic; + signal DRAM_CLK : std_logic; + signal DRAM_CS_N : std_logic; + signal DRAM_DQ : std_logic_vector(15 downto 0); + signal DRAM_DQM : std_logic_vector(1 downto 0); + signal DRAM_RAS_N : std_logic; + signal DRAM_WE_N : std_logic; + +begin + + -- SDRAM instatiation + sdram_controller : entity work.sdram_controller + port map( + address => sdram_addr, + byteenable => "11", + chipselect => chipselect_sdram, + clk => clk_sdram, + clken => '1', + reset => rst, + reset_req => rst, + write => d_we, + read => sdram_d_rd, + writedata => ddata_w, + burst => burst, + -- outputs: + readdata => sdram_read, + waitrequest => waitrequest, + DRAM_ADDR => DRAM_ADDR, + DRAM_BA => DRAM_BA, + DRAM_CAS_N => DRAM_CAS_N, + DRAM_CKE => DRAM_CKE, + DRAM_CLK => DRAM_CLK, + DRAM_CS_N => DRAM_CS_N, + DRAM_DQ => DRAM_DQ, + DRAM_DQM => DRAM_DQM, + DRAM_RAS_N => DRAM_RAS_N, + DRAM_WE_N => DRAM_WE_N + ); + + -- SDRAM model instatiation + sdram : entity work.mt48lc8m16a2 + generic map( + addr_bits => 13 + ) + port map( + Dq => DRAM_DQ, + Addr => DRAM_ADDR, + Ba => DRAM_BA, + Clk => clk_sdram, + Cke => DRAM_CKE, + Cs_n => DRAM_CS_N, + Ras_n => DRAM_RAS_N, + Cas_n => DRAM_CAS_N, + We_n => DRAM_WE_N, + Dqm => DRAM_DQM + ); + + clock_driver : process + constant period : time := 10 ns; + begin + clk_sdram <= '0'; + wait for period / 2; + clk_sdram <= '1'; + wait for period / 2; + end process clock_driver; + + end_gen : process + begin + sdram_addr <= x"00000000"; + chipselect_sdram <= '1'; + rst <= '1'; + d_we <= '0'; + sdram_d_rd <= '0'; + ddata_w <= x"00000004"; + burst <= '0'; + wait for 10 ns; + rst <= '0'; + wait for 200 ns; + burst <= '1'; + wait for 100 ns; + + d_we <= '1'; + ddata_w <= x"00000000"; + sdram_addr <= x"00000000"; + wait for 100 ns; + d_we <= '0'; + wait for 100 ns; + + d_we <= '1'; + ddata_w <= x"00000001"; + sdram_addr <= x"00000001"; + wait for 100 ns; + d_we <= '0'; + wait for 100 ns; + + d_we <= '1'; + ddata_w <= x"00000003"; + sdram_addr <= x"00000003"; + wait for 100 ns; + d_we <= '0'; + wait for 100 ns; + + sdram_d_rd <= '1'; + sdram_addr <= x"00000000"; + wait for 100 ns; + sdram_d_rd <= '1'; + wait for 100 ns; + + wait; + end process; + +end architecture RTL; diff --git a/peripherals/tft/boot_mem.vhd b/peripherals/tft/boot_mem.vhd new file mode 100644 index 00000000..4e5bb8bb --- /dev/null +++ b/peripherals/tft/boot_mem.vhd @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +entity boot_mem is + port(clk : in std_logic; + rst : in std_logic; + rd_en : in std_logic; + rd_data : out unsigned(31 downto 0); + empty : out std_logic + ); +end entity; + +architecture rtl_boot_mem of boot_mem IS + + -- Define the length of the boot memory + -- If you have 54 words in the memory, this number must be 53 + constant mem_lengh : natural := 53; + + type MEM is array (0 to mem_lengh) of unsigned(rd_data'range); + signal ram_block : MEM := (x"00e58000", x"00000001", x"00010100", x"00020700", + x"00031030", x"00040000", x"00080202", x"00090000", + x"000A0000", x"000C0000", x"000D0000", x"000F0000", + x"00100000", x"00110007", x"00120000", x"00130000", + x"FFFF0032", x"001017B0", x"00110007", x"FFFF000A", + x"0012013A", x"FFFF000A", x"00131A00", x"0029000c", + x"FFFF000A", x"00300000", x"00310505", x"00320004", + x"00350006", x"00360707", x"00370105", x"00380002", + x"00390707", x"003C0704", x"003D0807", x"0060A700", + x"00610001", x"006A0000", x"00210000", x"00200000", + x"00800000", x"00810000", x"00820000", x"00830000", + x"00840000", x"00850000", x"00900010", x"00920000", + x"00930003", x"00950110", x"00970000", x"00980000", + x"00070173", x"FFFF0032"); + + signal tail : integer range mem_lengh downto 0; + signal count : integer range mem_lengh downto 0; + signal empty_i : std_logic; + +begin + -- Set the empty flag + empty <= empty_i; + empty_i <= '1' when count = 0 else '0'; + + -- Update the tail pointer on read and pulse valid + proc_tail : process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + tail <= 0; + else + if rd_en = '1' and empty_i = '0' then + tail <= tail + 1; + end if; + + end if; + end if; + end process; + + rd_data <= ram_block(tail); + count <= mem_lengh - tail; + +end architecture; diff --git a/peripherals/tft/controller.vhd b/peripherals/tft/controller.vhd new file mode 100644 index 00000000..730568c1 --- /dev/null +++ b/peripherals/tft/controller.vhd @@ -0,0 +1,76 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity controller is + port( + clk : in std_logic; + reset : in std_logic; + ready : in std_logic; + start : out std_logic; + mux_sel : out std_logic; + empty_1 : in std_logic; + empty_2 : in std_logic; + read_en1 : out std_logic; + read_en2 : out std_logic + ); +end entity; + +architecture rtl_controller of controller is + type state_type is (IDLE, READ, WRITE); + signal state : state_type; +begin + moore : process(clk, reset) is + begin + if (reset = '1') then + state <= WRITE; + + elsif rising_edge(clk) then + case state is + when IDLE => + if (ready = '1') then + state <= READ; + end if; + when READ => + if (empty_1 = '0') then + state <= WRITE; + elsif (empty_2 = '0') then + state <= WRITE; + else + state <= IDLE; + end if; + when WRITE => + state <= IDLE; + end case; + end if; + end process; + + mealy : process(state, empty_1, empty_2) + begin + start <= '0'; + read_en1 <= '0'; + read_en2 <= '0'; + + mux_sel <= '1';-- + + if (empty_1 = '0') then + mux_sel <= '0'; + --elsif (empty_2 = '0') then + --mux_sel <= '1'; + end if; + + case state is + when IDLE => + null; + when READ => + if (empty_1 = '0') then + read_en1 <= '1'; + elsif (empty_2 = '0') then + read_en2 <= '1'; + end if; + when WRITE => + start <= '1'; + end case; + end process; + +end architecture; diff --git a/peripherals/tft/data_mem.vhd b/peripherals/tft/data_mem.vhd new file mode 100644 index 00000000..0b399855 --- /dev/null +++ b/peripherals/tft/data_mem.vhd @@ -0,0 +1,108 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +entity data_mem is + generic( + RAM_WIDTH : natural := 32; + RAM_DEPTH : natural := 320; + HEAD_INIT : natural := 0 + ); + port( + clk : in std_logic; + rst : in std_logic; + wr_en : in std_logic; + wr_data : in unsigned(RAM_WIDTH - 1 downto 0); + rd_en : in std_logic; + rd_data : out unsigned(RAM_WIDTH - 1 downto 0); + empty : out std_logic; + full : out std_logic + ); +end entity; + +architecture rtl_data_mem of data_mem IS + type MEM is array (0 to RAM_DEPTH - 1) of unsigned(wr_data'range); + + signal ram_block : MEM := (others => x"00000000"); + + subtype index_type is integer range ram_block'range; + signal head : index_type; + signal tail : index_type; + + signal empty_i : std_logic; + signal full_i : std_logic; + signal fill_count_i : integer range RAM_DEPTH - 1 downto 0; + + -- Increment and wrap + procedure incr(signal index : inout index_type) is + begin + if index = index_type'high then + index <= index_type'low; + else + index <= index + 1; + end if; + end procedure; + +begin + empty <= empty_i; + full <= full_i; + + -- Set the flags + empty_i <= '1' when fill_count_i = 0 else '0'; + full_i <= '1' when fill_count_i >= RAM_DEPTH - 1 else '0'; + + -- Update the head pointer in write + proc_head : process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + head <= HEAD_INIT; + else + + if wr_en = '1' and full_i = '0' then + incr(head); + end if; + + end if; + end if; + end process; + + -- Update the tail pointer on read and pulse valid + proc_tail : process(clk) + begin + if rising_edge(clk) then + if rst = '1' then + tail <= 0; + else + if rd_en = '1' and empty_i = '0' then + incr(tail); + end if; + + end if; + end if; + end process; + + -- Write to and read from the RAM + proc_ram : process(clk, ram_block, tail) + begin + if rising_edge(clk) then + if wr_en = '1' then + ram_block(head) <= wr_data; + end if; + end if; + rd_data <= ram_block(tail); + end process; + + -- Update the fill count + proc_count : process(head, tail) + begin + if head < tail then + fill_count_i <= head - tail + RAM_DEPTH; + else + fill_count_i <= head - tail; + end if; + end process; + +end architecture; diff --git a/peripherals/tft/decoder.vhd b/peripherals/tft/decoder.vhd new file mode 100644 index 00000000..0018e446 --- /dev/null +++ b/peripherals/tft/decoder.vhd @@ -0,0 +1,111 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity decoder is + port( + clk : in std_logic; + mem_init : in std_logic; + mem_full : in std_logic; + input_a : in unsigned(31 downto 0); + input_b : in unsigned(31 downto 0); + input_c : in unsigned(31 downto 0); + output : out unsigned(31 downto 0); + enable : out std_logic; + rst : out std_logic + ); +end entity; + +architecture rtl_decoder of decoder is + + constant n_block : natural := 3; + type MUX is array (0 to n_block) of unsigned(output'range); + + signal ready : std_logic; + signal color : unsigned(15 downto 0); + signal output_a : unsigned(31 downto 0); + signal output_b : unsigned(31 downto 0); + signal sel : unsigned(7 downto 0); + + signal mux_completed : unsigned(n_block - 1 downto 0); + signal mux_enable : unsigned(n_block - 1 downto 0); + signal mux_output : MUX; + +begin + + controller_inst : entity work.dec_fsm + port map( + clk => clk, + ready => ready, + input_a => input_a, + input_b => input_b, + input_c => input_c, + color => color, + output_a => output_a, + output_b => output_b, + sel => sel + ); + + mux_enable(0) <= '0'; + mux_output(0) <= x"00000000"; + reset_inst : entity work.dec_reset + port map( + clk => clk, + sel => sel, + mem_init => mem_init, + completed => mux_completed(0), + rst => rst + ); + + clean_inst : entity work.dec_clean + generic map( + SIZE_DISPLAY => 76800 + ) + port map( + clk => clk, + sel => sel, + completed => mux_completed(1), + mem_full => mem_full, + color => color, + output => mux_output(1), + write_en => mux_enable(1) + ); + + draw_rect_inst : entity work.dec_rect + generic map( + WIDTH => 240, + HEIGHT => 320 + ) + port map( + clk => clk, + sel => sel, + pos_x => output_a(31 downto 16), + pos_y => output_a(15 downto 0), + len_x => output_b(31 downto 16), + len_y => output_b(15 downto 0), + color => color, + mem_full => mem_full, + write_en => mux_enable(2), + output => mux_output(2), + completed => mux_completed(2) + ); + + output <= mux_output(0) when sel = x"01" else + mux_output(1) when sel = x"02" else + mux_output(2) when sel = x"03" else + mux_output(2) when sel = x"04" else + x"00000000"; + + enable <= mux_enable(0) when sel = x"01" else + mux_enable(1) when sel = x"02" else + mux_enable(2) when sel = x"03" else + mux_enable(2) when sel = x"04" else + '0'; + + ready <= mux_completed(0) when sel = x"01" else + mux_completed(1) when sel = x"02" else + mux_completed(2) when sel = x"03" else + mux_completed(2) when sel = x"04" else + '0'; + +end architecture; diff --git a/peripherals/tft/decoder/dec_clean.vhd b/peripherals/tft/decoder/dec_clean.vhd new file mode 100644 index 00000000..926fc5a2 --- /dev/null +++ b/peripherals/tft/decoder/dec_clean.vhd @@ -0,0 +1,102 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dec_clean is + generic( + SIZE_DISPLAY : natural := 76800 + ); + port( + clk : in std_logic; + sel : in unsigned(7 downto 0); + mem_full : in std_logic; + color : in unsigned(15 downto 0); + output : out unsigned(31 downto 0); + write_en : out std_logic; + completed : out std_logic + ); +end entity; + +architecture rtl_dec_clean of dec_clean is + type state_type is (IDLE, CLEAN_X, CLEAN_Y, CLEAN_RGB, FULL_VERIFY, FINISHED); + signal state : state_type; + signal next_state : state_type; + signal start : std_logic; + signal start_i : std_logic; +begin + + start <= '1' when sel = x"02" else '0'; + + start_detect : process(start, state) is + begin + if (state = CLEAN_X) then + start_i <= '0'; + elsif rising_edge(start) then + if state = IDLE then + start_i <= '1'; + elsif state = FINISHED then + start_i <= '1'; + end if; + end if; + end process; + + moore : process(clk, start_i) is + variable count_size : natural := 0; + begin + if start_i = '1' then + state <= CLEAN_X; + -- if rising_edge(start) then + -- state <= CLEAN_X; + elsif rising_edge(clk) then + case state is + when IDLE => + null; + when CLEAN_X => + state <= FULL_VERIFY; + next_state <= CLEAN_Y; + when CLEAN_Y => + state <= FULL_VERIFY; + next_state <= CLEAN_RGB; + when CLEAN_RGB => + state <= FULL_VERIFY; + next_state <= CLEAN_RGB; + count_size := count_size + 1; + if (count_size >= SIZE_DISPLAY) then + count_size := 0; + state <= FINISHED; + end if; + when FULL_VERIFY => + if (mem_full = '0') then + state <= next_state; + end if; + when FINISHED => + null; + end case; + end if; + end process; + + mealy : process(state, color) + begin + write_en <= '0'; + completed <= '0'; + output <= (others => '0'); + case state is + when IDLE => + null; + when CLEAN_X => + output <= x"00200000"; + write_en <= '1'; + when CLEAN_Y => + output <= x"00210000"; + write_en <= '1'; + when CLEAN_RGB => + output <= x"0022" & color; + write_en <= '1'; + when FULL_VERIFY => + write_en <= '0'; + when FINISHED => + completed <= '1'; + end case; + end process; + +end architecture; diff --git a/peripherals/tft/decoder/dec_fsm.vhd b/peripherals/tft/decoder/dec_fsm.vhd new file mode 100644 index 00000000..7327700c --- /dev/null +++ b/peripherals/tft/decoder/dec_fsm.vhd @@ -0,0 +1,117 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dec_fsm is + port( + clk : in std_logic; + ready : in std_logic; + input_a : in unsigned(31 downto 0); + input_b : in unsigned(31 downto 0); + input_c : in unsigned(31 downto 0); + color : out unsigned(15 downto 0); + output_a : out unsigned(31 downto 0); + output_b : out unsigned(31 downto 0); + sel : out unsigned(7 downto 0) + ); +end entity; + +architecture rtl_dec_fsm of dec_fsm is + type state_type is (IDLE, RESET, CLEAN, SQR, RECT, FINISHED); + signal state : state_type; + signal start : std_logic; + signal start_i : std_logic; + signal cmd : unsigned(15 downto 0); + + signal active : std_logic := '0'; + +begin + start <= input_a(31); + cmd <= '0' & input_a(30 downto 16); + + start_detect : process(start, active) is + begin + if active = '0' then + if rising_edge(start) then + start_i <= '1'; + end if; + else + start_i <= '0'; + end if; + end process; + + process(start_i) is + begin + if rising_edge(start_i) then + color <= input_a(15 downto 0); + output_a <= input_b; + output_b <= input_c; + end if; + end process; + + moore : process(clk, start_i) is + begin + if start_i = '1' then + state <= IDLE; + active <= '1'; + + elsif rising_edge(clk) then + case state is + when IDLE => + if (start = '1') then + active <= '1'; + case cmd is + when x"7FFF" => state <= RESET; + when x"0001" => state <= CLEAN; + when x"0002" => state <= SQR; + when x"0003" => state <= RECT; + when others => null; + end case; + end if; + when RESET => + if (ready = '1') then + active <= '0'; + state <= FINISHED; + end if; + when CLEAN => + if (ready = '1') then + active <= '0'; + state <= FINISHED; + end if; + when RECT => + if (ready = '1') then + active <= '0'; + state <= FINISHED; + end if; + when SQR => + if (ready = '1') then + active <= '0'; + state <= FINISHED; + end if; + when FINISHED => + state <= FINISHED; + active <= '0'; + end case; + end if; + end process; + + mealy : process(state) + begin + sel <= (others => '0'); + case state is + when IDLE => + null; + when RESET => + sel <= x"01"; + when CLEAN => + sel <= x"02"; + when SQR => + sel <= x"03"; + when RECT => + sel <= x"04"; + when FINISHED => + null; + end case; + end process; + +end architecture; diff --git a/peripherals/tft/decoder/dec_rect.vhd b/peripherals/tft/decoder/dec_rect.vhd new file mode 100644 index 00000000..1f1d228d --- /dev/null +++ b/peripherals/tft/decoder/dec_rect.vhd @@ -0,0 +1,260 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +entity dec_rect is + generic( + WIDTH : natural := 240; + HEIGHT : natural := 320 + ); + port( + clk : in std_logic; + sel : in unsigned(7 downto 0); + mem_full : in std_logic; + color : in unsigned(15 downto 0); + pos_x : in unsigned(15 downto 0); + pos_y : in unsigned(15 downto 0); + len_x : in unsigned(15 downto 0); + len_y : in unsigned(15 downto 0); + write_en : out std_logic; + output : out unsigned(31 downto 0); + completed : out std_logic + ); +end entity; + +architecture rtl_dec_rect of dec_rect IS + type state_type is (IDLE, INIT, FULL_VERIFY, FINISHED, + SET_ADDRESS_X, SET_ADDRESS_Y, SET_DIR_1, SET_DIR_2, SET_DIR_3, SET_DIR_4, + WRITE_X1, WRITE_X2, WRITE_Y1, WRITE_Y2); + + signal state : state_type; + signal next_state : state_type; + + signal x : unsigned(15 downto 0) := (others => '0'); + signal y : unsigned(15 downto 0) := (others => '0'); + + signal len_x_cmp : unsigned(15 downto 0); + signal len_y_cmp : unsigned(15 downto 0); + signal len_y_i : unsigned(15 downto 0); + + signal count_x : unsigned(15 downto 0) := (others => '0'); + signal count_y : unsigned(15 downto 0) := (others => '0'); + + signal start : std_logic; + signal start_i : std_logic; + +begin + + start <= '1' when sel = x"03" + else '1' when sel = x"04" + else '0'; + + len_y_i <= len_x when sel = x"03" else len_y; + + len_x_cmp <= x + len_x; + len_y_cmp <= y + len_y_i; + + limit_verify : process(pos_x, len_x, len_x_cmp, len_y, len_y_cmp, pos_y, x, y) + begin + if (pos_x > WIDTH) then + x <= x"0000"; + else + x <= pos_x; + end if; + + if (pos_y > HEIGHT) then + y <= x"0000"; + else + y <= pos_y; + end if; + + if (len_x_cmp > WIDTH) then + count_x <= WIDTH - x; + else + count_x <= len_x; + end if; + + if (len_y_cmp > HEIGHT) then + count_y <= HEIGHT - y; + else + count_y <= len_y; + end if; + end process; + + start_detect : process(start, state) is + begin + if (state = INIT) then + start_i <= '0'; + elsif rising_edge(start) then + if state = IDLE then + start_i <= '1'; + elsif state = FINISHED then + start_i <= '1'; + end if; + end if; + end process; + + moore : process(clk, start_i) is + variable count : natural := 0; + begin + if start_i = '1' then + state <= INIT; + -- if rising_edge(start) then + -- state <= INIT; + elsif rising_edge(clk) then + case state is + when IDLE => + null; + + when INIT => + state <= FULL_VERIFY; + next_state <= SET_ADDRESS_X; + count := 0; + + when SET_ADDRESS_X => + state <= FULL_VERIFY; + next_state <= SET_ADDRESS_Y; + + when SET_ADDRESS_Y => + state <= FULL_VERIFY; + next_state <= SET_DIR_1; + + when SET_DIR_1 => + state <= FULL_VERIFY; + next_state <= WRITE_X1; + + when WRITE_X1 => + count := count + 1; + if (count < count_x) then + state <= FULL_VERIFY; + next_state <= WRITE_X1; + else + state <= FULL_VERIFY; + next_state <= SET_DIR_2; + count := 0; + end if; + + when SET_DIR_2 => + state <= FULL_VERIFY; + next_state <= WRITE_Y1; + + when WRITE_Y1 => + count := count + 1; + if (count < count_y) then + state <= FULL_VERIFY; + next_state <= WRITE_Y1; + else + state <= FULL_VERIFY; + next_state <= SET_DIR_3; + count := 0; + end if; + + when SET_DIR_3 => + state <= FULL_VERIFY; + next_state <= WRITE_X2; + + when WRITE_X2 => + count := count + 1; + if (count < count_x) then + state <= FULL_VERIFY; + next_state <= WRITE_X2; + else + state <= FULL_VERIFY; + next_state <= SET_DIR_4; + count := 0; + end if; + + when SET_DIR_4 => + state <= FULL_VERIFY; + next_state <= WRITE_Y2; + + when WRITE_Y2 => + count := count + 1; + if (count < count_y) then + state <= FULL_VERIFY; + next_state <= WRITE_Y2; + else + state <= FULL_VERIFY; + next_state <= FINISHED; + count := 0; + end if; + + when FULL_VERIFY => + if (mem_full = '0') then + state <= next_state; + else + state <= FULL_VERIFY; + end if; + + when FINISHED => + state <= FINISHED; + end case; + + end if; + + end process; + + mealy : process(state, color, x, y) + begin + completed <= '0'; + write_en <= '1'; + output <= (others => '0'); + case state is + + when IDLE => + write_en <= '0'; + + when INIT => + write_en <= '0'; + + when SET_ADDRESS_X => + output(31 downto 16) <= x"0020"; + output(15 downto 0) <= x; + + when SET_ADDRESS_Y => + output(31 downto 16) <= x"0021"; + output(15 downto 0) <= y; + + when SET_DIR_1 => + output <= x"00031030"; + + when WRITE_X1 => + output(31 downto 16) <= x"0022"; + output(15 downto 0) <= color; + + when SET_DIR_2 => + output <= x"00031038"; + + when WRITE_Y1 => + output(31 downto 16) <= x"0022"; + output(15 downto 0) <= color; + + when SET_DIR_3 => + output <= x"00031000"; + + when WRITE_X2 => + output(31 downto 16) <= x"0022"; + output(15 downto 0) <= color; + + when SET_DIR_4 => + output <= x"00031008"; + + when WRITE_Y2 => + output(31 downto 16) <= x"0022"; + output(15 downto 0) <= color; + + when FULL_VERIFY => + write_en <= '0'; + output <= x"00000000"; + + when FINISHED => + write_en <= '0'; + output <= x"00000000"; + completed <= '1'; + + end case; + end process; + +end architecture; diff --git a/peripherals/tft/decoder/dec_reset.vhd b/peripherals/tft/decoder/dec_reset.vhd new file mode 100644 index 00000000..ea833103 --- /dev/null +++ b/peripherals/tft/decoder/dec_reset.vhd @@ -0,0 +1,72 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dec_reset is + port( + clk : in std_logic; + sel : in unsigned(7 downto 0); + mem_init : in std_logic; + completed : out std_logic; + rst : out std_logic + ); +end entity; + +architecture rtl_dec_reset of dec_reset is + type state_type is (IDLE, RESET, FINISHED); + + signal state : state_type; + signal start : std_logic; + signal start_i : std_logic; +begin + + start <= '1' when sel = x"01" else '0'; + + start_detect : process(start, state) is + begin + if(state = RESET) then + start_i <= '0'; + elsif rising_edge(start) then + if state = IDLE then + start_i <= '1'; + elsif state = FINISHED then + start_i <= '1'; + end if; + end if; + end process; + + moore : process(clk, start_i) is + begin + if start_i = '1' then + state <= RESET; +-- if rising_edge(start) then +-- state <= RESET; + elsif rising_edge(clk) then + case state is + when IDLE => + if (mem_init = '1') then + state <= FINISHED; + end if; + when RESET => + state <= IDLE; + when FINISHED => + null; + end case; + end if; + end process; + + mealy : process(state) + begin + completed <= '0'; + rst <= '0'; + case state is + when IDLE => + null; + when RESET => + rst <= '1'; + when FINISHED => + completed <= '1'; + end case; + end process; + +end architecture; diff --git a/peripherals/tft/greybox_tmp/cbx_args.txt b/peripherals/tft/greybox_tmp/cbx_args.txt new file mode 100644 index 00000000..fd2d6720 --- /dev/null +++ b/peripherals/tft/greybox_tmp/cbx_args.txt @@ -0,0 +1,58 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=100 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=1 +CLK0_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=100000 +INTENDED_DEVICE_FAMILY="MAX 10" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_UNUSED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_UNUSED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_UNUSED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +WIDTH_CLOCK=5 +DEVICE_FAMILY="MAX 10" +CBX_AUTO_BLACKBOX=ALL +inclk +inclk +clk diff --git a/peripherals/tft/mux32.vhd b/peripherals/tft/mux32.vhd new file mode 100644 index 00000000..512c950e --- /dev/null +++ b/peripherals/tft/mux32.vhd @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity mux32 is + port( + input_a : in unsigned(31 downto 0); + input_b : in unsigned(31 downto 0); + sel : in std_logic; + output : out unsigned(31 downto 0) + ); +end entity; + +architecture rtl of mux32 is +begin + + output <= input_a when sel = '0' else input_b; + +end architecture; diff --git a/peripherals/tft/tb/tb_boot_mem.do b/peripherals/tft/tb/tb_boot_mem.do new file mode 100644 index 00000000..a4d84694 --- /dev/null +++ b/peripherals/tft/tb/tb_boot_mem.do @@ -0,0 +1,40 @@ +# ============================================================================ +# Name : tb_divisor.do +# Author : Renan Augusto Starke +# Version : 0.1 +# Copyright : Renan, Departamento de Eletrônica, Florianópolis, IFSC +# Description : Exemplo de script de compilação ModelSim para divisor de clock +# ============================================================================ + + +#Cria biblioteca do projeto +vlib work + +#compila projeto: todos os aquivo. Ordem é importante +vcom boot_mem.vhd tb/tb_boot_mem.vhd + +#Simula (work é o diretorio, testbench é o nome da entity) +vsim -t ns work.testbench_boot_mem + +#Mosta forma de onda +view wave + +#Adiciona ondas específicas +# -radix: binary, hex, dec +# -label: nome da forma de onda +add wave -height 15 -divider "BOOT_MEM" +add wave -radix binary -label clk /clk +add wave -radix binary -label rst /rst +add wave -radix binary -label enable /rd_en +add wave -radix binary -label empty /empty +add wave -radix hex -label data /rd_data + +add wave -height 15 -divider "INTERNAL" +add wave -radix dec -label tail /boot_mem_inst/tail +add wave -radix hex -label ram_block /boot_mem_inst/ram_block + +#Simula até um 200ns +run 200ns + +wave zoomfull +write wave wave.ps diff --git a/peripherals/tft/tb/tb_boot_mem.vhd b/peripherals/tft/tb/tb_boot_mem.vhd new file mode 100644 index 00000000..f2a33e41 --- /dev/null +++ b/peripherals/tft/tb/tb_boot_mem.vhd @@ -0,0 +1,57 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +------------------------------------- +entity testbench_boot_mem is +end entity testbench_boot_mem; +------------------------------ + +architecture stimulus_boot_mem of testbench_boot_mem is + + signal clk : std_logic; + signal rst : std_logic; + signal rd_en : std_logic; + signal rd_data : unsigned(31 downto 0); + signal empty : std_logic; + +begin + boot_mem_inst : entity work.boot_mem + port map( + clk => clk, + rst => rst, + rd_en => rd_en, + rd_data => rd_data, + empty => empty + ); + + clock : process + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end process; + + process + begin + + rst <= '1'; + rd_en <= '0'; + + wait for 2 ns; + rst <= '0'; + + wait for 4 ns; + rd_en <= '1'; + + wait for 130 ns; + rst <= '1'; + + wait for 2 ns; + rst <= '0'; + + + wait; + end process; + +end architecture; diff --git a/peripherals/tft/tb/tb_data_mem.do b/peripherals/tft/tb/tb_data_mem.do new file mode 100644 index 00000000..429eb0b6 --- /dev/null +++ b/peripherals/tft/tb/tb_data_mem.do @@ -0,0 +1,45 @@ +# ============================================================================ +# Name : tb_divisor.do +# Author : Renan Augusto Starke +# Version : 0.1 +# Copyright : Renan, Departamento de Eletrônica, Florianópolis, IFSC +# Description : Exemplo de script de compilação ModelSim para divisor de clock +# ============================================================================ + + +#Cria biblioteca do projeto +vlib work + +#compila projeto: todos os aquivo. Ordem é importante +vcom data_mem.vhd tb/tb_data_mem.vhd + +#Simula (work é o diretorio, testbench é o nome da entity) +vsim -t ns work.testbench_data_mem + +#Mosta forma de onda +view wave + +#Adiciona ondas específicas +# -radix: binary, hex, dec +# -label: nome da forma de onda +add wave -height 15 -divider "DATA_MEM" +add wave -radix binary -label clk /clk +add wave -radix binary -label rst /rst +add wave -radix binary -label wr_en /wr_en +add wave -radix binary -label rd_en /rd_en +add wave -radix binary -label empty /empty +add wave -radix binary -label full /full +add wave -radix hex -label wr_data /wr_data +add wave -radix hex -label rd_data /rd_data + + +add wave -height 15 -divider "INTERNAL" +add wave -radix dec -label tail /data_mem_inst/tail +add wave -radix dec -label head /data_mem_inst/head +add wave -radix hex -label ram_block /data_mem_inst/ram_block + +#Simula até um 60ns +run 60ns + +wave zoomfull +write wave wave.ps diff --git a/peripherals/tft/tb/tb_data_mem.vhd b/peripherals/tft/tb/tb_data_mem.vhd new file mode 100644 index 00000000..f148771d --- /dev/null +++ b/peripherals/tft/tb/tb_data_mem.vhd @@ -0,0 +1,68 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +------------------------------------- +entity testbench_data_mem is +end entity testbench_data_mem; +------------------------------ + +architecture stimulus_data_mem of testbench_data_mem is + + signal clk : std_logic; + signal rst : std_logic; + signal wr_en : std_logic; + signal wr_data : unsigned(31 downto 0); + signal rd_en : std_logic; + signal rd_data : unsigned(31 downto 0); + signal empty : std_logic; + signal full : std_logic; + + +begin + data_mem_inst : entity work.data_mem + generic map( + RAM_WIDTH => 32, + RAM_DEPTH => 15, + HEAD_INIT => 9 + ) + port map( + clk => clk, + rst => rst, + wr_en => wr_en, + wr_data => wr_data, + rd_en => rd_en, + rd_data => rd_data, + empty => empty, + full => full + ); + + clock : process + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end process; + + process + begin + + wr_en <= '0'; + wr_data <= x"000FF000"; + rd_en <= '0'; + + rst <= '1'; + wait for 10 ns; + + rst <= '0'; + rd_en <= '1'; + + wait for 10 ns; + + wr_en <= '1'; + + + wait; + end process; + +end architecture; diff --git a/peripherals/tft/tb/tb_dec_rect.do b/peripherals/tft/tb/tb_dec_rect.do new file mode 100644 index 00000000..ced25182 --- /dev/null +++ b/peripherals/tft/tb/tb_dec_rect.do @@ -0,0 +1,58 @@ +# ============================================================================ +# Name : tb_divisor.do +# Author : Renan Augusto Starke +# Version : 0.1 +# Copyright : Renan, Departamento de Eletrônica, Florianópolis, IFSC +# Description : Exemplo de script de compilação ModelSim para divisor de clock +# ============================================================================ + + +#Cria biblioteca do projeto +vlib work + +#compila projeto: todos os aquivo. Ordem é importante +vcom decoder/dec_rect.vhd data_mem.vhd tb/tb_dec_rect.vhd + +#Simula (work é o diretorio, testbench é o nome da entity) +vsim -t ns work.testbench_dec_rect + +#Mosta forma de onda +view wave + +#Adiciona ondas específicas +# -radix: binary, hex, dec +# -label: nome da forma de onda +add wave -height 15 -divider "DRAW_RECT" + +add wave -radix hex -label pos_x /pos_x +add wave -radix hex -label pos_y /pos_y +add wave -radix hex -label len_x /len_x +add wave -radix hex -label len_y /len_y +add wave -radix hex -label color /color + +add wave -radix binary -label clk /clk +add wave -radix hex -label sel /sel +add wave -radix binary -label full /full +add wave -radix binary -label wr_en /wr_en +add wave -radix hex -label wr_data /wr_data +add wave -radix binary -label compltd /completed + +#Sinais internos do processo +add wave -height 15 -divider "INTERNAL DRAW_RECT" +add wave -radix dec -label state /dec_rect_inst/state +#add wave -radix dec -label state /dec_rect_inst/state_transation/count + +add wave -height 15 -divider "DATA_MEM" +add wave -radix binary -label rst /rst +add wave -radix binary -label rd_en /rd_en +add wave -radix binary -label empty /empty +add wave -radix hex -label rd_data /rd_data +add wave -radix hex -label ram_block /data_mem_inst/ram_block + + + +#Simula até um 200ns +run 100ns + +wave zoomfull +write wave wave.ps diff --git a/peripherals/tft/tb/tb_dec_rect.vhd b/peripherals/tft/tb/tb_dec_rect.vhd new file mode 100644 index 00000000..ba30fc3f --- /dev/null +++ b/peripherals/tft/tb/tb_dec_rect.vhd @@ -0,0 +1,96 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +------------------------------------- +entity testbench_dec_rect is +end entity testbench_dec_rect; +------------------------------ + +architecture stimulus_dec_rect of testbench_dec_rect is + + signal clk : std_logic; + signal sel : unsigned(7 downto 0); + signal pos_x : unsigned(15 downto 0); + signal pos_y : unsigned(15 downto 0); + signal len_x : unsigned(15 downto 0); + signal len_y : unsigned(15 downto 0); + signal color : unsigned(15 downto 0); + signal full : std_logic; + signal wr_en : std_logic; + signal wr_data : unsigned(31 downto 0); + signal completed : std_logic; + signal rst : std_logic; + signal rd_en : std_logic; + signal rd_data : unsigned(31 downto 0); + signal empty : std_logic; + +begin + + data_mem_inst : entity work.data_mem + generic map( + RAM_WIDTH => 32, + RAM_DEPTH => 20, + HEAD_INIT => 10 + ) + port map( + clk => clk, + rst => rst, + wr_en => wr_en, + wr_data => wr_data, + rd_en => rd_en, + rd_data => rd_data, + empty => empty, + full => full + ); + + dec_rect_inst : entity work.dec_rect + generic map( + WIDTH => 240, + HEIGHT => 320 + ) + port map( + clk => clk, + sel => sel, + mem_full => full, + color => color, + pos_x => pos_x, + pos_y => pos_y, + len_x => len_x, + len_y => len_y, + write_en => wr_en, + output => wr_data, + completed => completed + ); + + pos_x <= x"000A"; + pos_y <= x"000A"; + + len_x <= x"0002"; + len_y <= x"0002"; + + color <= x"FAFA"; + + clock : process + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end process; + + process + begin + sel <= x"00"; + rst <= '1'; + rd_en <= '0'; + wait for 3 ns; + rst <= '0'; + sel <= x"04"; + + wait for 50 ns; + rd_en <= '1'; + + wait; + end process; + +END ARCHITECTURE; diff --git a/peripherals/tft/tb/tb_generator.do b/peripherals/tft/tb/tb_generator.do new file mode 100644 index 00000000..e2278cde --- /dev/null +++ b/peripherals/tft/tb/tb_generator.do @@ -0,0 +1,50 @@ +#Cria biblioteca do projeto +vlib work + +#compila projeto: todos os aquivo. Ordem é importante +vcom block_controller.vhd block_reset.vhd draw_rect.vhd block_clean.vhd generator.vhd tb_generator.vhd + +#Simula (work é o diretorio, testbench é o nome da entity) +vsim -t ns work.testbench_generator + +#Mosta forma de onda +view wave + +#Adiciona ondas específicas +# -radix: binary, hex, dec +# -label: nome da forma de onda + +add wave -height 15 -divider "GENERATOR" + +add wave -radix binary -label clk /clk +add wave -radix binary -label mem_full /mem_full +add wave -radix binary -label mem_init /mem_init +add wave -radix hex -label input_a /input_a +add wave -radix hex -label input_b /input_b +add wave -radix hex -label input_c /input_c +add wave -radix binary -label rst /rst +add wave -radix hex -label output /output + +#Como mostrar sinais internos do processo +add wave -radix hex -label sel /dut/sel +add wave -radix bin -label completed /dut/mux_completed +add wave -radix binary -label enable /dut/enable + +add wave -height 15 -divider "CONTROLLER" +add wave -radix dec -label start /dut/controller_inst/start +add wave -radix hex -label cmd /dut/controller_inst/cmd +add wave -radix hex -label state /dut/controller_inst/state +add wave -radix hex -label ready /dut/controller_inst/ready + +add wave -height 15 -divider "RESET" +add wave -radix hex -label state_R /dut/reset_inst/state + +add wave -height 15 -divider "CLEAN" +add wave -radix hex -label state_C /dut/clean_inst/state +add wave -radix dec -label count /dut/clean_inst/state_transation/count_size + +#Simula até um 50ns +run 500us + +wave zoomfull +write wave wave.ps diff --git a/peripherals/tft/tb/tb_generator.vhd b/peripherals/tft/tb/tb_generator.vhd new file mode 100644 index 00000000..00b48222 --- /dev/null +++ b/peripherals/tft/tb/tb_generator.vhd @@ -0,0 +1,81 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity testbench_generator is +end entity; + +architecture stimulus_generator of testbench_generator is + + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal mem_full : std_logic := '0'; + signal mem_init : std_logic := '0'; + signal input_a : unsigned(31 downto 0) := x"00000000"; + signal input_b : unsigned(31 downto 0) := x"00000000"; + signal input_c : unsigned(31 downto 0) := x"00000000"; + signal output : unsigned(31 downto 0); + signal rst : std_logic; + signal write_en : std_logic := '0'; + +begin + + dut : entity work.generator + port map( + clk => clk, + mem_init => mem_init, + mem_full => mem_full, + input_a => input_a, + input_b => input_b, + input_c => input_c, + output => output, + enable => write_en, + rst => rst + ); + + -- clock + process + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end process; + + -- execução + process + begin + wait for 1 ns; + + reset <= '1'; + wait for 1 ns; + + reset <= '0'; + wait for 2 ns; + + input_a <= x"FFFF0000"; + wait until (rst = '1'); + mem_init <= '0'; + + wait for 2 ns; + input_a <= x"7FFF0000"; + + wait for 10 ns; + input_a <= x"80010000"; + + wait for 5 ns; + input_a <= x"00010000"; + + wait for 100 ns; + mem_init <= '1'; + + wait for 10 ns; + input_a <= x"8001FFFF"; + + wait for 5 ns; + input_a <= x"0001FFFF"; + + wait; + end process; + +end architecture; diff --git a/peripherals/tft/tb/tb_write_fsm.do b/peripherals/tft/tb/tb_write_fsm.do new file mode 100644 index 00000000..7da64cf9 --- /dev/null +++ b/peripherals/tft/tb/tb_write_fsm.do @@ -0,0 +1,35 @@ +#Cria biblioteca do projeto +vlib work + +#compila projeto: todos os aquivo. Ordem é importante +vcom fsm_cmd_data.vhd tb_write_fsm.vhd + +#Simula (work é o diretorio, testbench é o nome da entity) +vsim -t ns work.testbench + +#Mosta forma de onda +view wave + +#Adiciona ondas específicas +# -radix: binary, hex, dec +# -label: nome da forma de onda +add wave -radix binary /clk +add wave -radix binary /reset +add wave -radix binary /start +add wave -radix binary /ready +add wave -radix hex /data +add wave -radix hex /output +add wave -radix binary /cs +add wave -radix binary /rs +add wave -radix binary /wr + + +#Como mostrar sinais internos do processo +add wave -radix dec /dut/state +add wave -radix hex /dut/data_cp + +#Simula até um 50ns +run 1000ns + +wave zoomfull +write wave wave.ps diff --git a/peripherals/tft/tb/tb_write_fsm.vhd b/peripherals/tft/tb/tb_write_fsm.vhd new file mode 100644 index 00000000..ba6adfd4 --- /dev/null +++ b/peripherals/tft/tb/tb_write_fsm.vhd @@ -0,0 +1,70 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity testbench_write_fsm is +end entity testbench_write_fsm; + +architecture stimulus_write_fsm of testbench_write_fsm is + + signal clk : std_logic := '0'; + signal reset : std_logic := '0'; + signal start : std_logic := '0'; + signal ready : std_logic := '0'; + signal data : unsigned(31 downto 0) := x"89ABCDEF"; + signal output : unsigned(7 downto 0) := x"00"; + signal cs : std_logic := '0'; + signal rs : std_logic := '0'; + signal wr : std_logic := '0'; + +begin + + dut : entity work.write_cdmdata + port map( + clk => clk, + reset => reset, + start => start, + ready => ready, + data => data, + output => output, + cs => cs, + rs => rs, + wr => wr + ); + + -- clock + process + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end process; + + -- execução + process + begin + wait for 4 ns; + reset <= '1'; + wait for 10 ns; + reset <= '0'; + wait for 5 ns; + start <= '1'; + wait for 10 ns; + start <= '0'; + wait for 300 ns; + data <= x"FFFF0010"; + wait for 1 ns; + start <= '1'; + wait for 10 ns; + start <= '0'; + wait for 300 ns; + data <= x"12345678"; + wait for 1 ns; + start <= '1'; + wait for 10 ns; + start <= '0'; + wait; + end process; + +end architecture stimulus_write_fsm; diff --git a/peripherals/tft/tb_tft.do b/peripherals/tft/tb_tft.do new file mode 100644 index 00000000..d0ba19df --- /dev/null +++ b/peripherals/tft/tb_tft.do @@ -0,0 +1,71 @@ +# ============================================================================ +# Name : tb_divisor.do +# Author : Renan Augusto Starke +# Version : 0.1 +# Copyright : Renan, Departamento de Eletrônica, Florianópolis, IFSC +# Description : Exemplo de script de compilação ModelSim para divisor de clock +# ============================================================================ + + +#Cria biblioteca do projeto +vlib work + +#compila projeto: todos os aquivo. Ordem é importante +vcom mux32.vhd boot_mem.vhd data_mem.vhd decoder/dec_clean.vhd decoder/dec_fsm.vhd decoder/dec_rect.vhd decoder/dec_reset.vhd decoder.vhd writer.vhd controller.vhd tft.vhd tb_tft.vhd + +#Simula (work é o diretorio, testbench é o nome da entity) +vsim -t ns work.testbench_tft_controller + +#Mosta forma de onda +view wave + +#Adiciona ondas específicas +# -radix: binary, hex, dec +# -label: nome da forma de onda +add wave -height 15 -divider "INPUT" +add wave -radix hex -label input_a /input_a +add wave -radix hex -label input_b /input_b +add wave -radix hex -label input_c /input_c + +add wave -height 15 -divider "GENERATOR" +add wave -radix hex -label state /tft_inst/decoder_inst/controller_inst/state +add wave -radix bin -label start /tft_inst/decoder_inst/controller_inst/start + +add wave -height 15 -divider "BOOT_MEM" +add wave -radix binary -label clk /clk +add wave -radix binary -label reset /tft_inst/reset +add wave -radix binary -label rd_en_1 /tft_inst/rd_en_1 +add wave -radix binary -label empty_1 /tft_inst/empty_1 +add wave -radix dec -label tail_1 /tft_inst/boot_mem_inst/tail + +add wave -height 15 -divider "DATA_MEM" +add wave -radix binary -label wr_en /tft_inst/wr_en_2 +add wave -radix hex -label input /tft_inst/wr_data_2 +add wave -radix binary -label full /tft_inst/full_2 + +add wave -height 15 -divider "WRITE_OUT" +add wave -radix bin -label ready /tft_inst/write_cdmdata_inst/ready +add wave -radix hex -label start /tft_inst/start +add wave -radix hex -label state_write /tft_inst/write_cdmdata_inst/state +add wave -radix hex -label output /output + +add wave -height 15 -divider "FSM_CTR" +add wave -radix hex -label state_fsm /tft_inst/fsm_inst/state +add wave -radix hex -label read_en1 /tft_inst/fsm_inst/read_en1 +add wave -radix hex -label read_en2 /tft_inst/fsm_inst/read_en2 + +add wave -height 15 -divider "MUX" +add wave -radix hex -label rd_data_1 /tft_inst/rd_data_1 +add wave -radix hex -label mux_out /tft_inst/mux_out +add wave -radix bin -label mux_sel /tft_inst/mux_sel + +add wave -height 15 -divider "DATA_MEM" +add wave -radix hex -label data /tft_inst/data_mem_inst/ram_block +#Como mostrar sinais internos do processo + + +#Simula até um 60ns +run 100us + +wave zoomfull +write wave wave.ps diff --git a/peripherals/tft/tb_tft.vhd b/peripherals/tft/tb_tft.vhd new file mode 100644 index 00000000..ae3710af --- /dev/null +++ b/peripherals/tft/tb_tft.vhd @@ -0,0 +1,77 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +------------------------------------- +entity testbench_tft_controller is +end entity testbench_tft_controller; +------------------------------ + +architecture stimulus_tft_controller of testbench_tft_controller is + + signal clk : std_logic; + + signal input_a : unsigned(31 downto 0); + signal input_b : unsigned(31 downto 0); + signal input_c : unsigned(31 downto 0); + + signal output : unsigned(7 downto 0); + signal cs : std_logic := '0'; + signal rs : std_logic := '0'; + signal wr : std_logic := '0'; + +begin + + tft_inst : entity work.tft + port map( + clk => clk, + input_a => input_a, + input_b => input_b, + input_c => input_c, + output => output, + cs => cs, + rs => rs, + wr => wr + ); + + clock : process + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end process; + + process + begin + input_a <= x"00000000"; + input_b <= x"00000000"; + input_c <= x"00000000"; + wait for 10 ns; + + input_a <= x"ffffffff"; + input_b <= x"00000000"; + input_c <= x"00000000"; + wait for 20 us; + + input_a <= x"00000000"; + input_b <= x"00000000"; + input_c <= x"00000000"; + wait for 100 ns; + +-- input_a <= x"8001fafa"; +-- input_b <= x"00000000"; +-- input_c <= x"00000000"; +-- wait for 100 ns; + + input_a <= x"00000000"; + input_b <= x"00000000"; + input_c <= x"00000000"; + wait for 100 ns; + + input_a <= x"8003ffff"; + input_b <= x"00020002"; + input_c <= x"00020002"; + wait; + end process; + +end architecture stimulus_tft_controller; diff --git a/peripherals/tft/tft.vhd b/peripherals/tft/tft.vhd new file mode 100644 index 00000000..6157d717 --- /dev/null +++ b/peripherals/tft/tft.vhd @@ -0,0 +1,116 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tft is + port( + clk : in std_logic; + input_a : in unsigned(31 downto 0); + input_b : in unsigned(31 downto 0); + input_c : in unsigned(31 downto 0); + output : out unsigned(7 downto 0); + cs : out std_logic; + rs : out std_logic; + wr : out std_logic; + rst : out std_logic + ); +end entity; + +architecture rtl_tft of tft is + + signal reset : std_logic; + + signal rd_en_1 : std_logic; + signal rd_data_1 : unsigned(31 downto 0); + signal empty_1 : std_logic; + + signal wr_en_2 : std_logic; + signal wr_data_2 : unsigned(31 downto 0); + signal rd_en_2 : std_logic; + signal rd_data_2 : unsigned(31 downto 0); + signal empty_2 : std_logic; + signal full_2 : std_logic; + + signal start : std_logic; + signal ready : std_logic; + + signal mux_sel : std_logic; + signal mux_out : unsigned(31 downto 0); + +begin + rst <= not reset; + + mux32_inst : entity work.mux32 + port map( + input_a => rd_data_1, + input_b => rd_data_2, + sel => mux_sel, + output => mux_out + ); + + boot_mem_inst : entity work.boot_mem + port map( + clk => clk, + rst => reset, + rd_en => rd_en_1, + rd_data => rd_data_1, + empty => empty_1 + ); + + data_mem_inst : entity work.data_mem + generic map( + RAM_WIDTH => 32, + RAM_DEPTH => 320, + HEAD_INIT => 0 + ) + port map( + clk => clk, + rst => reset, + wr_en => wr_en_2, + wr_data => wr_data_2, + rd_en => rd_en_2, + rd_data => rd_data_2, + empty => empty_2, + full => full_2 + ); + + write_cdmdata_inst : entity work.writer + port map( + clk => clk, + reset => reset, + start => start, + ready => ready, + input => mux_out, + output => output, + cs => cs, + rs => rs, + wr => wr + ); + + fsm_inst : entity work.controller + port map( + clk => clk, + reset => reset, + ready => ready, + start => start, + mux_sel => mux_sel, + empty_1 => empty_1, + empty_2 => empty_2, + read_en1 => rd_en_1, + read_en2 => rd_en_2 + ); + + decoder_inst : entity work.decoder + port map( + clk => clk, + mem_init => empty_1, + mem_full => full_2, + input_a => input_a, + input_b => input_b, + input_c => input_c, + output => wr_data_2, + enable => wr_en_2, + rst => reset + ); + +end architecture; diff --git a/peripherals/tft/vish_stacktrace.vstf b/peripherals/tft/vish_stacktrace.vstf new file mode 100644 index 00000000..34b9bc23 --- /dev/null +++ b/peripherals/tft/vish_stacktrace.vstf @@ -0,0 +1,86 @@ +# Current time Mon Dec 2 12:54:40 2019 +# ModelSim - Intel FPGA Edition Stack Trace +# Program = vish +# Id = "10.5b" +# Version = "2016.10" +# Date = "Oct 5 2016" +# Platform = linuxpe +# 0 0x0832f8c7: 'wlfUncompress + 0xe7' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 1 0x082c6bf7: 'wlfiFileNextBuffer + 0x7f7' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 2 0x083bc9d2: 'wlfiScan + 0x1d32' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 3 0x082ce7b6: 'wlfiGetDataRange + 0x1a6' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 4 0x082b5468: '' +# 5 0x08229870: '' +# 6 0x0822c0ba: 'ts_print_item + 0xfa' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 7 0x0821030e: 'tree_iterate + 0x16e' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 8 0x0824131e: 'ts_print_tree + 0x8ce' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 9 0x082a72f4: '' +# 10 0x082aec06: '' +# 11 0x084cc41d: '' +# 12 0x0851503a: '' +# 13 0x0851d9dc: '' +# 14 0x085169cc: '' +# 15 0x0855ca25: 'TclObjInterpProcCore + 0x115' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 16 0x0855cfc2: 'TclObjInterpProc + 0x62' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 17 0x084cc41d: '' +# 18 0x084cded6: '' +# 19 0x084ce4c5: 'Tcl_EvalEx + 0x35' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 20 0x084ce92c: 'TclEvalObjEx + 0x3fc' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 21 0x084d5992: '' +# 22 0x084cc41d: '' +# 23 0x0851503a: '' +# 24 0x0855ca25: 'TclObjInterpProcCore + 0x115' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 25 0x0855cfc2: 'TclObjInterpProc + 0x62' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 26 0x084cc41d: '' +# 27 0x0851503a: '' +# 28 0x0855ca25: 'TclObjInterpProcCore + 0x115' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 29 0x0855cfc2: 'TclObjInterpProc + 0x62' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 30 0x084cc41d: '' +# 31 0x084cc9f2: 'Tcl_EvalObjv + 0x52' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 32 0x0854406e: '' +# 33 0x084cc41d: '' +# 34 0x084cded6: '' +# 35 0x084ce4c5: 'Tcl_EvalEx + 0x35' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 36 0x084ce507: 'Tcl_Eval + 0x37' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 37 0x084cebc0: 'Tcl_GlobalEval + 0x30' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 38 0x0819a2b2: '' +# 39 0x0819b990: '' +# 40 0x0819c0e8: 'tclprim_do + 0x2d8' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 41 0x084c7901: 'TclInvokeStringCommand + 0x71' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 42 0x084cc41d: '' +# 43 0x0851503a: '' +# 44 0x0851d9dc: '' +# 45 0x084ce59c: 'TclEvalObjEx + 0x6c' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 46 0x084cea36: 'Tcl_EvalObjEx + 0x36' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 47 0x084cc41d: '' +# 48 0x0851503a: '' +# 49 0x0855ca25: 'TclObjInterpProcCore + 0x115' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 50 0x0855cfc2: 'TclObjInterpProc + 0x62' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 51 0x084cc41d: '' +# 52 0x0851503a: '' +# 53 0x0855ca25: 'TclObjInterpProcCore + 0x115' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 54 0x0855cfc2: 'TclObjInterpProc + 0x62' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 55 0x084cc41d: '' +# 56 0x0851503a: '' +# 57 0x0855ca25: 'TclObjInterpProcCore + 0x115' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 58 0x0855cfc2: 'TclObjInterpProc + 0x62' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 59 0x084cc41d: '' +# 60 0x0851503a: '' +# 61 0x0855ca25: 'TclObjInterpProcCore + 0x115' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 62 0x0855cfc2: 'TclObjInterpProc + 0x62' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 63 0x084cc41d: '' +# 64 0x084cded6: '' +# 65 0x084ce4c5: 'Tcl_EvalEx + 0x35' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 66 0x084ce92c: 'TclEvalObjEx + 0x3fc' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 67 0x084d5992: '' +# 68 0x084cc41d: '' +# 69 0x0851503a: '' +# 70 0x0851d9dc: '' +# 71 0x084ce59c: 'TclEvalObjEx + 0x6c' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 72 0x084cea36: 'Tcl_EvalObjEx + 0x36' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/linuxaloem/vish' +# 73 0xf7fc4eac: 'Itcl_EvalMemberCode + 0x3cc' in '/home/fbroering/intelFPGA_lite/18.1/modelsim_ase/bin/../linux/itcl3.4/libitcl3.4.so' +# 74 0x09da466b: '' +# 75 0x0946c09b: '' +# 76 0xfffffffb: '' +# End of Stack Trace + diff --git a/peripherals/tft/writer.vhd b/peripherals/tft/writer.vhd new file mode 100644 index 00000000..fe925556 --- /dev/null +++ b/peripherals/tft/writer.vhd @@ -0,0 +1,235 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity writer is + port( + clk : in std_logic; + reset : in std_logic; + start : in std_logic; + input : in unsigned(31 downto 0); + output : out unsigned(7 downto 0); + ready : out std_logic; + cs : out std_logic; + rs : out std_logic; + wr : out std_logic + ); +end entity; + +architecture RTL_writer of writer is + type state_type is (IDLE, FINISH, DELAY_COUNT, + CS_LOW, CS_HIGH, RS_LOW, RS_HIGH, DELAY, WR_LOW, WR_HIGH, + LCD_CMD_HIGH, LCD_CMD_LOW, LCD_DATA_HIGH, LCD_DATA_LOW + ); + signal state : state_type; + signal state_out : state_type; + signal count : unsigned(31 downto 0); + signal count_cmp : unsigned(31 downto 0); + + -- Define the adjust of delay_ms, based on clock + -- ADJ must be clk/1000 + constant ADJ : natural := 100; + +begin + + state_transation : process(clk, reset) is + begin + if (reset = '1') then + state <= IDLE; + count <= (others => '0'); + elsif rising_edge(clk) then + case state is + when IDLE => + if start = '1' then + if (input(31 downto 16) = x"FFFF") then + state <= DELAY_COUNT; + else + state <= CS_LOW; + end if; + end if; + when DELAY_COUNT => + count_cmp <= input(15 downto 0) * ADJ; + if (count = count_cmp) then + state <= FINISH; + else + count <= count + 1; + end if; + when CS_LOW => + state <= RS_LOW; + when CS_HIGH => + state <= FINISH; + when RS_LOW => + state <= LCD_CMD_HIGH; + when RS_HIGH => + state <= LCD_DATA_HIGH; + when DELAY => + state <= WR_LOW; + when WR_LOW => + state <= WR_HIGH; + when WR_HIGH => + if (state_out = LCD_CMD_HIGH) then + state <= LCD_CMD_LOW; + elsif (state_out = LCD_CMD_LOW) then + state <= RS_HIGH; + elsif (state_out = LCD_DATA_HIGH) then + state <= LCD_DATA_LOW; + elsif (state_out = LCD_DATA_LOW) then + state <= CS_HIGH; + end if; + when LCD_CMD_HIGH => + state_out <= LCD_CMD_HIGH; + state <= DELAY; + when LCD_CMD_LOW => + state_out <= LCD_CMD_LOW; + state <= DELAY; + when LCD_DATA_HIGH => + state_out <= LCD_DATA_HIGH; + state <= DELAY; + when LCD_DATA_LOW => + state_out <= LCD_DATA_LOW; + state <= DELAY; + when FINISH => + count <= (others => '0'); + state <= IDLE; + end case; + end if; + end process; + + mealy_moore : process(state, state_out, input) + begin + case state is + when IDLE => + ready <= '1'; + + output <= (others => '0'); + cs <= '1'; + rs <= '1'; + wr <= '1'; + when FINISH => + ready <= '1'; + + output <= (others => '0'); + cs <= '1'; + rs <= '1'; + wr <= '1'; + when DELAY_COUNT => + ready <= '0'; + + output <= (others => '0'); + cs <= '1'; + rs <= '1'; + wr <= '1'; + when CS_LOW => + ready <= '0'; + cs <= '0'; + + output <= (others => '0'); + rs <= '1'; + wr <= '1'; + when CS_HIGH => + cs <= '1'; + + ready <= '0'; + output <= (others => '0'); + rs <= '1'; + wr <= '1'; + when RS_LOW => + rs <= '0'; + + ready <= '0'; + output <= (others => '0'); + cs <= '0'; + wr <= '1'; + when RS_HIGH => + rs <= '1'; + + ready <= '0'; + output <= (others => '0'); + cs <= '0'; + wr <= '1'; + when DELAY => + + ready <= '0'; + cs <= '0'; + wr <= '1'; + if (state_out = LCD_CMD_HIGH) then + rs <= '0'; + output <= input(31 downto 24); + elsif (state_out = LCD_CMD_LOW) then + rs <= '0'; + output <= input(23 downto 16); + elsif (state_out = LCD_DATA_HIGH) then + rs <= '1'; + output <= input(15 downto 8); + else + output <= input(7 downto 0); + rs <= '1'; + end if; + when WR_LOW => + wr <= '0'; + + ready <= '0'; + cs <= '0'; + if (state_out = LCD_CMD_HIGH) then + rs <= '0'; + output <= input(31 downto 24); + elsif (state_out = LCD_CMD_LOW) then + rs <= '0'; + output <= input(23 downto 16); + elsif (state_out = LCD_DATA_HIGH) then + rs <= '1'; + output <= input(15 downto 8); + else + output <= input(7 downto 0); + rs <= '1'; + end if; + when WR_HIGH => + wr <= '1'; + + ready <= '0'; + cs <= '0'; + if (state_out = LCD_CMD_HIGH) then + rs <= '0'; + output <= input(31 downto 24); + elsif (state_out = LCD_CMD_LOW) then + rs <= '0'; + output <= input(23 downto 16); + elsif (state_out = LCD_DATA_HIGH) then + rs <= '1'; + output <= input(15 downto 8); + else + output <= input(7 downto 0); + rs <= '1'; + end if; + when LCD_CMD_HIGH => + output <= input(31 downto 24); + + ready <= '0'; + cs <= '0'; + rs <= '0'; + wr <= '1'; + when LCD_CMD_LOW => + output <= input(23 downto 16); + + ready <= '0'; + cs <= '0'; + rs <= '0'; + wr <= '1'; + when LCD_DATA_HIGH => + output <= input(15 downto 8); + + ready <= '0'; + cs <= '0'; + rs <= '1'; + wr <= '1'; + when LCD_DATA_LOW => + output <= input(7 downto 0); + + ready <= '0'; + cs <= '0'; + rs <= '1'; + wr <= '1'; + end case; + end process; + +end architecture; diff --git a/peripherals/uart/README.md b/peripherals/uart/README.md new file mode 100644 index 00000000..0366d646 --- /dev/null +++ b/peripherals/uart/README.md @@ -0,0 +1,27 @@ +# UART +--- + +O periférico realiza a comunicação UART com um baudrate fixo de 9600. Tanto a transmissão quanto a recepção foram implementados e testados no Kit de desenvolvimento DE-10 Lite. + +É importante ressaltar a síntese da PLL para gerar os clocks utilizados: + + - Output clocks: + - clk c0 em 1 MHz + - clk c1 em 0.00960000 MHz (9600 Hz) + +O periférico feito possui ainda dois pinos que não foram conectados: tx_cmp e rx_cmp. O primeiro indica o término do envio ("tx complete") e o segundo o término da leitura de um byte ("rx complete"). Eles podem ser utilizados no futuro para sincronizar o envio e recepção por pooling. + +## Getting Started (software): + +Para transmissão de um carácter basta utilizar a função UART_write(carácter). + +```// Testing UART - Transmission``` +```UART_write('a');``` +```delay_(1000); // Necessário para não perder sincronia.``` + +Para recepçao de um carácter utilize a função UART_read(). +```// Testint UART - Reception``` +```int x;``` +```x = UART_read();``` +```OUTBUS = x;``` +```delay_(1000); // Necessário para não perder sincronia.``` diff --git a/peripherals/uart/de10_lite.vhd b/peripherals/uart/de10_lite.vhd new file mode 100644 index 00000000..60aa21ea --- /dev/null +++ b/peripherals/uart/de10_lite.vhd @@ -0,0 +1,278 @@ +------------------------------------------------------------------- +-- Name : de0_lite.vhd +-- Author : +-- Version : 0.1 +-- Copyright : Departamento de Eletrônica, Florianópolis, IFSC +-- Description : Projeto base DE10-Lite +------------------------------------------------------------------- +LIBRARY ieee; +USE IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +use work.decoder_types.all; + +entity de10_lite is + generic ( + --! Num of 32-bits memory words + IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes + DMEMORY_WORDS : integer := 1024 --!= 2k (512 * 2) bytes + ); + + + port( + ---------- CLOCK ---------- + ADC_CLK_10: in std_logic; + MAX10_CLK1_50: in std_logic; + MAX10_CLK2_50: in std_logic; + + ----------- SDRAM ------------ + DRAM_ADDR: out std_logic_vector (12 downto 0); + DRAM_BA: out std_logic_vector (1 downto 0); + DRAM_CAS_N: out std_logic; + DRAM_CKE: out std_logic; + DRAM_CLK: out std_logic; + DRAM_CS_N: out std_logic; + DRAM_DQ: inout std_logic_vector(15 downto 0); + DRAM_LDQM: out std_logic; + DRAM_RAS_N: out std_logic; + DRAM_UDQM: out std_logic; + DRAM_WE_N: out std_logic; + + ----------- SEG7 ------------ + HEX0: out std_logic_vector(7 downto 0); + HEX1: out std_logic_vector(7 downto 0); + HEX2: out std_logic_vector(7 downto 0); + HEX3: out std_logic_vector(7 downto 0); + HEX4: out std_logic_vector(7 downto 0); + HEX5: out std_logic_vector(7 downto 0); + + ----------- KEY ------------ + KEY: in std_logic_vector(1 downto 0); + + ----------- LED ------------ + LEDR: out std_logic_vector(9 downto 0); + + ----------- SW ------------ + SW: in std_logic_vector(9 downto 0); + + ----------- VGA ------------ + VGA_B: out std_logic_vector(3 downto 0); + VGA_G: out std_logic_vector(3 downto 0); + VGA_HS: out std_logic; + VGA_R: out std_logic_vector(3 downto 0); + VGA_VS: out std_logic; + + ----------- Accelerometer ------------ + GSENSOR_CS_N: out std_logic; + GSENSOR_INT: in std_logic_vector(2 downto 1); + GSENSOR_SCLK: out std_logic; + GSENSOR_SDI: inout std_logic; + GSENSOR_SDO: inout std_logic; + + ----------- Arduino ------------ + ARDUINO_IO: inout std_logic_vector(15 downto 0); + ARDUINO_RESET_N: inout std_logic + ); +end entity; + +architecture rtl of de10_lite is + + signal clk : std_logic; + signal rst : std_logic; + + -- Instruction bus signals + signal idata : std_logic_vector(31 downto 0); + signal iaddress : integer range 0 to IMEMORY_WORDS-1 := 0; + signal address : std_logic_vector (9 downto 0); + + -- Data bus signals + signal daddress : integer range 0 to DMEMORY_WORDS-1; + signal ddata_r : std_logic_vector(31 downto 0); + signal ddata_w : std_logic_vector(31 downto 0); + signal dmask : std_logic_vector(3 downto 0); + signal dcsel : std_logic_vector(1 downto 0); + signal d_we : std_logic := '0'; + + signal ddata_r_mem : std_logic_vector(31 downto 0); + signal d_rd : std_logic; + + -- I/O signals + signal input_in : std_logic_vector(31 downto 0); + + -- PLL signals + signal locked_sig : std_logic; + + -- CPU state signals + signal state : cpu_state_t; + + -- UART signals + -- signal clk_in_1M : std_logic; + signal clk_baud9600 : std_logic; + signal data_in : std_logic_vector(7 downto 0); + signal tx_cmp : std_logic; + signal data_out : std_logic_vector(7 downto 0); + signal rx_cmp : std_logic; + + signal csel_uart : std_logic; + +begin + + pll_inst: entity work.pll_quartus + port map( + areset => '0', + inclk0 => MAX10_CLK1_50, + c0 => clk, + c1 => clk_baud9600, + locked => locked_sig + ); + + rst <= SW(9); + + -- Dummy out signals + DRAM_DQ <= ddata_r(15 downto 0); + -- ARDUINO_IO <= ddata_r(31 downto 16); + LEDR(9) <= SW(9); + DRAM_ADDR(9 downto 0) <= address; + + -- IMem shoud be read from instruction and data buses + -- Not enough RAM ports for instruction bus, data bus and in-circuit programming + process(d_rd, dcsel, daddress, iaddress) + begin + if (d_rd = '1') and (dcsel = "00") then + address <= std_logic_vector(to_unsigned(daddress,10)); + else + address <= std_logic_vector(to_unsigned(iaddress,10)); + end if; + end process; + + -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor + iram_quartus_inst: entity work.iram_quartus + port map( + address => address, + byteena => "1111", + clock => clk, + data => (others => '0'), + wren => '0', + q => idata + ); + + -- Data Memory RAM + dmem: entity work.dmemory + generic map( + MEMORY_WORDS => DMEMORY_WORDS + ) + port map( + rst => rst, + clk => clk, + data => ddata_w, + address => daddress, + we => d_we, + csel => dcsel(0), + dmask => dmask, + q => ddata_r_mem + ); + + -- UART instatiation + uart_inst: entity work.uart + port map( + clk_in_1M => clk, + clk_baud => clk_baud9600, + csel => csel_uart, + data_in => data_in, + tx => ARDUINO_IO(1), + tx_cmp => tx_cmp, + data_out => data_out, + rx => ARDUINO_IO(0), + rx_cmp => rx_cmp + ); + + -- Adress space mux ((check sections.ld) -> Data chip select: + -- 0x00000 -> Instruction memory + -- 0x20000 -> Data memory + -- 0x40000 -> Input/Output generic address space + with dcsel select + ddata_r <= idata when "00", + ddata_r_mem when "01", + input_in when "10", + (others => '0') when others; + + -- Softcore instatiation + myRisc: entity work.core + generic map( + IMEMORY_WORDS => IMEMORY_WORDS, + DMEMORY_WORDS => DMEMORY_WORDS + ) + port map( + clk => clk, + rst => rst, + iaddress => iaddress, + idata => idata, + daddress => daddress, + ddata_r => ddata_r, + ddata_w => ddata_w, + d_we => d_we, + d_rd => d_rd, + dcsel => dcsel, + dmask => dmask, + state => state + ); + + -- Output register (Dummy LED blinky) + process(clk, rst) + begin + if rst = '1' then + LEDR(7 downto 0) <= (others => '0'); + HEX0 <= (others => '1'); + HEX1 <= (others => '1'); + HEX2 <= (others => '1'); + HEX3 <= (others => '1'); + HEX4 <= (others => '1'); + HEX5 <= (others => '1'); + csel_uart <= '0'; + else + if rising_edge(clk) then + csel_uart <= '0'; + if (d_we = '1') and (dcsel = "10") then + -- ToDo: Simplify compartors + -- ToDo: Maybe use byte addressing? + -- x"01" (word addressing) is x"04" (byte addressing) + if to_unsigned(daddress, 32)(8 downto 0) = x"01" then + LEDR(7 downto 0) <= ddata_w(7 downto 0); + elsif to_unsigned(daddress, 32)(8 downto 0) = x"02" then + HEX0 <= ddata_w(7 downto 0); + HEX1 <= ddata_w(15 downto 8); + HEX2 <= ddata_w(23 downto 16); + HEX3 <= ddata_w(31 downto 24); + -- HEX4 <= ddata_w(7 downto 0); + -- HEX5 <= ddata_w(7 downto 0); + elsif to_unsigned(daddress, 32)(8 downto 0) = x"03" then + data_in <= ddata_w(7 downto 0); + csel_uart <= ddata_w(8); + end if; + end if; + end if; + end if; + end process; + + + -- Input register + process(clk, rst) + begin + if rst = '1' then + input_in <= (others => '0'); + else + if rising_edge(clk) then + if (d_rd = '1') and (dcsel = "10") then + if to_unsigned(daddress, 32)(8 downto 0) = x"00" then + input_in(4 downto 0) <= SW(4 downto 0); + elsif to_unsigned(daddress, 32)(8 downto 0) = x"04" then + input_in(7 downto 0) <= data_out; + end if; + end if; + end if; + end if; + end process; + + +end; + diff --git a/peripherals/uart/pll/pll_quartus.cmp b/peripherals/uart/pll/pll_quartus.cmp new file mode 100644 index 00000000..9849212e --- /dev/null +++ b/peripherals/uart/pll/pll_quartus.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +component pll_quartus + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/peripherals/uart/pll/pll_quartus.ppf b/peripherals/uart/pll/pll_quartus.ppf new file mode 100644 index 00000000..4d68e582 --- /dev/null +++ b/peripherals/uart/pll/pll_quartus.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/peripherals/uart/pll/pll_quartus.qip b/peripherals/uart/pll/pll_quartus.qip new file mode 100644 index 00000000..bfd6a0e7 --- /dev/null +++ b/peripherals/uart/pll/pll_quartus.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_quartus.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus_inst.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_quartus.ppf"] diff --git a/peripherals/uart/pll/pll_quartus.vhd b/peripherals/uart/pll/pll_quartus.vhd new file mode 100644 index 00000000..61e5a753 --- /dev/null +++ b/peripherals/uart/pll/pll_quartus.vhd @@ -0,0 +1,399 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll_quartus.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 18.1.0 Build 625 09/12/2018 SJ Standard Edition +-- ************************************************************ + + +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll_quartus IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll_quartus; + + +ARCHITECTURE SYN OF pll_quartus IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + locked <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 50, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + clk1_divide_by => 15625, + clk1_duty_cycle => 50, + clk1_multiply_by => 3, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "MAX 10", + lpm_hint => "CBX_MODULE_PREFIX=pll_quartus", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire5, + clk => sub_wire0, + locked => sub_wire3 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "50" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.009600" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.00960000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_quartus.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "15625" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_quartus_inst.vhd TRUE +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/peripherals/uart/pll/pll_quartus_inst.vhd b/peripherals/uart/pll/pll_quartus_inst.vhd new file mode 100644 index 00000000..bee5a286 --- /dev/null +++ b/peripherals/uart/pll/pll_quartus_inst.vhd @@ -0,0 +1,7 @@ +pll_quartus_inst : pll_quartus PORT MAP ( + areset => areset_sig, + inclk0 => inclk0_sig, + c0 => c0_sig, + c1 => c1_sig, + locked => locked_sig + ); diff --git a/peripherals/uart/sint/de10_lite.ipregen.rpt b/peripherals/uart/sint/de10_lite.ipregen.rpt new file mode 100644 index 00000000..72188105 --- /dev/null +++ b/peripherals/uart/sint/de10_lite.ipregen.rpt @@ -0,0 +1,68 @@ +IP Upgrade report for de10_lite +Mon Jul 8 08:47:25 2019 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. IP Upgrade Summary + 3. Successfully Upgraded IP Components + 4. IP Upgrade Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------+ +; IP Upgrade Summary ; ++------------------------------+-------------------------------------------------+ +; IP Components Upgrade Status ; Passed - Mon Jul 8 08:47:25 2019 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; de10_lite ; +; Top-level Entity Name ; de0_lite ; +; Family ; MAX 10 ; ++------------------------------+-------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------+ +; Successfully Upgraded IP Components ; ++-------------+----------------+---------+------------------------+------------------------+------------------------+---------+ +; Entity Name ; Component Name ; Version ; Original Source File ; Generation File Path ; New Source File ; Message ; ++-------------+----------------+---------+------------------------+------------------------+------------------------+---------+ +; pll_quartus ; ALTPLL ; 17.1 ; ../pll/pll_quartus.qip ; ../pll/pll_quartus.vhd ; ../pll/pll_quartus.qip ; ; ++-------------+----------------+---------+------------------------+------------------------+------------------------+---------+ + + ++---------------------+ +; IP Upgrade Messages ; ++---------------------+ +Info (11902): Backing up file "../pll/pll_quartus.vhd" to "../pll/pll_quartus.BAK.vhd" +Info (11837): Started upgrading IP component ALTPLL with file "../pll/pll_quartus.vhd" +Info (11131): Completed upgrading IP component ALTPLL with file "../pll/pll_quartus.vhd" +Info (23030): Evaluation of Tcl script /home/xtarke/Data/Apps/intelFPGA/18.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful +Info: Quartus Prime Shell was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 1065 megabytes + Info: Processing ended: Mon Jul 8 08:47:25 2019 + Info: Elapsed time: 00:00:09 + Info: Total CPU time (on all processors): 00:00:28 + + diff --git a/peripherals/uart/sint/de10_lite.qpf b/peripherals/uart/sint/de10_lite.qpf new file mode 100644 index 00000000..2e37e9d1 --- /dev/null +++ b/peripherals/uart/sint/de10_lite.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition +# Date created = 18:49:34 June 20, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.0" +DATE = "18:49:34 June 20, 2019" + +# Revisions + +PROJECT_REVISION = "de10_lite" diff --git a/peripherals/uart/sint/de10_lite.qsf b/peripherals/uart/sint/de10_lite.qsf new file mode 100644 index 00000000..81c2855e --- /dev/null +++ b/peripherals/uart/sint/de10_lite.qsf @@ -0,0 +1,233 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition +# Date created = 18:49:34 June 20, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# de10_lite_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:49:34 JUNE 20, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name ENABLE_OCT_DONE ON +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name SDC_FILE de10_lite.sdc +set_global_assignment -name VHDL_FILE ../uart.vhd +set_global_assignment -name QIP_FILE ../pll/pll_quartus.qip +set_global_assignment -name VHDL_FILE ../../../alu/alu_types.vhd +set_global_assignment -name VHDL_FILE ../../../alu/alu.vhd +set_global_assignment -name VHDL_FILE ../de10_lite.vhd +set_global_assignment -name VHDL_FILE ../../../alu/m/M_types.vhd +set_global_assignment -name VHDL_FILE ../../../alu/m/M.vhd +set_global_assignment -name VHDL_FILE ../../../memory/dmemory.vhd +set_global_assignment -name VHDL_FILE ../../../memory/iram_quartus.vhd +set_global_assignment -name QIP_FILE ../../../memory/iram_quartus.qip +set_global_assignment -name VHDL_FILE ../../../decoder/iregister.vhd +set_global_assignment -name VHDL_FILE ../../../decoder/decoder_types.vhd +set_global_assignment -name VHDL_FILE ../../../decoder/decoder.vhd +set_global_assignment -name VHDL_FILE ../../../core/core.vhd +set_global_assignment -name VHDL_FILE ../../../registers/register_file.vhd +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/peripherals/uart/sint/de10_lite.sdc b/peripherals/uart/sint/de10_lite.sdc new file mode 100644 index 00000000..7267c16e --- /dev/null +++ b/peripherals/uart/sint/de10_lite.sdc @@ -0,0 +1,86 @@ +#************************************************************** +# This .sdc file is created by Terasic Tool. +# Users are recommended to modify this file to match users logic. +#************************************************************** + +#************************************************************** +# Create Clock +#************************************************************** +create_clock -period "10.0 MHz" [get_ports ADC_CLK_10] +create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50] +create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50] + +#************************************************************** +# Create Generated Clock +#************************************************************** +derive_pll_clocks + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** +derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + + + +#************************************************************** +# Set Load +#************************************************************** + + + diff --git a/peripherals/uart/sint/de10_lite_assignment_defaults.qdf b/peripherals/uart/sint/de10_lite_assignment_defaults.qdf new file mode 100644 index 00000000..d40b50e3 --- /dev/null +++ b/peripherals/uart/sint/de10_lite_assignment_defaults.qdf @@ -0,0 +1,807 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# Date created = 08:39:22 July 08, 2019 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_DO_REPORT_TIMING Off +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V" +set_global_assignment -name TIMING_ANALYZER_REPORT_NUM_WORST_CASE_TIMING_PATHS 100 +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria 10" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Stratix V" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV E" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Arria 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX II" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria II GZ" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone IV GX" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Cyclone V" +set_global_assignment -name MUX_RESTRUCTURE Auto +set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY -value "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000 +set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250 +set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On +set_global_assignment -name PARALLEL_SYNTHESIS On +set_global_assignment -name DSP_BLOCK_BALANCING Auto +set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)" +set_global_assignment -name NOT_GATE_PUSH_BACK On +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off +set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On +set_global_assignment -name IGNORE_CARRY_BUFFERS Off +set_global_assignment -name IGNORE_CASCADE_BUFFERS Off +set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off +set_global_assignment -name IGNORE_LCELL_BUFFERS Off +set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO +set_global_assignment -name IGNORE_SOFT_BUFFERS On +set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off +set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off +set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On +set_global_assignment -name AUTO_GLOBAL_OE_MAX On +set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off +set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut +set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed +set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced +set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area +set_global_assignment -name ALLOW_XOR_GATE_USAGE On +set_global_assignment -name AUTO_LCELL_INSERTION On +set_global_assignment -name CARRY_CHAIN_LENGTH 48 +set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32 +set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48 +set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70 +set_global_assignment -name CASCADE_CHAIN_LENGTH 2 +set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16 +set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4 +set_global_assignment -name AUTO_CARRY_CHAINS On +set_global_assignment -name AUTO_CASCADE_CHAINS On +set_global_assignment -name AUTO_PARALLEL_EXPANDERS On +set_global_assignment -name AUTO_OPEN_DRAIN_PINS On +set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off +set_global_assignment -name AUTO_ROM_RECOGNITION On +set_global_assignment -name AUTO_RAM_RECOGNITION On +set_global_assignment -name AUTO_DSP_RECOGNITION On +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto +set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On +set_global_assignment -name STRICT_RAM_RECOGNITION Off +set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On +set_global_assignment -name FORCE_SYNCH_CLEAR Off +set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off +set_global_assignment -name AUTO_RESOURCE_SHARING Off +set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off +set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off +set_global_assignment -name MAX7000_FANIN_PER_CELL 100 +set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On +set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)" +set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)" +set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off +set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V" +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX" +set_global_assignment -name REPORT_PARAMETER_SETTINGS On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On +set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On +set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone 10 LP" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name 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+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/peripherals/uart/sint/de10_lite_description.txt b/peripherals/uart/sint/de10_lite_description.txt new file mode 100644 index 00000000..e69de29b diff --git a/peripherals/uart/tb_uart.do b/peripherals/uart/tb_uart.do new file mode 100644 index 00000000..7d26ccb6 --- /dev/null +++ b/peripherals/uart/tb_uart.do @@ -0,0 +1,54 @@ +# ============================================================================ +# Name : tb_uart.do +# Author : Renan Augusto Starke +# Version : 0.1 +# Copyright : Renan, Departamento de Eletrnica, Florianpolis, IFSC +# Description : Exemplo de script de compilao ModelSim +# ============================================================================ + + +#Cria biblioteca do projeto +vlib work + +#compila projeto: todos os aquivo. Ordem importante +vcom uart.vhd tb_uart.vhd + +#Simula +vsim -t ns work.tb_uart + +#Mosta forma de onda +view wave + +#Adiciona ondas especficas +# -radix: binary, hex, dec +# -label: nome da forma de onda + +add wave -height 15 -divider "Clocks and Chip Sel." +add wave -radix binary -label clk_in_1M /clk_in_1M +add wave -radix binary -label clk_baud /clk_baud +add wave -radix binary -label csel /csel + +add wave -height 15 -divider "TX" +add wave -radix hex -label data_in /data_in +add wave -radix binary -label to_tx /dut/to_tx +add wave -radix binary -label tx /tx +add wave -radix dec -label cnt_tx /dut/cnt_tx +add wave -radix binary -label tx_cmp /tx_cmp +add wave -radix binary -label state_tx /dut/state_tx + +add wave -height 15 -divider "RX" +add wave -radix binary -label clk_in_1M /clk_in_1M +add wave -radix binary -label clk_baud /clk_baud +add wave -radix binary -label state_rx /dut/state_rx +add wave -radix binary -label to_rx /to_rx +add wave -radix binary -label rx /rx +add wave -radix binary -label from_rx /dut/rx_receive/from_rx +add wave -radix dec -label cnt_rx /dut/cnt_rx +add wave -radix binary -label rx_cmp /rx_cmp +add wave -radix hex -label data_out /data_out + +#Simula at 60ns +run 60ns + +wave zoomfull +write wave wave.ps diff --git a/peripherals/uart/tb_uart.vhd b/peripherals/uart/tb_uart.vhd new file mode 100644 index 00000000..19b935a3 --- /dev/null +++ b/peripherals/uart/tb_uart.vhd @@ -0,0 +1,101 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tb_uart is + generic ( + constant SIZE : integer := 8 + ); + +end entity tb_uart; + +architecture RTL of tb_uart is + + signal clk_1M_state : boolean; + signal clk_in_1M : std_logic; + + signal clk_baud : std_logic; + signal clk_baudState : boolean; + + signal csel : std_logic; + signal data_in : std_logic_vector(SIZE-1 downto 0); + signal tx : std_logic; + signal tx_cmp : std_logic; + + signal data_out : std_logic_vector(SIZE-1 downto 0); + signal rx : std_logic; + signal rx_cmp : std_logic; + signal to_rx : std_logic_vector(7 downto 0); + signal cnt_rx : integer := 0; + +begin + + dut: entity work.uart + generic map( + SIZE => SIZE + ) + port map( + clk_in_1M => clk_in_1M, + clk_baud => clk_baud, + csel => csel, + data_in => data_in, + tx => tx, + tx_cmp => tx_cmp, + data_out => data_out, + rx => rx, + rx_cmp => rx_cmp + ); + + clock_1M: process + begin + clk_in_1M <= '0'; + wait for 1 ns; + for i in 0 to 40 loop + clk_in_1M <= '0'; + clk_1M_state <= FALSE; + wait for 1 ns; + clk_in_1M <= '1'; + clk_1M_state <= TRUE; + wait for 1 ns; + end loop; + wait; + end process; + + clock_baud: process + begin + for i in 0 to 20 loop + clk_baud <= '0'; + clk_baudState <= FALSE; + wait for 2 ns; + clk_baud <= '1'; + clk_baudState <= TRUE; + wait for 2 ns; + end loop; + wait; + end process; + + transmitt: process + begin + data_in <= x"61"; + csel <= '1'; + wait until clk_1M_state; + wait; + end process; + + receive: process + begin + to_rx <= x"61"; + rx <= '1'; + wait until clk_1M_state; + rx <= '0'; -- Start bit + wait until clk_1M_state; + for i in 0 to 7 loop + rx <= (to_rx(cnt_rx)); + cnt_rx <= cnt_rx + 1; + wait until clk_baudState; + end loop; + rx <= '1'; -- Stop bit + wait; + end process; + +end architecture RTL; diff --git a/peripherals/uart/testbench.vhd b/peripherals/uart/testbench.vhd new file mode 100644 index 00000000..3fa1a295 --- /dev/null +++ b/peripherals/uart/testbench.vhd @@ -0,0 +1,264 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.decoder_types.all; + +entity testbench is + generic ( + --! Num of 32-bits memory words + IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes + DMEMORY_WORDS : integer := 1024; --!= 2k (512 * 2) bytes + constant SIZE : integer := 8 -- 8 bytes UART package + ); + port( + ----------- SEG7 ------------ + HEX0: out std_logic_vector(7 downto 0); + HEX1: out std_logic_vector(7 downto 0); + HEX2: out std_logic_vector(7 downto 0); + HEX3: out std_logic_vector(7 downto 0); + HEX4: out std_logic_vector(7 downto 0); + HEX5: out std_logic_vector(7 downto 0); + + ----------- SW ------------ + SW: in std_logic_vector(9 downto 0); + + + LEDR: out std_logic_vector(9 downto 0); + + ---------- ARDUINO IO ----- + ARDUINO_IO: inout std_logic_vector(15 downto 0) + ); + + +end entity testbench; + +architecture RTL of testbench is + signal clk : std_logic; + signal rst : std_logic; + + signal idata : std_logic_vector(31 downto 0); + + signal daddress : integer range 0 to DMEMORY_WORDS-1; + signal ddata_r : std_logic_vector(31 downto 0); + signal ddata_w : std_logic_vector(31 downto 0); + signal dmask : std_logic_vector(3 downto 0); + signal dcsel : std_logic_vector(1 downto 0); + signal d_we : std_logic := '0'; + + signal iaddress : integer range 0 to IMEMORY_WORDS-1 := 0; + + signal address : std_logic_vector(9 downto 0); + signal ddata_r_mem : std_logic_vector(31 downto 0); + signal d_rd : std_logic; + + signal input_in : std_logic_vector(31 downto 0); + signal cpu_state : cpu_state_t; + + signal debugString : string(64 downto 1); + + -- UART Signals + signal clk_baud : std_logic; + signal data_in : std_logic_vector(7 downto 0); + signal tx : std_logic; + signal start : std_logic; + signal tx_cmp : std_logic; + signal data_out : std_logic_vector(SIZE-1 downto 0); + signal rx : std_logic; + signal rx_cmp : std_logic; + + signal csel_uart : std_logic; + +begin + + clock_driver : process + constant period : time := 10 ns; + begin + clk <= '0'; + wait for period / 2; + clk <= '1'; + wait for period / 2; + end process clock_driver; + + reset : process is + begin + rst <= '1'; + wait for 5 ns; + rst <= '0'; + wait; + end process reset; + + -- Dummy out signals + -- ARDUINO_IO <= ddata_r(31 downto 16); + +-- imem: component imemory +-- generic map( +-- MEMORY_WORDS => IMEMORY_WORDS +-- ) +-- port map( +-- clk => clk, +-- data => idata, +-- write_address => 0, +-- read_address => iaddress, +-- we => '0', +-- q => idata +-- ); + + -- IMem shoud be read from instruction and data buses + -- Not enough RAM ports for instruction bus, data bus and in-circuit programming + -- with dcsel select + -- address <= std_logic_vector(to_unsigned(daddress,10)) when "01", + -- std_logic_vector(to_unsigned(iaddress,10)) when others; + process(d_rd, dcsel, daddress, iaddress) + begin + if (d_rd = '1') and (dcsel = "00") then + address <= std_logic_vector(to_unsigned(daddress,10)); + else + address <= std_logic_vector(to_unsigned(iaddress,10)); + end if; + end process; + + + -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor + iram_quartus_inst: entity work.iram_quartus + port map( + address => address, + byteena => "1111", + clock => clk, + data => (others => '0'), + wren => '0', + q => idata + ); + + -- UART instatiation + uart_inst: entity work.uart + port map( + clk_in_1M => clk, + clk_baud => clk_baud, + csel => csel_uart, + data_in => data_in, + tx => ARDUINO_IO(1), + tx_cmp => tx_cmp, + data_out => data_out, + rx => ARDUINO_IO(0), + rx_cmp => rx_cmp + ); + + clk_baud <= clk; -- Just for simulation + + -- Data Memory RAM + dmem: entity work.dmemory + generic map( + MEMORY_WORDS => DMEMORY_WORDS + ) + port map( + rst => rst, + clk => clk, + data => ddata_w, + address => daddress, + we => d_we, + csel => dcsel(0), + dmask => dmask, + q => ddata_r_mem + ); + + -- Adress space mux ((check sections.ld) -> Data chip select: + -- 0x00000 -> Instruction memory + -- 0x20000 -> Data memory + -- 0x40000 -> Input/Output generic address space + with dcsel select + ddata_r <= idata when "00", + ddata_r_mem when "01", + input_in when "10", + (others => '0') when others; + + -- Softcore instatiation + myRiscv: entity work.core + generic map( + IMEMORY_WORDS => IMEMORY_WORDS, + DMEMORY_WORDS => DMEMORY_WORDS + ) + port map( + clk => clk, + rst => rst, + iaddress => iaddress, + idata => idata, + daddress => daddress, + ddata_r => ddata_r, + ddata_w => ddata_w, + d_we => d_we, + d_rd => d_rd, + dcsel => dcsel, + dmask => dmask, + state => cpu_state + ); + + + -- Output register (Dummy LED blinky) + process(clk, rst) + begin + if rst = '1' then + LEDR(7 downto 0) <= (others => '0'); + HEX0 <= (others => '1'); + HEX1 <= (others => '1'); + HEX2 <= (others => '1'); + HEX3 <= (others => '1'); + HEX4 <= (others => '1'); + HEX5 <= (others => '1'); + csel_uart <= '0'; + else + if rising_edge(clk) then + csel_uart <= '0'; + if (d_we = '1') and (dcsel = "10") then + -- ToDo: Simplify compartors + -- ToDo: Maybe use byte addressing? + -- x"01" (word addressing) is x"04" (byte addressing) + if to_unsigned(daddress, 32)(8 downto 0) = x"01" then + LEDR(7 downto 0) <= ddata_w(7 downto 0); + elsif to_unsigned(daddress, 32)(8 downto 0) = x"02" then + HEX0 <= ddata_w(7 downto 0); + HEX1 <= ddata_w(15 downto 8); + HEX2 <= ddata_w(23 downto 16); + HEX3 <= ddata_w(31 downto 24); + -- HEX4 <= ddata_w(7 downto 0); + -- HEX5 <= ddata_w(7 downto 0); + elsif to_unsigned(daddress, 32)(8 downto 0) = x"03" then + data_in <= ddata_w(7 downto 0); + csel_uart <= ddata_w(8); + end if; + end if; + end if; + end if; + end process; + + -- Input register + process(clk, rst) + begin + if rst = '1' then + input_in <= (others => '0'); + else + if rising_edge(clk) then + if (d_rd = '1') and (dcsel = "10") then + if to_unsigned(daddress, 32)(8 downto 0) = x"00" then + input_in(4 downto 0) <= SW(4 downto 0); + elsif to_unsigned(daddress, 32)(8 downto 0) = x"04" then + input_in(7 downto 0) <= data_out; + end if; + end if; + end if; + end if; + end process; + + + -- FileOutput DEBUG + debug: entity work.trace_debug + generic map( + MEMORY_WORDS => IMEMORY_WORDS + ) + port map( + pc => iaddress, + data => idata, + inst => debugString + ); + +end architecture RTL; diff --git a/peripherals/uart/uart.vhd b/peripherals/uart/uart.vhd new file mode 100644 index 00000000..ee09783c --- /dev/null +++ b/peripherals/uart/uart.vhd @@ -0,0 +1,155 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity uart is + + port( + clk_in_1M : in std_logic; + clk_baud : in std_logic; + csel : in std_logic; + + data_in : in std_logic_vector(7 downto 0); + tx : out std_logic; + tx_cmp : out std_logic; + + data_out : out std_logic_vector(7 downto 0); + rx : in std_logic; + rx_cmp : out std_logic + ); +end entity uart; + +architecture RTL of uart is + -- Signals for TX + type state_tx_type is (IDLE, MOUNT_BYTE, TRANSMIT); + signal state_tx : state_tx_type := IDLE; + signal cnt_tx : integer := 0; + signal to_tx : std_logic_vector(10 downto 0) := (others => '1'); + signal send_byte : boolean := FALSE; + + -- Signals for RX + type state_rx_type is (IDLE, READ_BYTE); + signal state_rx : state_rx_type := IDLE; + signal cnt_rx : integer := 0; + signal byte_received : boolean := FALSE; +begin + + -------------------- TX -------------------- + + -- Maquina de estado TX: Moore + estado_tx: process(clk_in_1M) is + begin + if rising_edge(clk_in_1M) then + case state_tx is + when IDLE => + if csel = '1' then + state_tx <= MOUNT_BYTE; + else + state_tx <= IDLE; + end if; + when MOUNT_BYTE => + state_tx <= TRANSMIT; + when TRANSMIT => + if (cnt_tx < 10) then + state_tx <= TRANSMIT; + else + state_tx <= IDLE; + end if; + end case; + end if; + end process; + + -- Maquina MEALY: transmission + tx_proc: process(state_tx, data_in) + begin + + tx_cmp <= '0'; + send_byte <= FALSE; + + case state_tx is + when IDLE => + tx_cmp <= '1'; + to_tx <= (others => '1'); + send_byte <= FALSE; + + when MOUNT_BYTE => + to_tx <= "11" & data_in & '0'; + tx_cmp <= '0'; + send_byte <= FALSE; + + when TRANSMIT => + send_byte <= TRUE; + to_tx <= "11" & data_in & '0'; + end case; + + end process; + + tx_send: process(clk_baud, send_byte) + begin + if send_byte = TRUE then + if rising_edge(clk_baud) then + tx <= to_tx(cnt_tx); + cnt_tx <= cnt_tx + 1; + end if; + else + tx <= '1'; + cnt_tx <= 0; + end if; + end process; + + -------------------- RX -------------------- + -- Maquina de estado RX: Moore + estado_rx: process(clk_in_1M) is + begin + if rising_edge(clk_in_1M) then + case state_rx is + when IDLE => + if rx = '0' then + state_rx <= READ_BYTE; + else + state_rx <= IDLE; + end if; + when READ_BYTE => + if (cnt_rx < 10) then + state_rx <= READ_BYTE; + else + state_rx <= IDLE; + end if; + end case; + end if; + end process; + + -- Maquina MEALY: transmission + rx_proc: process(state_rx) + begin + + case state_rx is + when IDLE => + rx_cmp <= '1'; + byte_received <= FALSE; + + when READ_BYTE => + rx_cmp <= '0'; + byte_received <= TRUE; + + end case; + + end process; + + rx_receive: process(clk_baud, byte_received) + variable from_rx : std_logic_vector(9 downto 0); + begin + if byte_received = TRUE then + if rising_edge(clk_baud) then + from_rx(cnt_rx) := rx; + cnt_rx <= cnt_rx + 1; + if cnt_rx = 8 then + data_out <= from_rx(8 downto 1); + end if; + end if; + else + cnt_rx <= 0; + end if; + end process; + +end architecture RTL; diff --git a/peripherals/vga/README.md b/peripherals/vga/README.md new file mode 100644 index 00000000..a3b6ecba --- /dev/null +++ b/peripherals/vga/README.md @@ -0,0 +1,29 @@ +# VGA + +O controlador VGA está padronizado para a resolução 800x600 a 60Hz. +Para alterar a resolução, instanciar o controlador conforme 'timings' dos [Padrões VGA](http://tinyvga.com/vga-timing). +O controlador VGA necessita de uma RAM Dual Channel e de um PLL de 40MHz, conforme esquemático: +![RTL](https://drive.google.com/file/d/1flgcUsC5myYFzawOMX-cEWR_tmpqch94/view?usp=sharing) + +## Integração com o CORE +Para o CORE não gravar duplicado (na RAM de dados e na RAM da VGA), é necessário incluir o código seguinte e ligar os respectivos sinais as memórias: +```vhdl +process(dcsel, d_we) +begin + if dcsel = "11" then + wren_vga <= d_we; -- write to vga + wren_dm <= '0'; + else + wren_vga <= '0'; + wren_dm <= d_we; -- write do data memory + end if; +end process; +``` + +## To Do +Se a memória não suportar dados de um frame inteiro, o controlador irá repetir os dados da memória. Porém, com uma memória de 8kb é possível fazer uma imagem de 90x90 pixels. Os arquivos 'reescale' intentam fazer isso, incrementando o endereço da memória somente quando o pixel está dentro da linha e da coluna, e colocando preto quando estiver fora. + +### Links Úteis +[Controlador VGA VHDL](https://www.digikey.com/eewiki/pages/viewpage.action?pageId=15925278) + + diff --git a/peripherals/vga/RTL/VGA-rtl.png b/peripherals/vga/RTL/VGA-rtl.png new file mode 100644 index 00000000..8bab94a2 Binary files /dev/null and b/peripherals/vga/RTL/VGA-rtl.png differ diff --git a/peripherals/vga/Rescale/hw_image_generator_reescale.vhd b/peripherals/vga/Rescale/hw_image_generator_reescale.vhd new file mode 100644 index 00000000..0414cdd1 --- /dev/null +++ b/peripherals/vga/Rescale/hw_image_generator_reescale.vhd @@ -0,0 +1,34 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY hw_image_generator_reescale IS + GENERIC( + column_size : INTEGER := 90; + row_size : INTEGER := 90 + ); + PORT( + disp_ena : IN STD_LOGIC; --display enable ('1' = display time, '0' = blanking time) + rgb_in : in std_logic_vector(15 downto 0); -- RAM data in + row : in integer; + column : in integer; + red : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); --red magnitude output to R2R + green : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); --green magnitude output to R2R + blue : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0')); --blue magnitude output to R2R +END hw_image_generator_reescale; + +ARCHITECTURE behavior OF hw_image_generator_reescale IS +BEGIN + PROCESS(disp_ena, rgb_in, column, row) + BEGIN + IF (disp_ena /= '0' and column '0'); + green <= (OTHERS => '0'); + blue <= (OTHERS => '0'); + END IF; + + END PROCESS; +END behavior; diff --git a/peripherals/vga/Rescale/vga_addr_rescale.vhd b/peripherals/vga/Rescale/vga_addr_rescale.vhd new file mode 100644 index 00000000..f87084b2 --- /dev/null +++ b/peripherals/vga/Rescale/vga_addr_rescale.vhd @@ -0,0 +1,36 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vga_addr_rescale is + GENERIC( + column_size : INTEGER := 90; + row_size : INTEGER := 90 + ); + port( + rst : in std_logic; + column : in integer; + row : in integer; + addr_rescale : out std_logic_vector(12 downto 0) + ); +end entity vga_addr_rescale; + +architecture RTL of vga_addr_rescale is + +begin + proc : process(column, row, rst) + variable addr_count : INTEGER RANGE 0 TO row_size * column_size := 0; + begin + if rst = '1' then + addr_count := 0; + elsif column = 0 and row= 0 then + addr_count := 0; + elsif row < row_size then + if column < column_size then + addr_count := addr_count + 1; + end if; + end if; + addr_rescale <= Std_logic_vector(To_unsigned(addr_count, addr_rescale'length)); + end process; + +end architecture RTL; diff --git a/peripherals/vga/de10_lite.vhd b/peripherals/vga/de10_lite.vhd new file mode 100644 index 00000000..8466858c --- /dev/null +++ b/peripherals/vga/de10_lite.vhd @@ -0,0 +1,303 @@ +------------------------------------------------------------------- +-- Name : de0_lite.vhd +-- Author : +-- Version : 0.1 +-- Copyright : Departamento de Eletrônica, Florianópolis, IFSC +-- Description : Projeto base DE10-Lite +------------------------------------------------------------------- +LIBRARY ieee; +USE IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; + +use work.decoder_types.all; + +entity de10_lite is + generic ( + --! Num of 32-bits memory words + IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes + DMEMORY_WORDS : integer := 4096 --!= 8k (512 * 2) bytes + ); + + + port ( + ---------- CLOCK ---------- + ADC_CLK_10: in std_logic; + MAX10_CLK1_50: in std_logic; + MAX10_CLK2_50: in std_logic; + + ----------- SDRAM ------------ + DRAM_ADDR: out std_logic_vector (12 downto 0); + DRAM_BA: out std_logic_vector (1 downto 0); + DRAM_CAS_N: out std_logic; + DRAM_CKE: out std_logic; + DRAM_CLK: out std_logic; + DRAM_CS_N: out std_logic; + DRAM_DQ: inout std_logic_vector(15 downto 0); + DRAM_LDQM: out std_logic; + DRAM_RAS_N: out std_logic; + DRAM_UDQM: out std_logic; + DRAM_WE_N: out std_logic; + + ----------- SEG7 ------------ + HEX0: out std_logic_vector(7 downto 0); + HEX1: out std_logic_vector(7 downto 0); + HEX2: out std_logic_vector(7 downto 0); + HEX3: out std_logic_vector(7 downto 0); + HEX4: out std_logic_vector(7 downto 0); + HEX5: out std_logic_vector(7 downto 0); + + ----------- KEY ------------ + KEY: in std_logic_vector(1 downto 0); + + ----------- LED ------------ + LEDR: out std_logic_vector(9 downto 0); + + ----------- SW ------------ + SW: in std_logic_vector(9 downto 0); + + ----------- VGA ------------ + VGA_B: out std_logic_vector(3 downto 0); + VGA_G: out std_logic_vector(3 downto 0); + VGA_HS: out std_logic; + VGA_R: out std_logic_vector(3 downto 0); + VGA_VS: out std_logic; + + ----------- Accelerometer ------------ + GSENSOR_CS_N: out std_logic; + GSENSOR_INT: in std_logic_vector(2 downto 1); + GSENSOR_SCLK: out std_logic; + GSENSOR_SDI: inout std_logic; + GSENSOR_SDO: inout std_logic; + + ----------- Arduino ------------ + ARDUINO_IO: inout std_logic_vector(15 downto 0); + ARDUINO_RESET_N: inout std_logic + ); +end entity; + + + +architecture rtl of de10_lite is + + signal clk : std_logic; + signal rst : std_logic; + + -- Instruction bus signals + signal idata : std_logic_vector(31 downto 0); + signal iaddress : integer range 0 to IMEMORY_WORDS-1 := 0; + signal address : std_logic_vector (9 downto 0); + + -- Data bus signals + signal daddress : integer range 0 to DMEMORY_WORDS-1; + signal ddata_r : std_logic_vector(31 downto 0); + signal ddata_w : std_logic_vector(31 downto 0); + signal dmask : std_logic_vector(3 downto 0); + signal dcsel : std_logic_vector(1 downto 0); + signal d_we : std_logic := '0'; + + signal ddata_r_mem : std_logic_vector(31 downto 0); + signal d_rd : std_logic; + + -- I/O signals + signal input_in : std_logic_vector(31 downto 0); + + -- PLL signals + signal locked_sig : std_logic; + + -- CPU state signals + signal state : cpu_state_t; + + -- VGA Signals + signal clk_vga : STD_LOGIC; + signal disp_ena : STD_LOGIC; + signal addr_vga : std_logic_vector(12 downto 0); + signal rgb_in : std_logic_vector(15 downto 0); + signal wren_dm : std_logic; + signal wren_vga : std_logic; + signal vgaaddrwr : std_logic_vector(12 downto 0); + +begin + + pll_inst: entity work.pll + port map( + areset => rst, + inclk0 => MAX10_CLK1_50, + c0 => clk, + c1 => clk_vga, + locked => locked_sig + ); + + rst <= SW(9); + + -- Dummy out signals + DRAM_DQ <= ddata_r(15 downto 0); + ARDUINO_IO <= ddata_r(31 downto 16); + LEDR(9) <= SW(9); + DRAM_ADDR(9 downto 0) <= address; + + -- IMem shoud be read from instruction and data buses + -- Not enough RAM ports for instruction bus, data bus and in-circuit programming + process(d_rd, dcsel, daddress, iaddress) + begin + if (d_rd = '1') and (dcsel = "00") then + address <= std_logic_vector(to_unsigned(daddress,10)); + else + address <= std_logic_vector(to_unsigned(iaddress,10)); + end if; + end process; + + -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor + iram_quartus_inst: entity work.iram_quartus + port map( + address => address, + byteena => "1111", + clock => clk, + data => (others => '0'), + wren => '0', + q => idata + ); + + process(dcsel, d_we) + begin + if dcsel = "11" then + wren_vga <= d_we; -- write to vga + wren_dm <= '0'; + else + wren_vga <= '0'; + wren_dm <= d_we; -- write do data memory + end if; + end process; + + -- Data Memory RAM + dmem: entity work.dmemory + generic map( + MEMORY_WORDS => DMEMORY_WORDS + ) + port map( + rst => rst, + clk => clk, + data => ddata_w, + address => daddress, + we => wren_dm, + csel => dcsel(0), + dmask => dmask, + q => ddata_r_mem + ); + + vgaaddrwr <= Std_logic_vector(To_unsigned(daddress,13)); + + vgamem : entity work.ram_vga + port map( + data => ddata_w(15 downto 0), + rdaddress => addr_vga, + rdclock => clk_vga, + wraddress => vgaaddrwr, + wrclock => clk, + wren => wren_vga, + q => rgb_in + ); + + vgactrl: entity work.vga_controller + port map( + pixel_clk => clk_vga, + reset => rst, + h_sync => VGA_HS, + v_sync => VGA_VS, + disp_ena => disp_ena, + column => open, + row => open, + addr => addr_vga, + n_blank => open, + n_sync => open + ); + vgaimg: entity work.hw_image_generator + port map( + disp_ena => disp_ena, + rgb_in => rgb_in, + red => VGA_R, + green => VGA_G, + blue => VGA_B + ); + + -- Address space (check sections.ld) and chip select: + -- 0x0000000000 -> 0b000 0000 0000 0000 0000 0000 0000 + -- 0x0002000000 -> 0b010 0000 0000 0000 0000 0000 0000 + -- 0x0004000000 -> 0b100 0000 0000 0000 0000 0000 0000 + -- 0x0006000000 -> 0b110 0000 0000 0000 0000 0000 0000 + with dcsel select + ddata_r <= idata when "00", + ddata_r_mem when "01", + input_in when "10", + (others => '0') when others; + + -- Softcore instatiation + myRisc: entity work.core + generic map( + IMEMORY_WORDS => IMEMORY_WORDS, + DMEMORY_WORDS => DMEMORY_WORDS + ) + port map( + clk => clk, + rst => rst, + iaddress => iaddress, + idata => idata, + daddress => daddress, + ddata_r => ddata_r, + ddata_w => ddata_w, + d_we => d_we, + d_rd => d_rd, + dcsel => dcsel, + dmask => dmask, + state => state + ); + + -- Output register (Dummy LED blinky) + process(clk, rst) + begin + if rst = '1' then + LEDR(3 downto 0) <= (others => '0'); + HEX0 <= (others => '1'); + HEX1 <= (others => '1'); + HEX2 <= (others => '1'); + HEX3 <= (others => '1'); + HEX4 <= (others => '1'); + HEX5 <= (others => '1'); + else + if rising_edge(clk) then + if (d_we = '1') and (dcsel = "10")then + -- ToDo: Simplify compartors + -- ToDo: Maybe use byte addressing? + -- x"01" (word addressing) is x"04" (byte addressing) + if to_unsigned(daddress, 32)(8 downto 0) = x"01" then + LEDR(4 downto 0) <= ddata_w(4 downto 0); + elsif to_unsigned(daddress, 32)(8 downto 0) = x"02" then + HEX0 <= ddata_w(7 downto 0); + HEX1 <= ddata_w(15 downto 8); + HEX2 <= ddata_w(23 downto 16); + HEX3 <= ddata_w(31 downto 24); + -- HEX4 <= ddata_w(7 downto 0); + -- HEX5 <= ddata_w(7 downto 0); + end if; + end if; + end if; + end if; + end process; + + + -- Input register + process(clk, rst) + begin + if rst = '1' then + input_in <= (others => '0'); + else + if rising_edge(clk) then + if (d_rd = '1') and (dcsel = "10") then + input_in(4 downto 0) <= SW(4 downto 0); + end if; + end if; + end if; + end process; + + +end; + diff --git a/peripherals/vga/hw_image_generator.vhd b/peripherals/vga/hw_image_generator.vhd new file mode 100644 index 00000000..35d93abb --- /dev/null +++ b/peripherals/vga/hw_image_generator.vhd @@ -0,0 +1,28 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +ENTITY hw_image_generator IS + PORT( + disp_ena : IN STD_LOGIC; --display enable ('1' = display time, '0' = blanking time) + rgb_in : in std_logic_vector(15 downto 0); -- RAM data in + red : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); --red magnitude output to R2R + green : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0'); --green magnitude output to R2R + blue : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0')); --blue magnitude output to R2R +END hw_image_generator; + +ARCHITECTURE behavior OF hw_image_generator IS +BEGIN + PROCESS(disp_ena, rgb_in) + BEGIN + IF (disp_ena = '1') THEN --display time + red <= rgb_in(3 downto 0); + green <= rgb_in(7 downto 4); + blue <= rgb_in(11 downto 8); + ELSE --blanking time + red <= (OTHERS => '0'); + green <= (OTHERS => '0'); + blue <= (OTHERS => '0'); + END IF; + + END PROCESS; +END behavior; diff --git a/peripherals/vga/pll/pll.cmp b/peripherals/vga/pll/pll.cmp new file mode 100644 index 00000000..a23e8447 --- /dev/null +++ b/peripherals/vga/pll/pll.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +component pll + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/peripherals/vga/pll/pll.ppf b/peripherals/vga/pll/pll.ppf new file mode 100644 index 00000000..e107b0ee --- /dev/null +++ b/peripherals/vga/pll/pll.ppf @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/peripherals/vga/pll/pll.qip b/peripherals/vga/pll/pll.qip new file mode 100644 index 00000000..c051426a --- /dev/null +++ b/peripherals/vga/pll/pll.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/peripherals/vga/pll/pll.vhd b/peripherals/vga/pll/pll.vhd new file mode 100644 index 00000000..ae1d3fda --- /dev/null +++ b/peripherals/vga/pll/pll.vhd @@ -0,0 +1,399 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 18.1.0 Build 625 09/12/2018 SJ Standard Edition +-- ************************************************************ + + +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + c1 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + clk1_divide_by : NATURAL; + clk1_duty_cycle : NATURAL; + clk1_multiply_by : NATURAL; + clk1_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire6_bv(0 DOWNTO 0) <= "0"; + sub_wire6 <= To_stdlogicvector(sub_wire6_bv); + sub_wire2 <= sub_wire0(1); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + c1 <= sub_wire2; + locked <= sub_wire3; + sub_wire4 <= inclk0; + sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 50, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + clk1_divide_by => 5, + clk1_duty_cycle => 50, + clk1_multiply_by => 4, + clk1_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "MAX 10", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_USED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire5, + clk => sub_wire0, + locked => sub_wire3 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "40.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "40.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLK1 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "5" +-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/peripherals/vga/ram_vga.cmp b/peripherals/vga/ram_vga.cmp new file mode 100644 index 00000000..aeebaaf2 --- /dev/null +++ b/peripherals/vga/ram_vga.cmp @@ -0,0 +1,27 @@ +--Copyright (C) 2017 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +component ram_vga + PORT + ( + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + rdclock : IN STD_LOGIC ; + wraddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + wrclock : IN STD_LOGIC := '1'; + wren : IN STD_LOGIC := '0'; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +end component; diff --git a/peripherals/vga/ram_vga.qip b/peripherals/vga/ram_vga.qip new file mode 100644 index 00000000..5e3e965e --- /dev/null +++ b/peripherals/vga/ram_vga.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" +set_global_assignment -name IP_TOOL_VERSION "17.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ram_vga.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_vga.cmp"] diff --git a/peripherals/vga/ram_vga.vhd b/peripherals/vga/ram_vga.vhd new file mode 100644 index 00000000..da6583b1 --- /dev/null +++ b/peripherals/vga/ram_vga.vhd @@ -0,0 +1,198 @@ +-- megafunction wizard: %RAM: 2-PORT% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altsyncram + +-- ============================================================ +-- File Name: ram_vga.vhd +-- Megafunction Name(s): +-- altsyncram +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 17.1.0 Build 590 10/25/2017 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 2017 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.altera_mf_components.all; + +ENTITY ram_vga IS + PORT + ( + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + rdclock : IN STD_LOGIC ; + wraddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0); + wrclock : IN STD_LOGIC := '1'; + wren : IN STD_LOGIC := '0'; + q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) + ); +END ram_vga; + + +ARCHITECTURE SYN OF ram_vga IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0); + +BEGIN + q <= sub_wire0(15 DOWNTO 0); + + altsyncram_component : altsyncram + GENERIC MAP ( + address_aclr_b => "NONE", + address_reg_b => "CLOCK1", + clock_enable_input_a => "BYPASS", + clock_enable_input_b => "BYPASS", + clock_enable_output_b => "BYPASS", + intended_device_family => "MAX 10", + lpm_type => "altsyncram", + numwords_a => 8192, + numwords_b => 8192, + operation_mode => "DUAL_PORT", + outdata_aclr_b => "NONE", + outdata_reg_b => "UNREGISTERED", + power_up_uninitialized => "FALSE", + widthad_a => 13, + widthad_b => 13, + width_a => 16, + width_b => 16, + width_byteena_a => 1 + ) + PORT MAP ( + address_a => wraddress, + address_b => rdaddress, + clock0 => wrclock, + clock1 => rdclock, + data_a => data, + wren_a => wren, + q_b => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" +-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" +-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" +-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" +-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" +-- Retrieval info: PRIVATE: CLRdata NUMERIC "0" +-- Retrieval info: PRIVATE: CLRq NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRrren NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" +-- Retrieval info: PRIVATE: CLRwren NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "1" +-- Retrieval info: PRIVATE: Clock_A NUMERIC "0" +-- Retrieval info: PRIVATE: Clock_B NUMERIC "0" +-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" +-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" +-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" +-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" +-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" +-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" +-- Retrieval info: PRIVATE: MIFfilename STRING "vga.hex" +-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" +-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" +-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" +-- Retrieval info: PRIVATE: REGdata NUMERIC "1" +-- Retrieval info: PRIVATE: REGq NUMERIC "1" +-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGrren NUMERIC "1" +-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" +-- Retrieval info: PRIVATE: REGwren NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" +-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" +-- Retrieval info: PRIVATE: VarWidth NUMERIC "0" +-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" +-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" +-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" +-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" +-- Retrieval info: PRIVATE: enable NUMERIC "0" +-- Retrieval info: PRIVATE: rden NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" +-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192" +-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" +-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" +-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" +-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" +-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13" +-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" +-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]" +-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]" +-- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]" +-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock" +-- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]" +-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock" +-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" +-- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0 +-- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0 +-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0 +-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0 +-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0 +-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 16 0 @q_b 0 0 16 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_vga.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_vga.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_vga.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_vga.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL ram_vga_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/peripherals/vga/sint/de10_lite.ipregen.rpt b/peripherals/vga/sint/de10_lite.ipregen.rpt new file mode 100644 index 00000000..443f4822 --- /dev/null +++ b/peripherals/vga/sint/de10_lite.ipregen.rpt @@ -0,0 +1,68 @@ +IP Upgrade report for de10_lite +Mon Jul 8 14:08:52 2019 +Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. IP Upgrade Summary + 3. Successfully Upgraded IP Components + 4. IP Upgrade Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2018 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details. + + + ++--------------------------------------------------------------------------------+ +; IP Upgrade Summary ; ++------------------------------+-------------------------------------------------+ +; IP Components Upgrade Status ; Passed - Mon Jul 8 14:08:52 2019 ; +; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Standard Edition ; +; Revision Name ; de10_lite ; +; Top-level Entity Name ; de10_lite ; +; Family ; MAX 10 ; ++------------------------------+-------------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; Successfully Upgraded IP Components ; ++-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ +; Entity Name ; Component Name ; Version ; Original Source File ; Generation File Path ; New Source File ; Message ; ++-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ +; pll ; ALTPLL ; 17.1 ; ../pll/pll.qip ; ../pll/pll.vhd ; ../pll/pll.qip ; ; ++-------------+----------------+---------+----------------------+----------------------+-----------------+---------+ + + ++---------------------+ +; IP Upgrade Messages ; ++---------------------+ +Info (11902): Backing up file "../pll/pll.vhd" to "../pll/pll.BAK.vhd" +Info (11837): Started upgrading IP component ALTPLL with file "../pll/pll.vhd" +Info (11131): Completed upgrading IP component ALTPLL with file "../pll/pll.vhd" +Info (23030): Evaluation of Tcl script /home/xtarke/Data/Apps/intelFPGA/18.1/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful +Info: Quartus Prime Shell was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 1072 megabytes + Info: Processing ended: Mon Jul 8 14:08:52 2019 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:28 + + diff --git a/peripherals/vga/sint/de10_lite.qpf b/peripherals/vga/sint/de10_lite.qpf new file mode 100644 index 00000000..2e37e9d1 --- /dev/null +++ b/peripherals/vga/sint/de10_lite.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition +# Date created = 18:49:34 June 20, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "15.0" +DATE = "18:49:34 June 20, 2019" + +# Revisions + +PROJECT_REVISION = "de10_lite" diff --git a/peripherals/vga/sint/de10_lite.qsf b/peripherals/vga/sint/de10_lite.qsf new file mode 100644 index 00000000..2e19a916 --- /dev/null +++ b/peripherals/vga/sint/de10_lite.qsf @@ -0,0 +1,238 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2015 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, the Altera Quartus II License Agreement, +# the Altera MegaCore Function License Agreement, or other +# applicable license agreement, including, without limitation, +# that your use is for the sole purpose of programming logic +# devices manufactured by Altera and sold by Altera or its +# authorized distributors. Please refer to the applicable +# agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition +# Date created = 18:49:34 June 20, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# de10_lite_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M50DAF484C7G +set_global_assignment -name TOP_LEVEL_ENTITY de10_lite +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:49:34 JUNE 20, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name ENABLE_OCT_DONE ON +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_location_assignment PIN_N5 -to ADC_CLK_10 +set_location_assignment PIN_P11 -to MAX10_CLK1_50 +set_location_assignment PIN_N14 -to MAX10_CLK2_50 +set_location_assignment PIN_U17 -to DRAM_ADDR[0] +set_location_assignment PIN_W19 -to DRAM_ADDR[1] +set_location_assignment PIN_V18 -to DRAM_ADDR[2] +set_location_assignment PIN_U18 -to DRAM_ADDR[3] +set_location_assignment PIN_U19 -to DRAM_ADDR[4] +set_location_assignment PIN_T18 -to DRAM_ADDR[5] +set_location_assignment PIN_T19 -to DRAM_ADDR[6] +set_location_assignment PIN_R18 -to DRAM_ADDR[7] +set_location_assignment PIN_P18 -to DRAM_ADDR[8] +set_location_assignment PIN_P19 -to DRAM_ADDR[9] +set_location_assignment PIN_T20 -to DRAM_ADDR[10] +set_location_assignment PIN_P20 -to DRAM_ADDR[11] +set_location_assignment PIN_R20 -to DRAM_ADDR[12] +set_location_assignment PIN_T21 -to DRAM_BA[0] +set_location_assignment PIN_T22 -to DRAM_BA[1] +set_location_assignment PIN_U21 -to DRAM_CAS_N +set_location_assignment PIN_N22 -to DRAM_CKE +set_location_assignment PIN_L14 -to DRAM_CLK +set_location_assignment PIN_U20 -to DRAM_CS_N +set_location_assignment PIN_Y21 -to DRAM_DQ[0] +set_location_assignment PIN_Y20 -to DRAM_DQ[1] +set_location_assignment PIN_AA22 -to DRAM_DQ[2] +set_location_assignment PIN_AA21 -to DRAM_DQ[3] +set_location_assignment PIN_Y22 -to DRAM_DQ[4] +set_location_assignment PIN_W22 -to DRAM_DQ[5] +set_location_assignment PIN_W20 -to DRAM_DQ[6] +set_location_assignment PIN_V21 -to DRAM_DQ[7] +set_location_assignment PIN_P21 -to DRAM_DQ[8] +set_location_assignment PIN_J22 -to DRAM_DQ[9] +set_location_assignment PIN_H21 -to DRAM_DQ[10] +set_location_assignment PIN_H22 -to DRAM_DQ[11] +set_location_assignment PIN_G22 -to DRAM_DQ[12] +set_location_assignment PIN_G20 -to DRAM_DQ[13] +set_location_assignment PIN_G19 -to DRAM_DQ[14] +set_location_assignment PIN_F22 -to DRAM_DQ[15] +set_location_assignment PIN_V22 -to DRAM_LDQM +set_location_assignment PIN_U22 -to DRAM_RAS_N +set_location_assignment PIN_J21 -to DRAM_UDQM +set_location_assignment PIN_V20 -to DRAM_WE_N +set_location_assignment PIN_C14 -to HEX0[0] +set_location_assignment PIN_E15 -to HEX0[1] +set_location_assignment PIN_C15 -to HEX0[2] +set_location_assignment PIN_C16 -to HEX0[3] +set_location_assignment PIN_E16 -to HEX0[4] +set_location_assignment PIN_D17 -to HEX0[5] +set_location_assignment PIN_C17 -to HEX0[6] +set_location_assignment PIN_D15 -to HEX0[7] +set_location_assignment PIN_C18 -to HEX1[0] +set_location_assignment PIN_D18 -to HEX1[1] +set_location_assignment PIN_E18 -to HEX1[2] +set_location_assignment PIN_B16 -to HEX1[3] +set_location_assignment PIN_A17 -to HEX1[4] +set_location_assignment PIN_A18 -to HEX1[5] +set_location_assignment PIN_B17 -to HEX1[6] +set_location_assignment PIN_A16 -to HEX1[7] +set_location_assignment PIN_B20 -to HEX2[0] +set_location_assignment PIN_A20 -to HEX2[1] +set_location_assignment PIN_B19 -to HEX2[2] +set_location_assignment PIN_A21 -to HEX2[3] +set_location_assignment PIN_B21 -to HEX2[4] +set_location_assignment PIN_C22 -to HEX2[5] +set_location_assignment PIN_B22 -to HEX2[6] +set_location_assignment PIN_A19 -to HEX2[7] +set_location_assignment PIN_F21 -to HEX3[0] +set_location_assignment PIN_E22 -to HEX3[1] +set_location_assignment PIN_E21 -to HEX3[2] +set_location_assignment PIN_C19 -to HEX3[3] +set_location_assignment PIN_C20 -to HEX3[4] +set_location_assignment PIN_D19 -to HEX3[5] +set_location_assignment PIN_E17 -to HEX3[6] +set_location_assignment PIN_D22 -to HEX3[7] +set_location_assignment PIN_F18 -to HEX4[0] +set_location_assignment PIN_E20 -to HEX4[1] +set_location_assignment PIN_E19 -to HEX4[2] +set_location_assignment PIN_J18 -to HEX4[3] +set_location_assignment PIN_H19 -to HEX4[4] +set_location_assignment PIN_F19 -to HEX4[5] +set_location_assignment PIN_F20 -to HEX4[6] +set_location_assignment PIN_F17 -to HEX4[7] +set_location_assignment PIN_J20 -to HEX5[0] +set_location_assignment PIN_K20 -to HEX5[1] +set_location_assignment PIN_L18 -to HEX5[2] +set_location_assignment PIN_N18 -to HEX5[3] +set_location_assignment PIN_M20 -to HEX5[4] +set_location_assignment PIN_N19 -to HEX5[5] +set_location_assignment PIN_N20 -to HEX5[6] +set_location_assignment PIN_L19 -to HEX5[7] +set_location_assignment PIN_B8 -to KEY[0] +set_location_assignment PIN_A7 -to KEY[1] +set_location_assignment PIN_A8 -to LEDR[0] +set_location_assignment PIN_A9 -to LEDR[1] +set_location_assignment PIN_A10 -to LEDR[2] +set_location_assignment PIN_B10 -to LEDR[3] +set_location_assignment PIN_D13 -to LEDR[4] +set_location_assignment PIN_C13 -to LEDR[5] +set_location_assignment PIN_E14 -to LEDR[6] +set_location_assignment PIN_D14 -to LEDR[7] +set_location_assignment PIN_A11 -to LEDR[8] +set_location_assignment PIN_B11 -to LEDR[9] +set_location_assignment PIN_C10 -to SW[0] +set_location_assignment PIN_C11 -to SW[1] +set_location_assignment PIN_D12 -to SW[2] +set_location_assignment PIN_C12 -to SW[3] +set_location_assignment PIN_A12 -to SW[4] +set_location_assignment PIN_B12 -to SW[5] +set_location_assignment PIN_A13 -to SW[6] +set_location_assignment PIN_A14 -to SW[7] +set_location_assignment PIN_B14 -to SW[8] +set_location_assignment PIN_F15 -to SW[9] +set_location_assignment PIN_P1 -to VGA_B[0] +set_location_assignment PIN_T1 -to VGA_B[1] +set_location_assignment PIN_P4 -to VGA_B[2] +set_location_assignment PIN_N2 -to VGA_B[3] +set_location_assignment PIN_W1 -to VGA_G[0] +set_location_assignment PIN_T2 -to VGA_G[1] +set_location_assignment PIN_R2 -to VGA_G[2] +set_location_assignment PIN_R1 -to VGA_G[3] +set_location_assignment PIN_N3 -to VGA_HS +set_location_assignment PIN_AA1 -to VGA_R[0] +set_location_assignment PIN_V1 -to VGA_R[1] +set_location_assignment PIN_Y2 -to VGA_R[2] +set_location_assignment PIN_Y1 -to VGA_R[3] +set_location_assignment PIN_N1 -to VGA_VS +set_location_assignment PIN_AB16 -to GSENSOR_CS_N +set_location_assignment PIN_Y14 -to GSENSOR_INT[1] +set_location_assignment PIN_Y13 -to GSENSOR_INT[2] +set_location_assignment PIN_AB15 -to GSENSOR_SCLK +set_location_assignment PIN_V11 -to GSENSOR_SDI +set_location_assignment PIN_V12 -to GSENSOR_SDO +set_location_assignment PIN_AB5 -to ARDUINO_IO[0] +set_location_assignment PIN_AB6 -to ARDUINO_IO[1] +set_location_assignment PIN_AB7 -to ARDUINO_IO[2] +set_location_assignment PIN_AB8 -to ARDUINO_IO[3] +set_location_assignment PIN_AB9 -to ARDUINO_IO[4] +set_location_assignment PIN_Y10 -to ARDUINO_IO[5] +set_location_assignment PIN_AA11 -to ARDUINO_IO[6] +set_location_assignment PIN_AA12 -to ARDUINO_IO[7] +set_location_assignment PIN_AB17 -to ARDUINO_IO[8] +set_location_assignment PIN_AA17 -to ARDUINO_IO[9] +set_location_assignment PIN_AB19 -to ARDUINO_IO[10] +set_location_assignment PIN_AA19 -to ARDUINO_IO[11] +set_location_assignment PIN_Y19 -to ARDUINO_IO[12] +set_location_assignment PIN_AB20 -to ARDUINO_IO[13] +set_location_assignment PIN_AB21 -to ARDUINO_IO[14] +set_location_assignment PIN_AA20 -to ARDUINO_IO[15] +set_location_assignment PIN_F16 -to ARDUINO_RESET_N +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VHDL_FILE ../hw_image_generator.vhd +set_global_assignment -name VHDL_FILE ../vga_controller.vhd +set_global_assignment -name QIP_FILE ../pll/pll.qip +set_global_assignment -name VHDL_FILE ../ram_vga.vhd +set_global_assignment -name QIP_FILE ../ram_vga.qip +set_global_assignment -name VHDL_FILE ../de10_lite.vhd +set_global_assignment -name SDC_FILE de10_lite.sdc +set_global_assignment -name VHDL_FILE ../../../alu/alu_types.vhd +set_global_assignment -name VHDL_FILE ../../../alu/alu.vhd +set_global_assignment -name VHDL_FILE ../../../alu/m/M_types.vhd +set_global_assignment -name VHDL_FILE ../../../alu/m/M.vhd +set_global_assignment -name VHDL_FILE ../../../memory/dmemory.vhd +set_global_assignment -name VHDL_FILE ../../../memory/iram_quartus.vhd +set_global_assignment -name QIP_FILE ../../../memory/iram_quartus.qip +set_global_assignment -name VHDL_FILE ../../../decoder/iregister.vhd +set_global_assignment -name VHDL_FILE ../../../decoder/decoder_types.vhd +set_global_assignment -name VHDL_FILE ../../../decoder/decoder.vhd +set_global_assignment -name VHDL_FILE ../../../core/core.vhd +set_global_assignment -name VHDL_FILE ../../../registers/register_file.vhd + + + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/peripherals/vga/sint/de10_lite.sdc b/peripherals/vga/sint/de10_lite.sdc new file mode 100644 index 00000000..7267c16e --- /dev/null +++ b/peripherals/vga/sint/de10_lite.sdc @@ -0,0 +1,86 @@ +#************************************************************** +# This .sdc file is created by Terasic Tool. +# Users are recommended to modify this file to match users logic. +#************************************************************** + +#************************************************************** +# Create Clock +#************************************************************** +create_clock -period "10.0 MHz" [get_ports ADC_CLK_10] +create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50] +create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50] + +#************************************************************** +# Create Generated Clock +#************************************************************** +derive_pll_clocks + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** +derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + + + +#************************************************************** +# Set Load +#************************************************************** + + + diff --git a/peripherals/vga/sint/de10_lite_assignment_defaults.qdf b/peripherals/vga/sint/de10_lite_assignment_defaults.qdf new file mode 100644 index 00000000..d40b50e3 --- /dev/null +++ b/peripherals/vga/sint/de10_lite_assignment_defaults.qdf @@ -0,0 +1,807 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# Date created = 08:39:22 July 08, 2019 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. This file was generated +# automatically by the Quartus Prime software and is used +# to preserve global assignments across Quartus Prime versions. +# +# -------------------------------------------------------------------------- # + +set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off +set_global_assignment -name IP_COMPONENT_INTERNAL Off +set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On +set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off +set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off +set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db +set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off +set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off +set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off +set_global_assignment -name HC_OUTPUT_DIR hc_output +set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off +set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off +set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off +set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings" +set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On +set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On +set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off +set_global_assignment -name REVISION_TYPE Base -family "Arria V" +set_global_assignment -name REVISION_TYPE Base -family "Stratix V" +set_global_assignment -name REVISION_TYPE Base -family "Arria V GZ" +set_global_assignment -name REVISION_TYPE Base -family "Cyclone V" +set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle" +set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On +set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On +set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On +set_global_assignment -name DO_COMBINED_ANALYSIS Off +set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off +set_global_assignment -name ENABLE_HPS_INTERNAL_TIMING Off +set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off +set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off +set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On +set_global_assignment -name TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria V" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone 10 LP" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "MAX 10" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Stratix IV" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Cyclone IV E" +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS On -family "Arria 10" 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TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria V GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL Off -family "MAX II" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Arria II GZ" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone IV GX" +set_global_assignment -name TIMING_ANALYZER_DO_CCPP_REMOVAL On -family "Cyclone V" +set_global_assignment -name OPTIMIZATION_MODE Balanced +set_global_assignment -name ALLOW_REGISTER_MERGING On +set_global_assignment -name ALLOW_REGISTER_DUPLICATION On +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Arria V" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON -family "Cyclone 10 LP" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "MAX 10" +set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER OFF -family "Stratix IV" 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Off +set_global_assignment -name ENABLE_IP_DEBUG Off +set_global_assignment -name SAVE_DISK_SPACE On +set_global_assignment -name OCP_HW_EVAL -value OFF +set_global_assignment -name DEVICE_FILTER_PACKAGE Any +set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "" +set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001 +set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993 +set_global_assignment -name FAMILY -value "Cyclone V" +set_global_assignment -name TRUE_WYSIWYG_FLOW Off +set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off +set_global_assignment -name STATE_MACHINE_PROCESSING Auto +set_global_assignment -name SAFE_STATE_MACHINE Off +set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On +set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On +set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off 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SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_PROTECTED_REGISTERS_REPORTED 100 +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000 +set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone 10 LP" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name PRPOF_ID Off +set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off +set_global_assignment -name REPORT_PARAMETER_SETTINGS_PRO On +set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS_PRO On +set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE Off +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name PHYSICAL_SYNTHESIS Off +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image" +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria 10" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Stratix V" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Arria V GZ" +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" -family "Cyclone V" +set_global_assignment -name VID_OPERATION_MODE "PMBus Slave" +set_global_assignment -name USE_CONF_DONE AUTO +set_global_assignment -name USE_PWRMGT_SCL AUTO +set_global_assignment -name USE_PWRMGT_SDA AUTO +set_global_assignment -name USE_PWRMGT_ALERT AUTO +set_global_assignment -name USE_INIT_DONE AUTO +set_global_assignment -name USE_CVP_CONFDONE AUTO +set_global_assignment -name USE_SEU_ERROR AUTO +set_global_assignment -name RESERVE_AVST_CLK_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_VALID_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA15_THROUGH_DATA0_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_AVST_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name ENABLE_UNUSED_RX_CLOCK_WORKAROUND Off +set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL Off +set_global_assignment -name IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS On +set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION On +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN Off +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone 10 LP" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V" +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ" +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION OFF +set_global_assignment -name RESERVE_ROUTING_OUTPUT_FLEXIBILITY Off +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto +set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone 10 LP" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria 10" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX" +set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V" +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto +set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Auto +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone 10 LP" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name RESERVE_PR_PINS Off +set_global_assignment -name CONVERT_PR_WARNINGS_TO_ERRORS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ" +set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V" +set_global_assignment -name RELATIVE_NEUTRON_FLUX 1.0 +set_global_assignment -name SEU_FIT_REPORT Off +set_global_assignment -name HYPER_RETIMER Off -family "Arria 10" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ADD_PIPELINING_MAX "-1" +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_ASYNCH_CLEAR Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_USER_PRESERVE_RESTRICTION Auto +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_DSP_BLOCKS On +set_global_assignment -name HYPER_RETIMER_FAST_FORWARD_RAM_BLOCKS On +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone 10 LP" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE "PV3102 or EM1130" +set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 0000000 +set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 0000000 +set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "Auto discovery" +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_M 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_B 0 +set_global_assignment -name PWRMGT_DIRECT_FORMAT_COEFFICIENT_R 0 +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone 10 LP" +set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX" +set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V" +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off +set_global_assignment -name POR_SCHEME "Instant ON" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP On +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On +set_global_assignment -name POF_VERIFY_PROTECT Off +set_global_assignment -name ENABLE_SPI_MODE_CHECK Off +set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0 +set_global_assignment -name GENERATE_PMSF_FILES On +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off +set_global_assignment -name GENERATE_SVF_FILE Off +set_global_assignment -name GENERATE_ISC_FILE Off +set_global_assignment -name GENERATE_JAM_FILE Off +set_global_assignment -name GENERATE_JBC_FILE Off +set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off +set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off +set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On +set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off +set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state" +set_global_assignment -name HPS_EARLY_IO_RELEASE Off +set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off +set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off +set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5% +set_global_assignment -name POWER_USE_PVA On +set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" +set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On +set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On +set_global_assignment -name RTLV_GROUP_RELATED_NODES On +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off +set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off +set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On +set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On +set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On +set_global_assignment -name EQC_BBOX_MERGE On +set_global_assignment -name EQC_LVDS_MERGE On +set_global_assignment -name EQC_RAM_UNMERGING On +set_global_assignment -name EQC_DFF_SS_EMULATION On +set_global_assignment -name EQC_RAM_REGISTER_UNPACK On +set_global_assignment -name EQC_MAC_REGISTER_UNPACK On +set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On +set_global_assignment -name EQC_STRUCTURE_MATCHING On +set_global_assignment -name EQC_AUTO_BREAK_CONE On +set_global_assignment -name EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_EXTENDED_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p2 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/peripherals/vga/sint/de10_lite_description.txt b/peripherals/vga/sint/de10_lite_description.txt new file mode 100644 index 00000000..e69de29b diff --git a/peripherals/vga/vga_buffer.vhd b/peripherals/vga/vga_buffer.vhd new file mode 100644 index 00000000..d079bf40 --- /dev/null +++ b/peripherals/vga/vga_buffer.vhd @@ -0,0 +1,84 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity vga_buffer is + port( + clk : in std_logic; + rst : in std_logic; + address_vga : in std_logic_vector(31 downto 0); + sdram_data : in std_logic_vector(15 downto 0); + sdram_address : out std_logic_vector(31 downto 0); + sdram_r : out std_logic; + VGA_R : out std_logic_vector(3 downto 0); + VGA_G : out std_logic_vector(3 downto 0); + VGA_B : out std_logic_vector(3 downto 0) + ); +end entity vga_buffer; + +architecture RTL of vga_buffer is + type state_type is (WAIT_READ, WRITING_BANK1, WRITING_BANK2, IDLE); + + signal bank : std_logic; + signal bank_last_value : std_logic; + signal index : natural; + + type mem is array (0 to 15) of std_logic_vector(15 downto 0); + signal memory : mem := (x"0001",x"0001",x"0001",x"0001",x"0001",x"0001",x"0001",x"0001",x"0001",x"0001",x"0001",x"0001",x"0001",x"0001",x"0001",x"0001"); + +begin + + bank <= address_vga(3); + VGA_R <= memory(index)(3 downto 0); + VGA_G <= memory(index)(7 downto 4); + VGA_B <= memory(index)(11 downto 8); + index <= to_integer(unsigned(address_vga(3 downto 0))); + + process(clk, rst) is + variable state : state_type := WAIT_READ; + variable counter : natural := 0; + variable wait_cycles : natural; + begin + if rst = '1' then + state := IDLE; + elsif rising_edge(clk) then + case state is + when IDLE => + if bank /= bank_last_value then + bank_last_value <= bank; + sdram_address <= std_logic_vector(to_unsigned((to_integer(unsigned(address_vga)) + 8), 32)); + sdram_r <= '1'; + wait_cycles := 5; + state := WAIT_READ; + end if; + + when WAIT_READ => + wait_cycles := wait_cycles - 1; + if wait_cycles = 0 then + sdram_r <= '0'; + counter := 0; + if bank = '1' then + state := WRITING_BANK1; + else + state := WRITING_BANK2; + end if; + end if; + + when WRITING_BANK1 => + memory(counter) <= sdram_data; + counter := counter + 1; + if counter = 8 then + state := IDLE; + end if; + + when WRITING_BANK2 => + memory(8 + counter) <= sdram_data; + counter := counter + 1; + if counter = 8 then + state := IDLE; + end if; + end case; + end if; + end process; + +end architecture RTL; diff --git a/peripherals/vga/vga_controller.vhd b/peripherals/vga/vga_controller.vhd new file mode 100644 index 00000000..af9e91be --- /dev/null +++ b/peripherals/vga/vga_controller.vhd @@ -0,0 +1,101 @@ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +ENTITY vga_controller IS + GENERIC( + h_pulse : INTEGER := 128; --horiztonal sync pulse width in pixels + h_bp : INTEGER := 88; --horiztonal back porch width in pixels + h_pixels : INTEGER := 800; --horiztonal display width in pixels + h_fp : INTEGER := 40; --horiztonal front porch width in pixels + h_pol : STD_LOGIC := '1'; --horizontal sync pulse polarity (1 = positive, 0 = negative) + v_pulse : INTEGER := 4; --vertical sync pulse width in rows + v_bp : INTEGER := 23; --vertical back porch width in rows + v_pixels : INTEGER := 600; --vertical display width in rows + v_fp : INTEGER := 1; --vertical front porch width in rows + v_pol : STD_LOGIC := '1'); --vertical sync pulse polarity (1 = positive, 0 = negative) + PORT( + pixel_clk : IN STD_LOGIC; --pixel clock at frequency of VGA mode being used + reset : IN STD_LOGIC; --active low asycnchronous reset + h_sync : OUT STD_LOGIC; --horiztonal sync pulse + v_sync : OUT STD_LOGIC; --vertical sync pulse + disp_ena : OUT STD_LOGIC; --display enable ('1' = display time, '0' = blanking time) + column : OUT INTEGER; --horizontal pixel coordinate + row : OUT INTEGER; --vertical pixel coordinate + addr : OUT std_logic_vector(12 downto 0); --SRAM Addr + n_blank : OUT STD_LOGIC; --direct blacking output to DAC + n_sync : OUT STD_LOGIC); --sync-on-green output to DAC +END vga_controller; + +ARCHITECTURE behavior OF vga_controller IS + CONSTANT h_period : INTEGER := h_pulse + h_bp + h_pixels + h_fp; --total number of pixel clocks in a row + CONSTANT v_period : INTEGER := v_pulse + v_bp + v_pixels + v_fp; --total number of rows in column + +BEGIN + + n_blank <= '1'; --no direct blanking + n_sync <= '0'; --no sync on green + + prc : PROCESS(pixel_clk, reset) + VARIABLE h_count : INTEGER RANGE 0 TO h_period - 1 := 0; --horizontal counter (counts the columns) + VARIABLE v_count : INTEGER RANGE 0 TO v_period - 1 := 0; --vertical counter (counts the rows) + BEGIN + IF (reset = '1') THEN --reset asserted + h_count := 0; --reset horizontal counter + v_count := 0; --reset vertical counter + h_sync <= NOT h_pol; --deassert horizontal sync + v_sync <= NOT v_pol; --deassert vertical sync + disp_ena <= '0'; --disable display + addr <= (others => '0'); + column <= 0; --reset column pixel coordinate + row <= 0; --reset row pixel coordinate + + ELSIF (pixel_clk'EVENT AND pixel_clk = '1') THEN + + --counters + IF (h_count < h_period - 1) THEN --horizontal counter (pixels) + h_count := h_count + 1; + ELSE + h_count := 0; + IF (v_count < v_period - 1) THEN --veritcal counter (rows) + v_count := v_count + 1; + ELSE + v_count := 0; + END IF; + END IF; + + --horizontal sync signal + IF (h_count < h_pixels + h_fp OR h_count >= h_pixels + h_fp + h_pulse) THEN + h_sync <= NOT h_pol; --deassert horiztonal sync pulse + ELSE + h_sync <= h_pol; --assert horiztonal sync pulse + END IF; + + --vertical sync signal + IF (v_count < v_pixels + v_fp OR v_count >= v_pixels + v_fp + v_pulse) THEN + v_sync <= NOT v_pol; --deassert vertical sync pulse + ELSE + v_sync <= v_pol; --assert vertical sync pulse + END IF; + + --set pixel coordinates + IF (h_count < h_pixels) THEN --horiztonal display time + addr <= Std_logic_vector(To_unsigned(h_count + (h_pixels * v_count),addr'length)); + column <= h_count; --set horiztonal pixel coordinate + END IF; + IF (v_count < v_pixels) THEN --vertical display time + row <= v_count; --set vertical pixel coordinate + END IF; + + --set display enable output + IF (h_count < h_pixels AND v_count < v_pixels) THEN --display time + disp_ena <= '1'; --enable display + ELSE --blanking time + disp_ena <= '0'; --disable display + END IF; + + END IF; + END PROCESS; + +END behavior; diff --git a/pll/pll.cmp b/pll/pll.cmp new file mode 100644 index 00000000..5bc5fe1b --- /dev/null +++ b/pll/pll.cmp @@ -0,0 +1,24 @@ +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +component pll + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +end component; diff --git a/pll/pll.ppf b/pll/pll.ppf new file mode 100644 index 00000000..749d70f2 --- /dev/null +++ b/pll/pll.ppf @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/pll/pll.qip b/pll/pll.qip new file mode 100644 index 00000000..3c8baca8 --- /dev/null +++ b/pll/pll.qip @@ -0,0 +1,7 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_inst.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] diff --git a/pll/pll.vhd b/pll/pll.vhd new file mode 100644 index 00000000..11f8f73d --- /dev/null +++ b/pll/pll.vhd @@ -0,0 +1,369 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 18.1.0 Build 625 09/12/2018 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll; + + +ARCHITECTURE SYN OF pll IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + SIGNAL sub_wire5 : STD_LOGIC ; + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + self_reset_on_loss_lock : STRING; + width_clock : NATURAL + ); + PORT ( + areset : IN STD_LOGIC ; + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); + locked : OUT STD_LOGIC + ); + END COMPONENT; + +BEGIN + sub_wire2_bv(0 DOWNTO 0) <= "0"; + sub_wire2 <= To_stdlogicvector(sub_wire2_bv); + sub_wire0 <= inclk0; + sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0; + sub_wire4 <= sub_wire3(0); + c0 <= sub_wire4; + locked <= sub_wire5; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 50, + clk0_duty_cycle => 50, + clk0_multiply_by => 1, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 20000, + intended_device_family => "MAX 10", + lpm_hint => "CBX_MODULE_PREFIX=pll", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + self_reset_on_loss_lock => "OFF", + width_clock => 5 + ) + PORT MAP ( + areset => areset, + inclk => sub_wire1, + clk => sub_wire3, + locked => sub_wire5 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "50" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd TRUE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/pll/pll_inst.vhd b/pll/pll_inst.vhd new file mode 100644 index 00000000..6a70f285 --- /dev/null +++ b/pll/pll_inst.vhd @@ -0,0 +1,6 @@ +pll_inst : pll PORT MAP ( + areset => areset_sig, + inclk0 => inclk0_sig, + c0 => c0_sig, + locked => locked_sig + ); diff --git a/readme_img/compilation_ss.png b/readme_img/compilation_ss.png new file mode 100644 index 00000000..4a96c445 Binary files /dev/null and b/readme_img/compilation_ss.png differ diff --git a/registers/register_file.vhd b/registers/register_file.vhd new file mode 100644 index 00000000..92574067 --- /dev/null +++ b/registers/register_file.vhd @@ -0,0 +1,72 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity register_file is + port( + clk : in std_logic; + -- rst is not used since this register file uses a SRAM instance + rst : in std_logic; + + w_ena : in std_logic; + + w_address : in integer range 0 to 31; + w_data : in std_logic_vector(31 downto 0); + + r1_address : in integer range 0 to 31; + r1_data : out std_logic_vector(31 downto 0); + + r2_address : in integer range 0 to 31; + r2_data : out std_logic_vector(31 downto 0) + ); +end entity register_file; + +architecture RTL of register_file is + -- Build a 2-D array type for the RAM + type RamType is array (0 to 31) of std_logic_vector(31 downto 0); + + -- RAM initialization function + impure function InitRam return RamType is + variable RAM : RamType; + begin + -- Clear all RAM cells + for i in RamType'range loop + RAM(i) := (others => '0'); + end loop; + + return RAM; + end function; + + signal ram: RamType := InitRam; --! RAM Block instance with InitRam initializer + signal w_ena_prot : std_logic; + +begin + -- Writes to register 0 is not allowed + w_ena_prot <= '0' when w_address = 0 else w_ena; + + dual_port_ram: block + begin + portA: process(clk) + begin + if(rising_edge(clk)) then + -- Write port + if(w_ena_prot = '1') then + ram(w_address) <= w_data; + else + -- Read port A + r1_data <= ram(r1_address); + end if; + end if; + end process; + + portB: process(clk) + begin + if(rising_edge(clk)) then + -- Read port B + r2_data <= ram(r2_address); + end if; + end process; + + end block dual_port_ram; + +end architecture RTL; diff --git a/riscv-multicycle.doxyfile b/riscv-multicycle.doxyfile new file mode 100644 index 00000000..974cf1ab --- /dev/null +++ b/riscv-multicycle.doxyfile @@ -0,0 +1,2498 @@ +# Doxyfile 1.8.13 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project. +# +# All text after a double hash (##) is considered a comment and is placed in +# front of the TAG it is preceding. +# +# All text after a single hash (#) is considered a comment and will be ignored. +# The format is: +# TAG = value [value, ...] +# For lists, items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (\" \"). + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. 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By default anonymous namespace +# are hidden. +# The default value is: NO. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all +# undocumented members inside documented classes or files. If set to NO these +# members will be included in the various overviews, but no documentation +# section is generated. This option has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. If set +# to NO, these classes will be included in the various overviews. This option +# has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend +# (class|struct|union) declarations. If set to NO, these declarations will be +# included in the documentation. +# The default value is: NO. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any +# documentation blocks found inside the body of a function. If set to NO, these +# blocks will be appended to the function's detailed documentation block. +# The default value is: NO. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation that is typed after a +# \internal command is included. If the tag is set to NO then the documentation +# will be excluded. Set it to YES to include the internal documentation. +# The default value is: NO. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file +# names in lower-case letters. If set to YES, upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. +# The default value is: system dependent. + +CASE_SENSE_NAMES = YES + +# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with +# their full class and namespace scopes in the documentation. If set to YES, the +# scope will be hidden. +# The default value is: NO. + +HIDE_SCOPE_NAMES = NO + +# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will +# append additional text to a page's title, such as Class Reference. If set to +# YES the compound reference will be hidden. +# The default value is: NO. + +HIDE_COMPOUND_REFERENCE= NO + +# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of +# the files that are included by a file in the documentation of that file. +# The default value is: YES. + +SHOW_INCLUDE_FILES = YES + +# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each +# grouped member an include statement to the documentation, telling the reader +# which file to include in order to use the member. +# The default value is: NO. + +SHOW_GROUPED_MEMB_INC = NO + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include +# files with double quotes in the documentation rather than with sharp brackets. +# The default value is: NO. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the +# documentation for inline members. +# The default value is: YES. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the +# (detailed) documentation of file and class members alphabetically by member +# name. If set to NO, the members will appear in declaration order. +# The default value is: YES. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief +# descriptions of file, namespace and class members alphabetically by member +# name. If set to NO, the members will appear in declaration order. Note that +# this will also influence the order of the classes in the class list. +# The default value is: NO. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the +# (brief and detailed) documentation of class members so that constructors and +# destructors are listed first. If set to NO the constructors will appear in the +# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS. +# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief +# member documentation. +# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting +# detailed member documentation. +# The default value is: NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy +# of group names into alphabetical order. If set to NO the group names will +# appear in their defined order. +# The default value is: NO. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by +# fully-qualified names, including namespaces. If set to NO, the class list will +# be sorted only by class name, not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the alphabetical +# list. +# The default value is: NO. + +SORT_BY_SCOPE_NAME = NO + +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper +# type resolution of all parameters of a function it will reject a match between +# the prototype and the implementation of a member function even if there is +# only one candidate or it is obvious which candidate to choose by doing a +# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still +# accept a match between prototype and implementation in such cases. +# The default value is: NO. + +STRICT_PROTO_MATCHING = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo +# list. This list is created by putting \todo commands in the documentation. +# The default value is: YES. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test +# list. This list is created by putting \test commands in the documentation. +# The default value is: YES. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug +# list. This list is created by putting \bug commands in the documentation. +# The default value is: YES. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO) +# the deprecated list. This list is created by putting \deprecated commands in +# the documentation. +# The default value is: YES. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional documentation +# sections, marked by \if ... \endif and \cond +# ... \endcond blocks. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the +# initial value of a variable or macro / define can have for it to appear in the +# documentation. If the initializer consists of more lines than specified here +# it will be hidden. Use a value of 0 to hide initializers completely. The +# appearance of the value of individual variables and macros / defines can be +# controlled using \showinitializer or \hideinitializer command in the +# documentation regardless of this setting. +# Minimum value: 0, maximum value: 10000, default value: 30. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at +# the bottom of the documentation of classes and structs. If set to YES, the +# list will mention the files that were used to generate the documentation. +# The default value is: YES. + +SHOW_USED_FILES = YES + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This +# will remove the Files entry from the Quick Index and from the Folder Tree View +# (if specified). +# The default value is: YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces +# page. This will remove the Namespaces entry from the Quick Index and from the +# Folder Tree View (if specified). +# The default value is: YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command command input-file, where command is the value of the +# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided +# by doxygen. Whatever the program writes to standard output is used as the file +# version. For an example see the documentation. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. To create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. You can +# optionally specify a file name after the option, if omitted DoxygenLayout.xml +# will be used as the name of the layout file. +# +# Note that if you run doxygen from a directory containing a file called +# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE +# tag is left empty. + +LAYOUT_FILE = + +# The CITE_BIB_FILES tag can be used to specify one or more bib files containing +# the reference definitions. This must be a list of .bib files. The .bib +# extension is automatically appended if omitted. This requires the bibtex tool +# to be installed. See also http://en.wikipedia.org/wiki/BibTeX for more info. +# For LaTeX the style of the bibliography can be controlled using +# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the +# search path. See also \cite for info how to create references. + +CITE_BIB_FILES = + +#--------------------------------------------------------------------------- +# Configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated to +# standard output by doxygen. If QUIET is set to YES this implies that the +# messages are off. +# The default value is: NO. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES +# this implies that the warnings are on. +# +# Tip: Turn warnings on while writing the documentation. +# The default value is: YES. + +WARNINGS = YES + +# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate +# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag +# will automatically be disabled. +# The default value is: YES. + +WARN_IF_UNDOCUMENTED = YES + +# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some parameters +# in a documented function, or documenting parameters that don't exist or using +# markup commands wrongly. +# The default value is: YES. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that +# are documented, but have no documentation for their parameters or return +# value. If set to NO, doxygen will only warn about wrong or incomplete +# parameter documentation, but not about the absence of documentation. +# The default value is: NO. + +WARN_NO_PARAMDOC = NO + +# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when +# a warning is encountered. +# The default value is: NO. + +WARN_AS_ERROR = NO + +# The WARN_FORMAT tag determines the format of the warning messages that doxygen +# can produce. The string should contain the $file, $line, and $text tags, which +# will be replaced by the file and line number from which the warning originated +# and the warning text. Optionally the format may contain $version, which will +# be replaced by the version of the file (if it could be obtained via +# FILE_VERSION_FILTER) +# The default value is: $file:$line: $text. + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning and error +# messages should be written. If left blank the output is written to standard +# error (stderr). + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# Configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag is used to specify the files and/or directories that contain +# documented source files. You may enter file names like myfile.cpp or +# directories like /usr/src/myproject. Separate the files or directories with +# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING +# Note: If this tag is empty the current directory is searched. + +INPUT = alu \ + core \ + decoder \ + memory \ + registers + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses +# libiconv (or the iconv built into libc) for the transcoding. See the libiconv +# documentation (see: http://www.gnu.org/software/libiconv) for the list of +# possible encodings. +# The default value is: UTF-8. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and +# *.h) to filter out the source-files in the directories. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# read by doxygen. +# +# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp, +# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, +# *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, +# *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, +# *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf and *.qsf. + +FILE_PATTERNS = *.c \ + *.cc \ + *.cxx \ + *.cpp \ + *.c++ \ + *.java \ + *.ii \ + *.ixx \ + *.ipp \ + *.i++ \ + *.inl \ + *.idl \ + *.ddl \ + *.odl \ + *.h \ + *.hh \ + *.hxx \ + *.hpp \ + *.h++ \ + *.cs \ + *.d \ + *.php \ + *.php4 \ + *.php5 \ + *.phtml \ + *.inc \ + *.m \ + *.markdown \ + *.md \ + *.mm \ + *.dox \ + *.py \ + *.pyw \ + *.f90 \ + *.f95 \ + *.f03 \ + *.f08 \ + *.f \ + *.for \ + *.tcl \ + *.vhd \ + *.vhdl \ + *.ucf \ + *.qsf + +# The RECURSIVE tag can be used to specify whether or not subdirectories should +# be searched for input files as well. +# The default value is: NO. + +RECURSIVE = NO + +# The EXCLUDE tag can be used to specify files and/or directories that should be +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. +# +# Note that relative paths are relative to the directory from which doxygen is +# run. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded +# from the input. +# The default value is: NO. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories use the pattern */test/* + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or directories +# that contain example code fragments that are included (see the \include +# command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and +# *.h) to filter out the source-files in the directories. If left blank all +# files are included. + +EXAMPLE_PATTERNS = * + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude commands +# irrespective of the value of the RECURSIVE tag. +# The default value is: NO. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or directories +# that contain images that are to be included in the documentation (see the +# \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command: +# +# +# +# where is the value of the INPUT_FILTER tag, and is the +# name of an input file. Doxygen will then use the output that the filter +# program writes to standard output. If FILTER_PATTERNS is specified, this tag +# will be ignored. +# +# Note that the filter must not add or remove lines; it is applied before the +# code is scanned, but not when the output code is generated. If lines are added +# or removed, the anchors will not be placed correctly. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# properly processed by doxygen. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: pattern=filter +# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how +# filters are used. If the FILTER_PATTERNS tag is empty or if none of the +# patterns match the file name, INPUT_FILTER is applied. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# properly processed by doxygen. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will also be used to filter the input files that are used for +# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES). +# The default value is: NO. + +FILTER_SOURCE_FILES = NO + +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and +# it is also possible to disable source filtering for a specific pattern using +# *.ext= (so without naming a filter). +# This tag requires that the tag FILTER_SOURCE_FILES is set to YES. + +FILTER_SOURCE_PATTERNS = + +# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that +# is part of the input, its contents will be placed on the main page +# (index.html). This can be useful if you have a project on for instance GitHub +# and want to reuse the introduction page also for the doxygen output. + +USE_MDFILE_AS_MAINPAGE = + +#--------------------------------------------------------------------------- +# Configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will be +# generated. Documented entities will be cross-referenced with these sources. +# +# Note: To get rid of all source code in the generated output, make sure that +# also VERBATIM_HEADERS is set to NO. +# The default value is: NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body of functions, +# classes and enums directly into the documentation. +# The default value is: NO. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any +# special comment blocks from generated source code fragments. Normal C, C++ and +# Fortran comments will always remain visible. +# The default value is: YES. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES then for each documented +# function all documented functions referencing it will be listed. +# The default value is: NO. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES then for each documented function +# all documented entities called/used by that function will be listed. +# The default value is: NO. + +REFERENCES_RELATION = NO + +# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set +# to YES then the hyperlinks from functions in REFERENCES_RELATION and +# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will +# link to the documentation. +# The default value is: YES. + +REFERENCES_LINK_SOURCE = YES + +# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the +# source code will show a tooltip with additional information such as prototype, +# brief description and links to the definition and documentation. Since this +# will make the HTML file larger and loading of large files a bit slower, you +# can opt to disable this feature. +# The default value is: YES. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +SOURCE_TOOLTIPS = YES + +# If the USE_HTAGS tag is set to YES then the references to source code will +# point to the HTML generated by the htags(1) tool instead of doxygen built-in +# source browser. The htags tool is part of GNU's global source tagging system +# (see http://www.gnu.org/software/global/global.html). You will need version +# 4.8.6 or higher. +# +# To use it do the following: +# - Install the latest version of global +# - Enable SOURCE_BROWSER and USE_HTAGS in the config file +# - Make sure the INPUT points to the root of the source tree +# - Run doxygen as normal +# +# Doxygen will invoke htags (and that will in turn invoke gtags), so these +# tools must be available from the command line (i.e. in the search path). +# +# The result: instead of the source browser generated by doxygen, the links to +# source code will now point to the output of htags. +# The default value is: NO. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a +# verbatim copy of the header file for each class for which an include is +# specified. Set to NO to disable this. +# See also: Section \class. +# The default value is: YES. + +VERBATIM_HEADERS = YES + +# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the +# clang parser (see: http://clang.llvm.org/) for more accurate parsing at the +# cost of reduced performance. This can be particularly helpful with template +# rich C++ code for which doxygen's built-in parser lacks the necessary type +# information. +# Note: The availability of this option depends on whether or not doxygen was +# generated with the -Duse-libclang=ON option for CMake. +# The default value is: NO. + +CLANG_ASSISTED_PARSING = NO + +# If clang assisted parsing is enabled you can provide the compiler with command +# line options that you would normally use when invoking the compiler. Note that +# the include paths will already be set by doxygen for the files and directories +# specified with INPUT and INCLUDE_PATH. +# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES. + +CLANG_OPTIONS = + +#--------------------------------------------------------------------------- +# Configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all +# compounds will be generated. Enable this if the project contains a lot of +# classes, structs, unions or interfaces. +# The default value is: YES. + +ALPHABETICAL_INDEX = YES + +# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in +# which the alphabetical index list will be split. +# Minimum value: 1, maximum value: 20, default value: 5. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all classes will +# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag +# can be used to specify a prefix (or a list of prefixes) that should be ignored +# while generating the index headers. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output +# The default value is: YES. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a +# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of +# it. +# The default directory is: html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each +# generated HTML page (for example: .htm, .php, .asp). +# The default value is: .html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a user-defined HTML header file for +# each generated HTML page. If the tag is left blank doxygen will generate a +# standard header. +# +# To get valid HTML the header file that includes any scripts and style sheets +# that doxygen needs, which is dependent on the configuration options used (e.g. +# the setting GENERATE_TREEVIEW). It is highly recommended to start with a +# default header using +# doxygen -w html new_header.html new_footer.html new_stylesheet.css +# YourConfigFile +# and then modify the file new_header.html. See also section "Doxygen usage" +# for information on how to generate the default header that doxygen normally +# uses. +# Note: The header is subject to change so you typically have to regenerate the +# default header when upgrading to a newer version of doxygen. For a description +# of the possible markers and block names see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each +# generated HTML page. If the tag is left blank doxygen will generate a standard +# footer. See HTML_HEADER for more information on how to generate a default +# footer and what special commands can be used inside the footer. See also +# section "Doxygen usage" for information on how to generate the default footer +# that doxygen normally uses. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style +# sheet that is used by each HTML page. It can be used to fine-tune the look of +# the HTML output. If left blank doxygen will generate a default style sheet. +# See also section "Doxygen usage" for information on how to generate the style +# sheet that doxygen normally uses. +# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as +# it is more robust and this tag (HTML_STYLESHEET) will in the future become +# obsolete. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_STYLESHEET = + +# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined +# cascading style sheets that are included after the standard style sheets +# created by doxygen. Using this option one can overrule certain style aspects. +# This is preferred over using HTML_STYLESHEET since it does not replace the +# standard style sheet and is therefore more robust against future updates. +# Doxygen will copy the style sheet files to the output directory. +# Note: The order of the extra style sheet files is of importance (e.g. the last +# style sheet in the list overrules the setting of the previous ones in the +# list). For an example see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that the +# files will be copied as-is; there are no commands or markers available. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen +# will adjust the colors in the style sheet and background images according to +# this color. Hue is specified as an angle on a colorwheel, see +# http://en.wikipedia.org/wiki/Hue for more information. For instance the value +# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300 +# purple, and 360 is red again. +# Minimum value: 0, maximum value: 359, default value: 220. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors +# in the HTML output. For a value of 0 the output will use grayscales only. A +# value of 255 will produce the most vivid colors. +# Minimum value: 0, maximum value: 255, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the +# luminance component of the colors in the HTML output. Values below 100 +# gradually make the output lighter, whereas values above 100 make the output +# darker. The value divided by 100 is the actual gamma applied, so 80 represents +# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not +# change the gamma. +# Minimum value: 40, maximum value: 240, default value: 80. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting this +# to YES can help to show when doxygen was last run and thus if the +# documentation is up to date. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_TIMESTAMP = NO + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_DYNAMIC_SECTIONS = NO + +# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries +# shown in the various tree structured indices initially; the user can expand +# and collapse entries dynamically later on. Doxygen will expand the tree to +# such a level that at most the specified number of entries are visible (unless +# a fully collapsed tree already exceeds this amount). So setting the number of +# entries 1 will produce a full collapsed tree by default. 0 is a special value +# representing an infinite number of entries and will result in a full expanded +# tree by default. +# Minimum value: 0, maximum value: 9999, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_INDEX_NUM_ENTRIES = 100 + +# If the GENERATE_DOCSET tag is set to YES, additional index files will be +# generated that can be used as input for Apple's Xcode 3 integrated development +# environment (see: http://developer.apple.com/tools/xcode/), introduced with +# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a +# Makefile in the HTML output directory. Running make will produce the docset in +# that directory and running make install will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at +# startup. See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_DOCSET = NO + +# This tag determines the name of the docset feed. A documentation feed provides +# an umbrella under which multiple documentation sets from a single provider +# (such as a company or product suite) can be grouped. +# The default value is: Doxygen generated docs. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# This tag specifies a string that should uniquely identify the documentation +# set bundle. This should be a reverse domain-name style string, e.g. +# com.mycompany.MyDocSet. Doxygen will append .docset to the name. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify +# the documentation publisher. This should be a reverse domain-name style +# string, e.g. com.mycompany.MyDocSet.documentation. +# The default value is: org.doxygen.Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher. +# The default value is: Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three +# additional HTML index files: index.hhp, index.hhc, and index.hhk. The +# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop +# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on +# Windows. +# +# The HTML Help Workshop contains a compiler that can convert all HTML output +# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML +# files are now used as the Windows 98 help format, and will replace the old +# Windows help format (.hlp) on all Windows platforms in the future. Compressed +# HTML files also contain an index, a table of contents, and you can search for +# words in the documentation. The HTML workshop also contains a viewer for +# compressed HTML files. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_HTMLHELP = NO + +# The CHM_FILE tag can be used to specify the file name of the resulting .chm +# file. You can add a path in front of the file if the result should not be +# written to the html output directory. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_FILE = + +# The HHC_LOCATION tag can be used to specify the location (absolute path +# including file name) of the HTML help compiler (hhc.exe). If non-empty, +# doxygen will try to run the HTML help compiler on the generated index.hhp. +# The file has to be specified with full path. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +HHC_LOCATION = + +# The GENERATE_CHI flag controls if a separate .chi index file is generated +# (YES) or that it should be included in the master .chm file (NO). +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +GENERATE_CHI = NO + +# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc) +# and project file content. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_INDEX_ENCODING = + +# The BINARY_TOC flag controls whether a binary table of contents is generated +# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it +# enables the Previous and Next buttons. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members to +# the table of contents of the HTML help documentation and to the tree view. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that +# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help +# (.qch) of the generated HTML documentation. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify +# the file name of the resulting .qch file. The path specified is relative to +# the HTML output folder. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help +# Project output. For more information please see Qt Help Project / Namespace +# (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#namespace). +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt +# Help Project output. For more information please see Qt Help Project / Virtual +# Folders (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#virtual- +# folders). +# The default value is: doc. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_VIRTUAL_FOLDER = doc + +# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom +# filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://qt-project.org/doc/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's filter section matches. Qt Help Project / Filter Attributes (see: +# http://qt-project.org/doc/qt-4.8/qthelpproject.html#filter-attributes). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_SECT_FILTER_ATTRS = + +# The QHG_LOCATION tag can be used to specify the location of Qt's +# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the +# generated .qhp file. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be +# generated, together with the HTML files, they form an Eclipse help plugin. To +# install this plugin and make it available under the help contents menu in +# Eclipse, the contents of the directory containing the HTML and XML files needs +# to be copied into the plugins directory of eclipse. The name of the directory +# within the plugins directory should be the same as the ECLIPSE_DOC_ID value. +# After copying Eclipse needs to be restarted before the help appears. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the Eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have this +# name. Each documentation set should have its own identifier. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# If you want full control over the layout of the generated HTML pages it might +# be necessary to disable the index and replace it with your own. The +# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top +# of each HTML page. A value of NO enables the index and the value YES disables +# it. Since the tabs in the index contain the same information as the navigation +# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +DISABLE_INDEX = NO + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. If the tag +# value is set to YES, a side panel will be generated containing a tree-like +# index structure (just like the one that is generated for HTML Help). For this +# to work a browser that supports JavaScript, DHTML, CSS and frames is required +# (i.e. any modern browser). Windows users are probably better off using the +# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can +# further fine-tune the look of the index. As an example, the default style +# sheet generated by doxygen has an example that shows how to put an image at +# the root of the tree instead of the PROJECT_NAME. Since the tree basically has +# the same information as the tab index, you could consider setting +# DISABLE_INDEX to YES when enabling this option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_TREEVIEW = NO + +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that +# doxygen will group on one line in the generated HTML documentation. +# +# Note that a value of 0 will completely suppress the enum values from appearing +# in the overview section. +# Minimum value: 0, maximum value: 20, default value: 4. +# This tag requires that the tag GENERATE_HTML is set to YES. + +ENUM_VALUES_PER_LINE = 4 + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used +# to set the initial width (in pixels) of the frame in which the tree is shown. +# Minimum value: 0, maximum value: 1500, default value: 250. +# This tag requires that the tag GENERATE_HTML is set to YES. + +TREEVIEW_WIDTH = 250 + +# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to +# external symbols imported via tag files in a separate window. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of LaTeX formulas included as images in +# the HTML documentation. When you change the font size after a successful +# doxygen run you need to manually remove any form_*.png images from the HTML +# output directory to force them to be regenerated. +# Minimum value: 8, maximum value: 50, default value: 10. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are not +# supported properly for IE 6.0, but are supported on all modern browsers. +# +# Note that when changing this option you need to delete any form_*.png files in +# the HTML output directory before the changes have effect. +# The default value is: YES. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see +# http://www.mathjax.org) which uses client side Javascript for the rendering +# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX +# installed or if you want to formulas look prettier in the HTML output. When +# enabled you may also need to install MathJax separately and configure the path +# to it using the MATHJAX_RELPATH option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +USE_MATHJAX = NO + +# When MathJax is enabled you can set the default output format to be used for +# the MathJax output. See the MathJax site (see: +# http://docs.mathjax.org/en/latest/output.html) for more details. +# Possible values are: HTML-CSS (which is slower, but has the best +# compatibility), NativeMML (i.e. MathML) and SVG. +# The default value is: HTML-CSS. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_FORMAT = HTML-CSS + +# When MathJax is enabled you need to specify the location relative to the HTML +# output directory using the MATHJAX_RELPATH option. The destination directory +# should contain the MathJax.js script. For instance, if the mathjax directory +# is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax +# Content Delivery Network so you can quickly see the result without installing +# MathJax. However, it is strongly recommended to install a local copy of +# MathJax from http://www.mathjax.org before deployment. +# The default value is: http://cdn.mathjax.org/mathjax/latest. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest + +# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax +# extension names that should be enabled during MathJax rendering. For example +# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_EXTENSIONS = + +# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces +# of code that will be used on startup of the MathJax code. See the MathJax site +# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an +# example see the documentation. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_CODEFILE = + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box for +# the HTML output. The underlying search engine uses javascript and DHTML and +# should work on any modern browser. Note that when using HTML help +# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) +# there is already a search function so this one should typically be disabled. +# For large projects the javascript based search engine can be slow, then +# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to +# search using the keyboard; to jump to the search box use + S +# (what the is depends on the OS and browser, but it is typically +# , /