diff --git a/peripherals/simple_serial_transmitter/README.md b/peripherals/simple_serial_transmitter/README.md
new file mode 100644
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--- /dev/null
+++ b/peripherals/simple_serial_transmitter/README.md
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+# Simple Serial Transmitter
+
+Esse módulo implementa um transmissor serial que converte dados de 8 bits em formato paralelo para um formato serial para transmissão por um único pino de saída. O código inclui uma máquina de estados que controla o processo de transmissão, incluindo a adição de um bit de start, mantendo a saída em nível lógico alto quando inativa.
+
+## Funcionamento
+A transmissão inicia com um bit de start em nível baixo, seguido pelo envio serial do endereço (8 bits), seguido pelos dados (8 bits). Após a transmissão, a linha de saída (sdata) retorna para nível lógico alto até a próxima transmissão.
+
+O Simple Serial Transmitter pode ser testado utilizando o modelSim, onde a simulação foi projetada para que seja possível ver o nível lógico da saída, o estado atual da máquina de estados e os bits que estão sendo enviados.
+
+A funcionalidade do circuito pode ser validada em hardware, utilizando um osciloscópio para monitorar a saída serial (sdata).
+
+### Diagrama de blocos do Simple Serial Transmitter
+
+
+
+
+### Arquivos
+
+Os códigos utilizados para esse projeto podem ser encontrados nas pastas:
+
+* [Script em C](../../software/simple_serial_transmitter)
+* [Script em vhd](../simple_serial_transmitter)
+
+## Máquina de estados
+
+Uma máquina de estados foi usada para gerenciar as diferentes fases da transmissão, incluindo o envio do bit de start, o endereço e os dados.
+A máquina de estados com 4 estados pode ser vista no arquivo .vhd do Simple Serial Transmitter, assim como nos diagramas de blocos a seguir, gerados pelo software Sigasi e Quartus respectivamente.
+
+
+
+
+
+
+
+
+## Resultados esperados para simulação e medições no osciloscópio
+
+O transmissor deve gerar uma sequência de bits como ilustrado abaixo:
+```
+[Start Bit (0)] [addr (8 bits)] [data (8 bits)]
+```
+* Start Bit: Um único bit em nível lógico baixo 0 sinalizando o início da transmissão.
+
+* addr: 8 bits do endereço.
+
+* data: 8 bits do dado a ser transmitido.
+
+Enquanto não tiver transmissão, o nível lógico na saída será 1, até o proxímo start bit ser enviado.
+
+### Simulação utilizando ModelSim
+
+
+
+
+
+Nessa imagem podemos examinar todos os estados da máquina de estados, e ver o processo de envio serial dos bits e o comportamento da saída sdata. Lembrando que a saída sdata é a informação utilizada para medição com o uso do osciloscópio.
+
+### Testando em bancada
+Após compilar o arquivo ```.c``` do simple serial transmitter, o arquivo ```.hex``` criado é então importado para a memória da placa e de acordo com a síntese do codígo, na saída ```ARDUINO_IO(0)``` é possível ver a saída ```stdata```, como pode ser visto nas imagens a seguir.
+
+
+
+
+
+
+
+
+
+
+
+Analisando as imagens anteriores, podemos ver o start bit mudando o nível lógico da saída para 0, e após isso é feito a transmissão do sinal ```addr``` que no momento de execução estava definido como ```0xff```, após a transferência do sinal addr, começa a ser transmitido o sinal ```data``` que no momento de execução estava definido como ```data```, que é um valor int que é incrementado a cada loop.
+
+## Notas finais
+
+Os arquivos utilizados para esse projeto possuem o nome ```simple_serial_transmitter```, com exceção aos arquivos de ```testbench```, ```tb.do``` e o arquivo de síntese do software Quartus.
+
+Os arquivos ```.c``` e ```.h``` são utilizados para a geração e definição dos bits de endereço (addr), dados (data) e start_bit (start).
+
+Também é possível visualizar a informação do ```data``` através dos blinks dos LEDs.
+
+Os arquivos ```testbench``` e ```tb.do``` foram criados para os testes e simulações no software ModelSim.
+
+E por fim os arquivos ```.vhd``` são os arquivos de definição do script do projeto assim como síntese para utilizar no hardware.
+
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diff --git a/peripherals/simple_serial_transmitter/simple_serial_transmitter.vhd b/peripherals/simple_serial_transmitter/simple_serial_transmitter.vhd
new file mode 100644
index 00000000..a92011a1
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+-------------------------------------------------------------------
+-- Name : simple_serial_transmitter.vhd --
+-- Author : Gabriel Romero e Yuri Marques --
+-- Description : Simple Serial Transmitter --
+-------------------------------------------------------------------
+
+--! Use standard library
+library ieee;
+--! Use standard logic elements
+use ieee.std_logic_1164.all;
+--! Use conversion functions
+use ieee.numeric_std.all;
+
+entity simple_serial_transmitter is
+ generic (
+ --! Chip selec
+ MY_CHIPSELECT : std_logic_vector(1 downto 0) := "10"; --! Chip select of this device
+ MY_WORD_ADDRESS : unsigned(15 downto 0) := x"0130"; --! Address of this device
+ DADDRESS_BUS_SIZE : integer := 32 --! Data bus size
+ );
+ port
+(
+ clk : in std_logic;
+ rst : in std_logic;
+
+ -- Core data bus signals
+ -- ToDo: daddress shoud be unsgined
+ daddress : in unsigned(DADDRESS_BUS_SIZE-1 downto 0);
+ ddata_w : in std_logic_vector(31 downto 0);
+ ddata_r : out std_logic_vector(31 downto 0);
+ d_we : in std_logic;
+ d_rd : in std_logic;
+ dcsel : in std_logic_vector(1 downto 0); --! Chip select
+ -- ToDo: Module should mask bytes (Word, half word and byte access)
+ dmask : in std_logic_vector(3 downto 0); --! Byte enable mask
+
+ -- hardware input/output signals
+ sdata : out std_logic
+ );
+end entity simple_serial_transmitter;
+
+architecture rtl of Simple_Serial_Transmitter is
+
+ type state_type is (IDLE, ADDR_TR, DATA_TR, DONE);
+ signal state : state_type := IDLE;
+ signal start_w : std_logic;
+ signal addr_w : std_logic_vector(7 downto 0);
+ signal data_w : std_logic_vector(7 downto 0);
+ signal databit_transmission : unsigned(0 to 7);
+ signal sregister : std_logic_vector(15 downto 0) := (others => '0');
+
+begin
+
+ process(clk, rst)
+ begin
+ if rst = '1' then
+ start_w <= '0';
+ addr_w <= (others => '0');
+ data_w <= (others => '0');
+ elsif rising_edge(clk) then
+ if (d_we = '1') and (dcsel = MY_CHIPSELECT) then
+ if daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0000") then -- addr
+ addr_w <= ddata_w(7 downto 0);
+ elsif daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0001") then -- data
+ data_w <= ddata_w(7 downto 0);
+ elsif daddress(15 downto 0) = (MY_WORD_ADDRESS + x"0002") then -- start
+ start_w <= ddata_w(0);
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+ process(clk, rst)
+ begin
+ if rst = '1' then
+ databit_transmission <= (others => '0');
+ state <= IDLE;
+ else
+ if rising_edge(clk) then
+ case state is
+ when IDLE =>
+ databit_transmission <= (others => '0');
+ if start_w = '1' then
+ state <= ADDR_TR;
+ end if;
+ when ADDR_TR =>
+ if databit_transmission = 7 then
+ databit_transmission <= (others => '0');
+ state <= DATA_TR;
+ else
+ databit_transmission <= databit_transmission + 1;
+ end if;
+ when DATA_TR =>
+ if databit_transmission = 7 then
+ state <= DONE;
+ else
+ databit_transmission <= databit_transmission + 1;
+ end if;
+ when DONE =>
+ if start_w = '0' then
+ state <= IDLE;
+ end if;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ process(state, start_w, databit_transmission)
+ constant NO_TRANSMISSION : std_logic := '1';
+ begin
+
+ sdata <= NO_TRANSMISSION; -- no transmission: sdata = 1;
+
+ case state is
+ when IDLE =>
+ if start_w = '1' then
+ sregister <= addr_w & data_w;
+ sdata <= '0'; -- send start bit = 0;
+ end if;
+ when ADDR_TR =>
+ sdata <= sregister(15 - To_integer(databit_transmission));
+ when DATA_TR =>
+ sdata <= sregister(7 - To_integer(databit_transmission));
+ when DONE =>
+ end case;
+ end process;
+
+end architecture rtl;
diff --git a/peripherals/simple_serial_transmitter/sint/de0_lite.vhd b/peripherals/simple_serial_transmitter/sint/de0_lite.vhd
new file mode 100644
index 00000000..96795dc6
--- /dev/null
+++ b/peripherals/simple_serial_transmitter/sint/de0_lite.vhd
@@ -0,0 +1,347 @@
+-------------------------------------------------------------------
+-- Name : de0_lite.vhd
+-- Author : Gabriel Romero e Yuri Marques
+-- Version : 0.1
+-- Copyright : Departamento de Eletrônica, Florianópolis, IFSC
+-- Description : Projeto base DE10-Lite
+-------------------------------------------------------------------
+LIBRARY ieee;
+USE IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
+
+use work.decoder_types.all;
+
+entity de0_lite_simple_serial_transmitter is
+ generic (
+ --! Num of 32-bits memory words
+ IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes
+ DMEMORY_WORDS : integer := 1024 --!= 2k (512 * 2) bytes
+ );
+ port (
+ ---------- CLOCK ----------
+ ADC_CLK_10: in std_logic;
+ MAX10_CLK1_50: in std_logic;
+ MAX10_CLK2_50: in std_logic;
+
+ ----------- SDRAM ------------
+ DRAM_ADDR: out std_logic_vector (12 downto 0);
+ DRAM_BA: out std_logic_vector (1 downto 0);
+ DRAM_CAS_N: out std_logic;
+ DRAM_CKE: out std_logic;
+ DRAM_CLK: out std_logic;
+ DRAM_CS_N: out std_logic;
+ DRAM_DQ: inout std_logic_vector(15 downto 0);
+ DRAM_LDQM: out std_logic;
+ DRAM_RAS_N: out std_logic;
+ DRAM_UDQM: out std_logic;
+ DRAM_WE_N: out std_logic;
+
+ ----------- SEG7 ------------
+ HEX0: out std_logic_vector(7 downto 0);
+ HEX1: out std_logic_vector(7 downto 0);
+ HEX2: out std_logic_vector(7 downto 0);
+ HEX3: out std_logic_vector(7 downto 0);
+ HEX4: out std_logic_vector(7 downto 0);
+ HEX5: out std_logic_vector(7 downto 0);
+
+ ----------- KEY ------------
+ KEY: in std_logic_vector(1 downto 0);
+
+ ----------- LED ------------
+ LEDR: out std_logic_vector(9 downto 0);
+
+ ----------- SW ------------
+ SW: in std_logic_vector(9 downto 0);
+
+ ----------- VGA ------------
+ VGA_B: out std_logic_vector(3 downto 0);
+ VGA_G: out std_logic_vector(3 downto 0);
+ VGA_HS: out std_logic;
+ VGA_R: out std_logic_vector(3 downto 0);
+ VGA_VS: out std_logic;
+
+ ----------- Accelerometer ------------
+ GSENSOR_CS_N: out std_logic;
+ GSENSOR_INT: in std_logic_vector(2 downto 1);
+ GSENSOR_SCLK: out std_logic;
+ GSENSOR_SDI: inout std_logic;
+ GSENSOR_SDO: inout std_logic;
+
+ ----------- Arduino ------------
+ ARDUINO_IO: inout std_logic_vector(15 downto 0);
+ ARDUINO_RESET_N: inout std_logic
+ );
+end entity;
+
+
+
+architecture rtl of de0_lite_simple_serial_transmitter is
+ -- chip select
+ constant MY_CHIPSELECT : std_logic_vector(1 downto 0) := "10";
+ constant MY_SERIAL_TRANSMITTER_ADDRESS: unsigned(15 downto 0) := x"0130";
+ constant DADDRESS_BUS_SIZE : integer := 32;
+
+ -- Clocks and reset
+ signal clk : std_logic;
+ signal rst : std_logic;
+ signal clk_50MHz : std_logic;
+ -- PLL signals
+ signal locked_sig : std_logic;
+
+ -- Instruction bus signals
+ signal idata : std_logic_vector(31 downto 0);
+ signal iaddress : unsigned(15 downto 0);
+ signal address : std_logic_vector (9 downto 0);
+
+ -- Data bus signals
+ signal daddress : unsigned(31 downto 0);
+ signal ddata_r : std_logic_vector(31 downto 0);
+ signal ddata_w : std_logic_vector(31 downto 0);
+ signal ddata_r_mem : std_logic_vector(31 downto 0);
+ signal dmask : std_logic_vector(3 downto 0);
+ signal dcsel : std_logic_vector(1 downto 0);
+ signal d_we : std_logic;
+ signal d_rd : std_logic;
+ signal d_sig : std_logic;
+
+ -- SDRAM signals
+ signal ddata_r_sdram : std_logic_vector(31 downto 0);
+
+ -- CPU state signals
+ signal state : cpu_state_t;
+ signal div_result : std_logic_vector(31 downto 0);
+
+ -- I/O signals
+ signal gpio_input : std_logic_vector(31 downto 0);
+ signal gpio_output : std_logic_vector(31 downto 0);
+
+ -- Peripheral data signals
+ signal ddata_r_gpio : std_logic_vector(31 downto 0);
+ signal ddata_r_timer : std_logic_vector(31 downto 0);
+ signal ddata_r_periph : std_logic_vector(31 downto 0);
+ signal ddata_r_segments : std_logic_vector(31 downto 0);
+ signal ddata_r_uart : std_logic_vector(31 downto 0);
+ signal ddata_r_adc : std_logic_vector(31 downto 0);
+ signal ddata_r_i2c : std_logic_vector(31 downto 0);
+ signal ddata_r_dig_fil : std_logic_vector(31 downto 0);
+ signal ddata_r_stepmot : std_logic_vector(31 downto 0);
+ signal ddata_r_lcd : std_logic_vector(31 downto 0);
+ signal ddata_r_nn_accelerator : std_logic_vector(31 downto 0);
+ signal ddata_r_fir_fil : std_logic_vector(31 downto 0);
+ signal ddata_r_spwm : std_logic_vector(31 downto 0);
+ signal ddata_r_crc : std_logic_vector(31 downto 0);
+ signal ddata_r_key : std_logic_vector(31 downto 0);
+ signal ddata_r_accelerometer : std_logic_vector(31 downto 0);
+
+ -- Interrupt Signals
+ signal interrupts : std_logic_vector(31 downto 0);
+ signal gpio_interrupts : std_logic_vector(6 downto 0);
+ signal timer_interrupt : std_logic_vector(5 downto 0);
+
+ -- I/O signals
+ signal input_in : std_logic_vector(31 downto 0);
+
+ signal ifcap : std_logic; -- capture flag
+
+begin
+
+ -- Reset
+ rst <= SW(9);
+ LEDR(9) <= SW(9);
+
+ -- Clocks
+ pll_inst : entity work.pll
+ port map(
+ areset => '0',
+ inclk0 => MAX10_CLK1_50,
+ c0 => clk,
+ c1 => clk_50MHz,
+ locked => locked_sig
+ );
+
+ -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor
+ iram_quartus_inst: entity work.iram_quartus
+ port map(
+ address => address,
+ byteena => "1111",
+ clock => clk,
+ data => (others => '0'),
+ wren => '0',
+ q => idata
+ );
+
+ -- IMem shoud be read from instruction and data buses
+ -- Not enough RAM ports for instruction bus, data bus and in-circuit programming
+ instr_mux: entity work.instructionbusmux
+ port map(
+ d_rd => d_rd,
+ dcsel => dcsel,
+ daddress => daddress,
+ iaddress => iaddress,
+ address => address
+ );
+
+ -- Data Memory RAM
+ dmem: entity work.dmemory
+ generic map(
+ MEMORY_WORDS => DMEMORY_WORDS
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ data => ddata_w,
+ address => daddress,
+ we => d_we,
+ csel => dcsel(0),
+ dmask => dmask,
+ signal_ext => d_sig,
+ q => ddata_r_mem
+ );
+
+ -- Adress space mux ((check sections.ld) -> Data chip select:
+ -- 0x00000 -> Instruction memory
+ -- 0x20000 -> Data memory
+ -- 0x40000 -> Input/Output generic address space
+ -- ( ... ) -> ( ... )
+ datamux: entity work.databusmux
+ port map(
+ dcsel => dcsel,
+ idata => idata,
+ ddata_r_mem => ddata_r_mem,
+ ddata_r_periph => ddata_r_periph,
+ ddata_r_sdram =>ddata_r_sdram,
+ ddata_r => ddata_r
+
+ );
+
+ -- Softcore instatiation
+ myRiscv : entity work.core
+ port map(
+ clk => clk,
+ rst => rst,
+ clk_32x => clk_50MHz,
+ iaddress => iaddress,
+ idata => idata,
+ daddress => daddress,
+ ddata_r => ddata_r,
+ ddata_w => ddata_w,
+ d_we => d_we,
+ d_rd => d_rd,
+ d_sig => d_sig,
+ dcsel => dcsel,
+ dmask => dmask,
+ interrupts=>interrupts,
+ state => state
+ );
+
+ -- IRQ lines
+ interrupts(24 downto 18) <= gpio_interrupts(6 downto 0);
+ interrupts(30 downto 25) <= timer_interrupt;
+
+ io_data_bus_mux: entity work.iodatabusmux
+ port map(
+ daddress => daddress,
+ ddata_r_gpio => ddata_r_gpio,
+ ddata_r_segments => ddata_r_segments,
+ ddata_r_uart => ddata_r_uart,
+ ddata_r_adc => ddata_r_adc,
+ ddata_r_i2c => ddata_r_i2c,
+ ddata_r_timer => ddata_r_timer,
+ ddata_r_periph => ddata_r_periph,
+ ddata_r_dif_fil => ddata_r_dig_fil,
+ ddata_r_stepmot => ddata_r_stepmot,
+ ddata_r_lcd => ddata_r_lcd,
+ ddata_r_fir_fil => ddata_r_fir_fil,
+ ddata_r_nn_accelerator => ddata_r_nn_accelerator,
+ ddata_r_spwm => ddata_r_spwm,
+ ddata_r_crc => ddata_r_crc,
+ ddata_r_key => ddata_r_key,
+ ddata_r_accelerometer => ddata_r_accelerometer
+ );
+
+ generic_gpio: entity work.gpio
+ port map(
+ clk => clk,
+ rst => rst,
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => ddata_r_gpio,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+ input => gpio_input,
+ output => gpio_output,
+ gpio_interrupts => gpio_interrupts
+ );
+
+ -- Timer instantiation
+ timer : entity work.Timer
+ generic map(
+ PRESCALER_SIZE => 16,
+ COMPARE_SIZE => 32
+ )
+ port map(
+ clock => clk,
+ reset => rst,
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => ddata_r_timer,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+ timer_interrupt => timer_interrupt,
+ ifcap => ifcap
+ );
+
+ generic_displays : entity work.led_displays
+ port map(
+ clk => clk,
+ rst => rst,
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => ddata_r_segments,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+ hex0 => HEX0,
+ hex1 => HEX1,
+ hex2 => HEX2,
+ hex3 => HEX3,
+ hex4 => HEX4,
+ hex5 => HEX5,
+ hex6 => open,
+ hex7 => open
+ );
+
+ simple_serial_transmitter_inst : entity work.simple_serial_transmitter
+ generic map(
+ MY_CHIPSELECT => MY_CHIPSELECT,
+ MY_WORD_ADDRESS => MY_SERIAL_TRANSMITTER_ADDRESS,
+ DADDRESS_BUS_SIZE => DADDRESS_BUS_SIZE
+ )
+ port map(
+ clk => clk,
+ rst => rst,
+
+ -- core data bus
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => open,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+
+ -- serial transmitter
+ sdata => ARDUINO_IO(0)
+ );
+
+ -- Connect input hardware to gpio data
+ gpio_input(3 downto 0) <= SW(3 downto 0);
+ LEDR(7 downto 0) <= gpio_output(7 downto 0);
+
+end;
+
diff --git a/peripherals/simple_serial_transmitter/sint/de10_lite.qpf b/peripherals/simple_serial_transmitter/sint/de10_lite.qpf
new file mode 100644
index 00000000..2e37e9d1
--- /dev/null
+++ b/peripherals/simple_serial_transmitter/sint/de10_lite.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
+# Date created = 18:49:34 June 20, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "15.0"
+DATE = "18:49:34 June 20, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "de10_lite"
diff --git a/peripherals/simple_serial_transmitter/sint/de10_lite.qsf b/peripherals/simple_serial_transmitter/sint/de10_lite.qsf
new file mode 100644
index 00000000..295461a1
--- /dev/null
+++ b/peripherals/simple_serial_transmitter/sint/de10_lite.qsf
@@ -0,0 +1,244 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors. Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 15.0.0 Build 145 04/22/2015 SJ Web Edition
+# Date created = 18:49:34 June 20, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# de10_lite_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "MAX 10"
+set_global_assignment -name DEVICE 10M50DAF484C7G
+set_global_assignment -name TOP_LEVEL_ENTITY de0_lite_simple_serial_transmitter
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.0.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:49:34 JUNE 20, 2019"
+set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.0 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL ""
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name ENABLE_OCT_DONE ON
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE IMAGE WITH ERAM"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_location_assignment PIN_N5 -to ADC_CLK_10
+set_location_assignment PIN_P11 -to MAX10_CLK1_50
+set_location_assignment PIN_N14 -to MAX10_CLK2_50
+set_location_assignment PIN_U17 -to DRAM_ADDR[0]
+set_location_assignment PIN_W19 -to DRAM_ADDR[1]
+set_location_assignment PIN_V18 -to DRAM_ADDR[2]
+set_location_assignment PIN_U18 -to DRAM_ADDR[3]
+set_location_assignment PIN_U19 -to DRAM_ADDR[4]
+set_location_assignment PIN_T18 -to DRAM_ADDR[5]
+set_location_assignment PIN_T19 -to DRAM_ADDR[6]
+set_location_assignment PIN_R18 -to DRAM_ADDR[7]
+set_location_assignment PIN_P18 -to DRAM_ADDR[8]
+set_location_assignment PIN_P19 -to DRAM_ADDR[9]
+set_location_assignment PIN_T20 -to DRAM_ADDR[10]
+set_location_assignment PIN_P20 -to DRAM_ADDR[11]
+set_location_assignment PIN_R20 -to DRAM_ADDR[12]
+set_location_assignment PIN_T21 -to DRAM_BA[0]
+set_location_assignment PIN_T22 -to DRAM_BA[1]
+set_location_assignment PIN_U21 -to DRAM_CAS_N
+set_location_assignment PIN_N22 -to DRAM_CKE
+set_location_assignment PIN_L14 -to DRAM_CLK
+set_location_assignment PIN_U20 -to DRAM_CS_N
+set_location_assignment PIN_Y21 -to DRAM_DQ[0]
+set_location_assignment PIN_Y20 -to DRAM_DQ[1]
+set_location_assignment PIN_AA22 -to DRAM_DQ[2]
+set_location_assignment PIN_AA21 -to DRAM_DQ[3]
+set_location_assignment PIN_Y22 -to DRAM_DQ[4]
+set_location_assignment PIN_W22 -to DRAM_DQ[5]
+set_location_assignment PIN_W20 -to DRAM_DQ[6]
+set_location_assignment PIN_V21 -to DRAM_DQ[7]
+set_location_assignment PIN_P21 -to DRAM_DQ[8]
+set_location_assignment PIN_J22 -to DRAM_DQ[9]
+set_location_assignment PIN_H21 -to DRAM_DQ[10]
+set_location_assignment PIN_H22 -to DRAM_DQ[11]
+set_location_assignment PIN_G22 -to DRAM_DQ[12]
+set_location_assignment PIN_G20 -to DRAM_DQ[13]
+set_location_assignment PIN_G19 -to DRAM_DQ[14]
+set_location_assignment PIN_F22 -to DRAM_DQ[15]
+set_location_assignment PIN_V22 -to DRAM_LDQM
+set_location_assignment PIN_U22 -to DRAM_RAS_N
+set_location_assignment PIN_J21 -to DRAM_UDQM
+set_location_assignment PIN_V20 -to DRAM_WE_N
+set_location_assignment PIN_C14 -to HEX0[0]
+set_location_assignment PIN_E15 -to HEX0[1]
+set_location_assignment PIN_C15 -to HEX0[2]
+set_location_assignment PIN_C16 -to HEX0[3]
+set_location_assignment PIN_E16 -to HEX0[4]
+set_location_assignment PIN_D17 -to HEX0[5]
+set_location_assignment PIN_C17 -to HEX0[6]
+set_location_assignment PIN_D15 -to HEX0[7]
+set_location_assignment PIN_C18 -to HEX1[0]
+set_location_assignment PIN_D18 -to HEX1[1]
+set_location_assignment PIN_E18 -to HEX1[2]
+set_location_assignment PIN_B16 -to HEX1[3]
+set_location_assignment PIN_A17 -to HEX1[4]
+set_location_assignment PIN_A18 -to HEX1[5]
+set_location_assignment PIN_B17 -to HEX1[6]
+set_location_assignment PIN_A16 -to HEX1[7]
+set_location_assignment PIN_B20 -to HEX2[0]
+set_location_assignment PIN_A20 -to HEX2[1]
+set_location_assignment PIN_B19 -to HEX2[2]
+set_location_assignment PIN_A21 -to HEX2[3]
+set_location_assignment PIN_B21 -to HEX2[4]
+set_location_assignment PIN_C22 -to HEX2[5]
+set_location_assignment PIN_B22 -to HEX2[6]
+set_location_assignment PIN_A19 -to HEX2[7]
+set_location_assignment PIN_F21 -to HEX3[0]
+set_location_assignment PIN_E22 -to HEX3[1]
+set_location_assignment PIN_E21 -to HEX3[2]
+set_location_assignment PIN_C19 -to HEX3[3]
+set_location_assignment PIN_C20 -to HEX3[4]
+set_location_assignment PIN_D19 -to HEX3[5]
+set_location_assignment PIN_E17 -to HEX3[6]
+set_location_assignment PIN_D22 -to HEX3[7]
+set_location_assignment PIN_F18 -to HEX4[0]
+set_location_assignment PIN_E20 -to HEX4[1]
+set_location_assignment PIN_E19 -to HEX4[2]
+set_location_assignment PIN_J18 -to HEX4[3]
+set_location_assignment PIN_H19 -to HEX4[4]
+set_location_assignment PIN_F19 -to HEX4[5]
+set_location_assignment PIN_F20 -to HEX4[6]
+set_location_assignment PIN_F17 -to HEX4[7]
+set_location_assignment PIN_J20 -to HEX5[0]
+set_location_assignment PIN_K20 -to HEX5[1]
+set_location_assignment PIN_L18 -to HEX5[2]
+set_location_assignment PIN_N18 -to HEX5[3]
+set_location_assignment PIN_M20 -to HEX5[4]
+set_location_assignment PIN_N19 -to HEX5[5]
+set_location_assignment PIN_N20 -to HEX5[6]
+set_location_assignment PIN_L19 -to HEX5[7]
+set_location_assignment PIN_B8 -to KEY[0]
+set_location_assignment PIN_A7 -to KEY[1]
+set_location_assignment PIN_A8 -to LEDR[0]
+set_location_assignment PIN_A9 -to LEDR[1]
+set_location_assignment PIN_A10 -to LEDR[2]
+set_location_assignment PIN_B10 -to LEDR[3]
+set_location_assignment PIN_D13 -to LEDR[4]
+set_location_assignment PIN_C13 -to LEDR[5]
+set_location_assignment PIN_E14 -to LEDR[6]
+set_location_assignment PIN_D14 -to LEDR[7]
+set_location_assignment PIN_A11 -to LEDR[8]
+set_location_assignment PIN_B11 -to LEDR[9]
+set_location_assignment PIN_C10 -to SW[0]
+set_location_assignment PIN_C11 -to SW[1]
+set_location_assignment PIN_D12 -to SW[2]
+set_location_assignment PIN_C12 -to SW[3]
+set_location_assignment PIN_A12 -to SW[4]
+set_location_assignment PIN_B12 -to SW[5]
+set_location_assignment PIN_A13 -to SW[6]
+set_location_assignment PIN_A14 -to SW[7]
+set_location_assignment PIN_B14 -to SW[8]
+set_location_assignment PIN_F15 -to SW[9]
+set_location_assignment PIN_P1 -to VGA_B[0]
+set_location_assignment PIN_T1 -to VGA_B[1]
+set_location_assignment PIN_P4 -to VGA_B[2]
+set_location_assignment PIN_N2 -to VGA_B[3]
+set_location_assignment PIN_W1 -to VGA_G[0]
+set_location_assignment PIN_T2 -to VGA_G[1]
+set_location_assignment PIN_R2 -to VGA_G[2]
+set_location_assignment PIN_R1 -to VGA_G[3]
+set_location_assignment PIN_N3 -to VGA_HS
+set_location_assignment PIN_AA1 -to VGA_R[0]
+set_location_assignment PIN_V1 -to VGA_R[1]
+set_location_assignment PIN_Y2 -to VGA_R[2]
+set_location_assignment PIN_Y1 -to VGA_R[3]
+set_location_assignment PIN_N1 -to VGA_VS
+set_location_assignment PIN_AB16 -to GSENSOR_CS_N
+set_location_assignment PIN_Y14 -to GSENSOR_INT[1]
+set_location_assignment PIN_Y13 -to GSENSOR_INT[2]
+set_location_assignment PIN_AB15 -to GSENSOR_SCLK
+set_location_assignment PIN_V11 -to GSENSOR_SDI
+set_location_assignment PIN_V12 -to GSENSOR_SDO
+set_location_assignment PIN_AB5 -to ARDUINO_IO[0]
+set_location_assignment PIN_AB6 -to ARDUINO_IO[1]
+set_location_assignment PIN_AB7 -to ARDUINO_IO[2]
+set_location_assignment PIN_AB8 -to ARDUINO_IO[3]
+set_location_assignment PIN_AB9 -to ARDUINO_IO[4]
+set_location_assignment PIN_Y10 -to ARDUINO_IO[5]
+set_location_assignment PIN_AA11 -to ARDUINO_IO[6]
+set_location_assignment PIN_AA12 -to ARDUINO_IO[7]
+set_location_assignment PIN_AB17 -to ARDUINO_IO[8]
+set_location_assignment PIN_AA17 -to ARDUINO_IO[9]
+set_location_assignment PIN_AB19 -to ARDUINO_IO[10]
+set_location_assignment PIN_AA19 -to ARDUINO_IO[11]
+set_location_assignment PIN_Y19 -to ARDUINO_IO[12]
+set_location_assignment PIN_AB20 -to ARDUINO_IO[13]
+set_location_assignment PIN_AB21 -to ARDUINO_IO[14]
+set_location_assignment PIN_AA20 -to ARDUINO_IO[15]
+set_location_assignment PIN_F16 -to ARDUINO_RESET_N
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
+
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name VHDL_FILE ../../../gpio/led_displays.vhd
+set_global_assignment -name VHDL_FILE ../../../gpio/gpio.vhd
+set_global_assignment -name VHDL_FILE ../../simple_serial_transmitter.vhd
+set_global_assignment -name VHDL_FILE ../../../../alu/m/quick_clz.vhd
+set_global_assignment -name VHDL_FILE ../../../../alu/m/division_functions.vhd
+set_global_assignment -name VHDL_FILE ../../../../alu/m/quick_naive.vhd
+set_global_assignment -name VHDL_FILE ../../../../memory/periphdatabusmux.vhd
+set_global_assignment -name VHDL_FILE ../../../timer/Timer.vhd
+set_global_assignment -name VHDL_FILE ../../../../core/csr.vhd
+set_global_assignment -name VHDL_FILE ../../../../registers/register_file.vhd
+set_global_assignment -name VHDL_FILE ../../../../memory/instructionbusmux.vhd
+set_global_assignment -name VHDL_FILE ../../../../memory/iodatabusmux.vhd
+set_global_assignment -name VHDL_FILE ../../../../memory/databusmux.vhd
+set_global_assignment -name QIP_FILE ../../../../memory/iram_quartus.qip
+set_global_assignment -name VHDL_FILE ../../../../memory/dmemory.vhd
+set_global_assignment -name VHDL_FILE ../../../../decoder/iregister.vhd
+set_global_assignment -name VHDL_FILE ../../../../decoder/decoder_types.vhd
+set_global_assignment -name VHDL_FILE ../../../../decoder/decoder.vhd
+set_global_assignment -name VHDL_FILE ../../../../core/core.vhd
+set_global_assignment -name VHDL_FILE ../../../../alu/m/M_types.vhd
+set_global_assignment -name VHDL_FILE ../../../../alu/m/M.vhd
+set_global_assignment -name VHDL_FILE ../../../../alu/alu_types.vhd
+set_global_assignment -name VHDL_FILE ../../../../alu/alu.vhd
+set_global_assignment -name VHDL_FILE de0_lite.vhd
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name SOURCE_FILE db/de10_lite.cmp.rdb
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/peripherals/simple_serial_transmitter/sint/de10_lite.sdc b/peripherals/simple_serial_transmitter/sint/de10_lite.sdc
new file mode 100644
index 00000000..970e0f20
--- /dev/null
+++ b/peripherals/simple_serial_transmitter/sint/de10_lite.sdc
@@ -0,0 +1,83 @@
+#**************************************************************
+# This .sdc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period "10.0 MHz" [get_ports ADC_CLK_10]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
diff --git a/peripherals/simple_serial_transmitter/sint/pll.ppf b/peripherals/simple_serial_transmitter/sint/pll.ppf
new file mode 100644
index 00000000..e107b0ee
--- /dev/null
+++ b/peripherals/simple_serial_transmitter/sint/pll.ppf
@@ -0,0 +1,12 @@
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/peripherals/simple_serial_transmitter/sint/pll.qip b/peripherals/simple_serial_transmitter/sint/pll.qip
new file mode 100644
index 00000000..65a39c14
--- /dev/null
+++ b/peripherals/simple_serial_transmitter/sint/pll.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "21.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/peripherals/simple_serial_transmitter/sint/pll.vhd b/peripherals/simple_serial_transmitter/sint/pll.vhd
new file mode 100644
index 00000000..04c6901a
--- /dev/null
+++ b/peripherals/simple_serial_transmitter/sint/pll.vhd
@@ -0,0 +1,400 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- altpll
+--
+-- Simulation Library Files(s):
+--
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 21.1.1 Build 850 06/23/2022 SJ Standard Edition
+-- ************************************************************
+
+
+--Copyright (C) 2022 Intel Corporation. All rights reserved.
+--Your use of Intel Corporation's design tools, logic functions
+--and other software and tools, and any partner logic
+--functions, and any output files from any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Intel Program License
+--Subscription Agreement, the Intel Quartus Prime License Agreement,
+--the Intel FPGA IP License Agreement, or other applicable license
+--agreement, including, without limitation, that your use is for
+--the sole purpose of programming logic devices manufactured by
+--Intel and sold by Intel or its authorized distributors. Please
+--refer to the applicable agreement for further details, at
+--https://fpgasoftware.intel.com/eula.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+ PORT
+ (
+ areset : IN STD_LOGIC := '0';
+ inclk0 : IN STD_LOGIC := '0';
+ c0 : OUT STD_LOGIC ;
+ c1 : OUT STD_LOGIC ;
+ locked : OUT STD_LOGIC
+ );
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+ SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
+ SIGNAL sub_wire1 : STD_LOGIC ;
+ SIGNAL sub_wire2 : STD_LOGIC ;
+ SIGNAL sub_wire3 : STD_LOGIC ;
+ SIGNAL sub_wire4 : STD_LOGIC ;
+ SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
+ SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
+ SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+ COMPONENT altpll
+ GENERIC (
+ bandwidth_type : STRING;
+ clk0_divide_by : NATURAL;
+ clk0_duty_cycle : NATURAL;
+ clk0_multiply_by : NATURAL;
+ clk0_phase_shift : STRING;
+ clk1_divide_by : NATURAL;
+ clk1_duty_cycle : NATURAL;
+ clk1_multiply_by : NATURAL;
+ clk1_phase_shift : STRING;
+ compensate_clock : STRING;
+ inclk0_input_frequency : NATURAL;
+ intended_device_family : STRING;
+ lpm_hint : STRING;
+ lpm_type : STRING;
+ operation_mode : STRING;
+ pll_type : STRING;
+ port_activeclock : STRING;
+ port_areset : STRING;
+ port_clkbad0 : STRING;
+ port_clkbad1 : STRING;
+ port_clkloss : STRING;
+ port_clkswitch : STRING;
+ port_configupdate : STRING;
+ port_fbin : STRING;
+ port_inclk0 : STRING;
+ port_inclk1 : STRING;
+ port_locked : STRING;
+ port_pfdena : STRING;
+ port_phasecounterselect : STRING;
+ port_phasedone : STRING;
+ port_phasestep : STRING;
+ port_phaseupdown : STRING;
+ port_pllena : STRING;
+ port_scanaclr : STRING;
+ port_scanclk : STRING;
+ port_scanclkena : STRING;
+ port_scandata : STRING;
+ port_scandataout : STRING;
+ port_scandone : STRING;
+ port_scanread : STRING;
+ port_scanwrite : STRING;
+ port_clk0 : STRING;
+ port_clk1 : STRING;
+ port_clk2 : STRING;
+ port_clk3 : STRING;
+ port_clk4 : STRING;
+ port_clk5 : STRING;
+ port_clkena0 : STRING;
+ port_clkena1 : STRING;
+ port_clkena2 : STRING;
+ port_clkena3 : STRING;
+ port_clkena4 : STRING;
+ port_clkena5 : STRING;
+ port_extclk0 : STRING;
+ port_extclk1 : STRING;
+ port_extclk2 : STRING;
+ port_extclk3 : STRING;
+ self_reset_on_loss_lock : STRING;
+ width_clock : NATURAL
+ );
+ PORT (
+ areset : IN STD_LOGIC ;
+ inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+ clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+ locked : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+BEGIN
+ sub_wire6_bv(0 DOWNTO 0) <= "0";
+ sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
+ sub_wire2 <= sub_wire0(1);
+ sub_wire1 <= sub_wire0(0);
+ c0 <= sub_wire1;
+ c1 <= sub_wire2;
+ locked <= sub_wire3;
+ sub_wire4 <= inclk0;
+ sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
+
+ altpll_component : altpll
+ GENERIC MAP (
+ bandwidth_type => "AUTO",
+ clk0_divide_by => 50,
+ clk0_duty_cycle => 50,
+ clk0_multiply_by => 1,
+ clk0_phase_shift => "0",
+ clk1_divide_by => 1,
+ clk1_duty_cycle => 50,
+ clk1_multiply_by => 1,
+ clk1_phase_shift => "0",
+ compensate_clock => "CLK0",
+ inclk0_input_frequency => 20000,
+ intended_device_family => "MAX 10",
+ lpm_hint => "CBX_MODULE_PREFIX=pll",
+ lpm_type => "altpll",
+ operation_mode => "NORMAL",
+ pll_type => "AUTO",
+ port_activeclock => "PORT_UNUSED",
+ port_areset => "PORT_USED",
+ port_clkbad0 => "PORT_UNUSED",
+ port_clkbad1 => "PORT_UNUSED",
+ port_clkloss => "PORT_UNUSED",
+ port_clkswitch => "PORT_UNUSED",
+ port_configupdate => "PORT_UNUSED",
+ port_fbin => "PORT_UNUSED",
+ port_inclk0 => "PORT_USED",
+ port_inclk1 => "PORT_UNUSED",
+ port_locked => "PORT_USED",
+ port_pfdena => "PORT_UNUSED",
+ port_phasecounterselect => "PORT_UNUSED",
+ port_phasedone => "PORT_UNUSED",
+ port_phasestep => "PORT_UNUSED",
+ port_phaseupdown => "PORT_UNUSED",
+ port_pllena => "PORT_UNUSED",
+ port_scanaclr => "PORT_UNUSED",
+ port_scanclk => "PORT_UNUSED",
+ port_scanclkena => "PORT_UNUSED",
+ port_scandata => "PORT_UNUSED",
+ port_scandataout => "PORT_UNUSED",
+ port_scandone => "PORT_UNUSED",
+ port_scanread => "PORT_UNUSED",
+ port_scanwrite => "PORT_UNUSED",
+ port_clk0 => "PORT_USED",
+ port_clk1 => "PORT_USED",
+ port_clk2 => "PORT_UNUSED",
+ port_clk3 => "PORT_UNUSED",
+ port_clk4 => "PORT_UNUSED",
+ port_clk5 => "PORT_UNUSED",
+ port_clkena0 => "PORT_UNUSED",
+ port_clkena1 => "PORT_UNUSED",
+ port_clkena2 => "PORT_UNUSED",
+ port_clkena3 => "PORT_UNUSED",
+ port_clkena4 => "PORT_UNUSED",
+ port_clkena5 => "PORT_UNUSED",
+ port_extclk0 => "PORT_UNUSED",
+ port_extclk1 => "PORT_UNUSED",
+ port_extclk2 => "PORT_UNUSED",
+ port_extclk3 => "PORT_UNUSED",
+ self_reset_on_loss_lock => "OFF",
+ width_clock => 5
+ )
+ PORT MAP (
+ areset => areset,
+ inclk => sub_wire5,
+ clk => sub_wire0,
+ locked => sub_wire3
+ );
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/peripherals/simple_serial_transmitter/testbench.do b/peripherals/simple_serial_transmitter/testbench.do
new file mode 100644
index 00000000..42917ec5
--- /dev/null
+++ b/peripherals/simple_serial_transmitter/testbench.do
@@ -0,0 +1,191 @@
+#******************************************************************************
+# *
+# Copyright (C) 2019 IFSC *
+# *
+# *
+# All information provided herein is provided on an "as is" basis, *
+# without warranty of any kind. *
+# *
+# File Name: testbench.do *
+# *
+# Function: riscv muticycle simulation script *
+# *
+# REVISION HISTORY: *
+# Revision 0.1.0 08/01/2018 - Initial Revision *
+# Revision 0.2.0 31/05/2021 - Change path and added some peripherals *
+#******************************************************************************
+
+vlib work
+vcom ../../memory/iram_quartus.vhd
+vcom ../../memory/instructionbusmux.vhd
+vcom ../../memory/databusmux.vhd
+vcom ../../memory/dmemory.vhd
+vcom ../../memory/iodatabusmux.vhd
+vcom ../../alu/alu_types.vhd
+vcom ../../alu/alu.vhd
+vcom ../../alu/m/division_functions.vhd
+vcom ../../alu/m/quick_naive.vhd
+vcom ../../alu/m/M_types.vhd
+vcom ../../alu/m/M.vhd
+vcom ../../decoder/decoder_types.vhd
+vcom ../../decoder/iregister.vhd
+vcom ../../decoder/decoder.vhd
+vcom ../../registers/register_file.vhd
+vcom ../../peripherals/gpio/gpio.vhd
+vcom ../../peripherals/gpio/led_displays.vhd
+vcom ../../peripherals/timer/Timer.vhd
+vcom ../../core/csr.vhd
+vcom ../../core/core.vhd
+vcom ../../core/txt_util.vhdl
+vcom ../../core/trace_debug.vhd
+vcom simple_serial_transmitter.vhd
+vcom testbench.vhd
+
+vsim -voptargs="+acc" -t ns work.core_main_testbench
+
+view wave
+add wave -radix binary /clk
+add wave -radix binary /rst
+add wave -height 15 -divider "Instruction Memory"
+add wave -label iAddr -radix hex /address
+add wave -label iWord -radix hex idata
+add wave -label decoded -radix ASCII /debugString
+# add wave /debugString
+# add wave -radix hex /imem/RAM
+# add wave -radix hex /q
+
+add wave -height 15 -divider "PC and Ctrl Targers"
+add wave -radix hex -label pc /myRiscv/pc
+add wave -radix hex -label jal_target /myRiscv/jal_target
+add wave -radix hex -label jalr_target /myRiscv/jalr_target
+add wave -label branch_cmp /myRiscv/branch_cmp
+add wave -radix hex -label jumps /myRiscv/jumps
+
+
+add wave -height 15 -divider "Iregister debug"
+add wave -label opcode /myRiscv/opcodes
+add wave -label rd /myRiscv/rd
+add wave -label rs1 /myRiscv/rs1
+add wave -label rs2 /myRiscv/rs2
+add wave -label imm_i /myRiscv/imm_i
+add wave -label imm_s /myRiscv/imm_s
+add wave -label imm_b /myRiscv/imm_b
+add wave -label imm_u /myRiscv/imm_u
+add wave -label imm_j /myRiscv/imm_j
+
+
+add wave -height 15 -divider "Register file debug"
+ add wave -label registers -radix hex /myRiscv/registers/ram
+ add wave -label w_ena /myRiscv/rf_w_ena
+ add wave -label w_data -radix hex /myRiscv/rw_data
+ add wave -label r1_data -radix hex /myRiscv/rs1_data
+ add wave -label r2_data -radix hex /myRiscv/rs2_data
+
+# decoder debug
+add wave -label states /myRiscv/decoder0/state
+
+add wave -height 15 -divider "GPIO"
+add wave -label enable_exti_mask -radix hex /generic_gpio/enable_exti_mask
+add wave -label edge_exti_mask -radix hex /generic_gpio/edge_exti_mask
+add wave -label output_reg -radix hex /generic_gpio/output_reg
+
+add wave -height 15 -divider "CSR"
+add wave -label interrupts -radix hex /myRiscv/interrupts
+add wave -label pending_interrupts -radix hex /myRiscv/ins_csr/pending_interrupts
+add wave -label mret -radix hex /myRiscv/ins_csr/mret
+add wave -label pending /myRiscv/pending
+add wave -label csr_write /myRiscv/csr_write
+add wave -label csr_addr /myRiscv/imm_i
+add wave -label csr_value -radix hex /myRiscv/csr_value
+add wave -label load_mepc -radix hex /myRiscv/load_mepc
+# add wave -label load_mepc_holder -radix hex /myRiscv/ins_csr/load_mepc_holder
+add wave -label mepc -radix hex /myRiscv/mepc
+add wave -label mretpc -radix hex /myRiscv/mretpc
+add wave -label csr_new -radix hex /myRiscv/rs1_data
+# add wave -label mreg -radix hex /myRiscv/ins_csr/mreg
+
+
+add wave -height 15 -divider "Alu debug"
+add wave -radix dec -label aluData /myRiscv/alu_data
+add wave -radix dec -label aluOut /myRiscv/alu_out
+
+add wave -height 15 -divider "M Extension debug"
+add wave -label clock_32x /myRiscv/clk_32x
+add wave -label code_operator /myRiscv/M_data.code
+add wave -radix dec -label a_integer /myRiscv/M_data.a
+add wave -radix dec -label b_integer /myRiscv/M_data.b
+add wave -radix dec -label M_out /myRiscv/M_out
+
+add wave -height 15 -divider "Data memory debug"
+add wave -label daddr -radix hex /myRiscv/memAddrTypeSBlock/addr
+add wave -label fsm_data -radix hex /dmem/fsm_data
+add wave -label ram_data -radix hex /dmem/ram_data
+add wave -label mState /dmem/state
+add wave -label fsm_we /dmem/fsm_we
+add wave -label ddata_r_mem -radix hex /dmem/q
+add wave -label datamemory -radix hex /dmem/ram_block
+
+
+add wave -height 15 -divider "Data bus"
+add wave -label daddress -radix hex /daddress
+add wave -label ddata_r -radix hex /ddata_r
+add wave -label ddata_w -radix hex /ddata_w
+add wave -label dmask -radix bin /dmask
+add wave -label dcsel /dcsel
+add wave -label d_we /d_we
+add wave -label d_rd /d_rd
+add wave -label d_sig /d_sig
+
+add wave -height 15 -divider "Peripheral Data bus"
+add wave -label daddress -radix hex /daddress
+add wave -label ddata_r_periph -radix hex /ddata_r_periph
+add wave -label ddata_r_gpio -radix hex /ddata_r_gpio
+
+add wave -label gpio_interrupts -radix hex /gpio_interrupts
+add wave -label gpio_input -radix hex /gpio_input
+
+add wave -height 15 -divider "Timer"
+add wave -label enable_timer_irq_mask -radix hex /timer/enable_timer_irq_mask
+add wave -label timer_interrupt -radix hex /timer/timer_interrupt
+add wave -label timer_reset -radix binary /timer/timer_reset
+add wave -label timer_mode -radix unsigned /timer/timer_mode
+add wave -label prescaler -radix unsigned /timer/prescaler
+add wave -label top_counter -radix unsigned /timer/top_counter
+add wave -label counter -radix unsigned /timer/counter
+add wave -label compare_0A -radix unsigned /timer/compare_0A
+add wave -label compare_0B -radix unsigned /timer/compare_0B
+add wave -label compare_1A -radix unsigned /timer/compare_1A
+add wave -label compare_1B -radix unsigned /timer/compare_1B
+add wave -label compare_2A -radix unsigned /timer/compare_2A
+add wave -label compare_2B -radix unsigned /timer/compare_2B
+add wave -label output_0A -radix binary /timer/output_A(0)
+add wave -label output_0B -radix binary /timer/output_B(0)
+add wave -label output_1A -radix binary /timer/output_A(1)
+add wave -label output_1B -radix binary /timer/output_B(1)
+add wave -label output_2A -radix binary /timer/output_A(2)
+add wave -label output_2B -radix binary /timer/output_B(2)
+add wave -label internal_clock -radix binary /timer/internal_clock
+
+
+add wave -height 15 -divider "Input/Output SIM"
+add wave -label LEDR -radix hex /LEDR
+add wave -label HEX0 -radix hex /HEX0
+add wave -label ARDUINO_IO -radix hex /ARDUINO_IO
+
+
+add wave -label RESET -radix binary /simple_serial_transmitter_inst/rst
+add wave -label CLOCK -radix binary /simple_serial_transmitter_inst/clk
+add wave -label DADDRESS -radix hex /simple_serial_transmitter_inst/daddress
+add wave -label DDATA_W -radix hex /simple_serial_transmitter_inst/ddata_w
+add wave -label DDATA_R -radix hex /simple_serial_transmitter_inst/ddata_r
+add wave -label D_WE -radix binary /simple_serial_transmitter_inst/d_we
+add wave -label D_RD -radix binary /simple_serial_transmitter_inst/d_rd
+add wave -label DCSEL -radix binary /simple_serial_transmitter_inst/dcsel
+add wave -label START -radix binary /simple_serial_transmitter_inst/start_w
+add wave -label ADDR -radix binary /simple_serial_transmitter_inst/addr_w
+add wave -label DATA -radix binary /simple_serial_transmitter_inst/data_w
+add wave -label STATE -radix dec /simple_serial_transmitter_inst/state
+add wave -label SDATA -radix binary /simple_serial_transmitter_inst/sdata
+
+run 8000 us
+wave zoomfull
diff --git a/peripherals/simple_serial_transmitter/testbench.vhd b/peripherals/simple_serial_transmitter/testbench.vhd
new file mode 100644
index 00000000..f658c097
--- /dev/null
+++ b/peripherals/simple_serial_transmitter/testbench.vhd
@@ -0,0 +1,341 @@
+-------------------------------------------------------
+--! @file
+--! @brief RISCV Testbench
+-- This testbench simulates a core with a
+-- generic IO hardware and a Timer
+--
+-------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.decoder_types.all;
+
+
+entity core_main_testbench is
+ generic(
+ --! Num of 32-bits memory words
+ IMEMORY_WORDS : integer := 1024; --!= 4K (1024 * 4) bytes
+ DMEMORY_WORDS : integer := 1024 --!= 2k (512 * 2) bytes
+ );
+
+ port(
+ ----------- SEG7 ------------
+ HEX0 : out std_logic_vector(7 downto 0);
+ HEX1 : out std_logic_vector(7 downto 0);
+ HEX2 : out std_logic_vector(7 downto 0);
+ HEX3 : out std_logic_vector(7 downto 0);
+ HEX4 : out std_logic_vector(7 downto 0);
+ HEX5 : out std_logic_vector(7 downto 0);
+ ----------- SW ------------
+
+ SW: in std_logic_vector(9 downto 0);
+ LEDR: out std_logic_vector(9 downto 0);
+
+ ---------- ARDUINO IO -----
+ ARDUINO_IO: inout std_logic_vector(15 downto 0)
+ );
+
+
+end entity core_main_testbench;
+
+architecture RTL of core_main_testbench is
+ -- Clocks and reset
+ signal clk : std_logic;
+ signal clk_32x : std_logic;
+ signal rst : std_logic;
+
+ -- Instruction bus and instruction memory
+ signal address : std_logic_vector(9 downto 0);
+ signal iaddress : unsigned(15 downto 0);
+ signal idata : std_logic_vector(31 downto 0);
+
+ -- Data bus
+ signal daddress : unsigned(31 downto 0);
+ signal ddata_r : std_logic_vector(31 downto 0);
+ signal ddata_w : std_logic_vector(31 downto 0);
+ signal dmask : std_logic_vector(3 downto 0);
+ signal dcsel : std_logic_vector(1 downto 0);
+ signal d_we : std_logic := '0';
+ signal ddata_r_mem : std_logic_vector(31 downto 0);
+ signal d_rd : std_logic;
+ signal d_sig : std_logic;
+
+ -- Modelsim debug signals
+ signal cpu_state : cpu_state_t;
+ signal debugString : string(1 to 40) := (others => '0');
+
+ -- I/O signals
+ signal interrupts : std_logic_vector(31 downto 0);
+ signal ddata_r_gpio : std_logic_vector(31 downto 0);
+ signal gpio_input : std_logic_vector(31 downto 0);
+ signal gpio_output : std_logic_vector(31 downto 0);
+
+ signal ddata_r_timer : std_logic_vector(31 downto 0);
+ signal timer_interrupt : std_logic_vector(5 downto 0);
+ signal ddata_r_periph : std_logic_vector(31 downto 0);
+ signal ddata_r_stepmot : std_logic_vector(31 downto 0);
+ signal ddata_r_sdram : std_logic_vector(31 downto 0);
+
+ signal gpio_interrupts : std_logic_vector(6 downto 0);
+ signal ddata_r_segments : std_logic_vector(31 downto 0);
+ signal ddata_r_uart : std_logic_vector(31 downto 0);
+ signal ddata_r_adc : std_logic_vector(31 downto 0);
+ signal ddata_r_i2c : std_logic_vector(31 downto 0);
+ signal ddata_r_dif_fil : std_logic_vector(31 downto 0);
+ signal ddata_r_lcd : std_logic_vector(31 downto 0);
+ signal ddata_r_nn_accelerator : std_logic_vector(31 downto 0);
+ signal ddata_r_fir_fil : std_logic_vector(31 downto 0);
+ signal ddata_r_spwm : std_logic_vector(31 downto 0);
+ signal ddata_r_crc : std_logic_vector(31 downto 0);
+ signal ddata_r_key : std_logic_vector(31 downto 0);
+ signal ddata_r_accelerometer : std_logic_vector(31 downto 0);
+
+ -- Timer
+ signal ifcap : std_logic;
+
+
+begin
+
+ clock_driver : process
+ constant period : time := 1000 ns;
+ begin
+ clk <= '0';
+ wait for period / 2;
+ clk <= '1';
+ wait for period / 2;
+ end process clock_driver;
+
+ --! Division unit clock
+ clock_driver_32x : process
+ constant period : time := 20 ns;
+ begin
+ clk_32x <= '0';
+ wait for period / 2;
+ clk_32x <= '1';
+ wait for period / 2;
+ end process clock_driver_32x;
+
+ reset : process is
+ begin
+ rst <= '1';
+ wait for 150 ns;
+ rst <= '0';
+ wait;
+ end process reset;
+
+ -- Connect gpio data to output hardware
+ LEDR <= gpio_output(9 downto 0);
+
+ -- Connect input hardware to gpio data
+ gpio_test: process
+ begin
+ gpio_input <= (others => '0');
+ wait for 6 ms;
+
+ -- Generate a input pulse (External IRQ 0 or pooling)
+ gpio_input(0) <= '1';
+ wait for 1 us;
+ gpio_input(0) <= '0';
+
+ -- Generate a input pulse (External IRQ 1 or pooling)
+ wait for 200 us;
+ gpio_input(1) <= '1';
+ wait for 1 us;
+ gpio_input(1) <= '0';
+
+ wait;
+ end process;
+
+ -- IMem shoud be read from instruction and data buses
+ -- Not enough RAM ports for instruction bus, data bus and in-circuit programming
+ instr_mux: entity work.instructionbusmux
+ port map(
+ d_rd => d_rd,
+ dcsel => dcsel,
+ daddress => daddress,
+ iaddress => iaddress,
+ address => address
+ );
+
+ -- 32-bits x 1024 words quartus RAM (dual port: portA -> riscV, portB -> In-System Mem Editor
+ iram_quartus_inst : entity work.iram_quartus
+ port map(
+ address => address(9 downto 0),
+ byteena => "1111",
+ clock => clk,
+ data => (others => '0'),
+ wren => '0',
+ q => idata
+ );
+
+ -- dmemory_address <= daddress;
+ -- Data Memory RAM
+ dmem : entity work.dmemory
+ generic map(
+ MEMORY_WORDS => DMEMORY_WORDS
+ )
+ port map(
+ rst => rst,
+ clk => clk,
+ data => ddata_w,
+ address => daddress,
+ we => d_we,
+ signal_ext => d_sig,
+ csel => dcsel(0),
+ dmask => dmask,
+ q => ddata_r_mem
+ );
+
+ -- Adress space mux ((check sections.ld) -> Data chip select:
+ -- 0x00000 -> Instruction memory
+ -- 0x20000 -> Data memory
+ -- 0x40000 -> Input/Output generic address space
+ -- 0x60000 -> SDRAM address space
+ data_bus_mux: entity work.databusmux
+ port map(
+ dcsel => dcsel,
+ idata => idata,
+ ddata_r_mem => ddata_r_mem,
+ ddata_r_periph => ddata_r_periph,
+ ddata_r_sdram => ddata_r_sdram,
+ ddata_r => ddata_r
+ );
+
+ io_data_bus_mux: entity work.iodatabusmux
+ port map(
+ daddress => daddress,
+ ddata_r_gpio => ddata_r_gpio,
+ ddata_r_segments => ddata_r_segments,
+ ddata_r_uart => ddata_r_uart,
+ ddata_r_adc => ddata_r_adc,
+ ddata_r_i2c => ddata_r_i2c,
+ ddata_r_timer => ddata_r_timer,
+ ddata_r_dif_fil => ddata_r_dif_fil,
+ ddata_r_stepmot => ddata_r_stepmot,
+ ddata_r_lcd => ddata_r_lcd,
+ ddata_r_nn_accelerator => ddata_r_nn_accelerator,
+ ddata_r_fir_fil => ddata_r_fir_fil,
+ ddata_r_spwm => ddata_r_spwm,
+ ddata_r_crc => ddata_r_crc,
+ ddata_r_key => ddata_r_key,
+ ddata_r_accelerometer => ddata_r_accelerometer,
+ ddata_r_periph => ddata_r_periph
+ );
+
+ -- Softcore instatiation
+ myRiscv : entity work.core
+ port map(
+ clk => clk,
+ rst => rst,
+ clk_32x => clk_32x,
+ iaddress => iaddress,
+ idata => idata,
+ daddress => daddress,
+ ddata_r => ddata_r,
+ ddata_w => ddata_w,
+ d_we => d_we,
+ d_rd => d_rd,
+ d_sig => d_sig,
+ dcsel => dcsel,
+ dmask => dmask,
+ interrupts=>interrupts,
+ state => cpu_state
+ );
+
+ -- Group IRQ signals.
+ irq_signals: process(timer_interrupt,gpio_interrupts)
+ begin
+ interrupts <= (others => '0');
+ interrupts(24 downto 18) <= gpio_interrupts(6 downto 0);
+ interrupts(30 downto 25) <= timer_interrupt;
+ end process;
+
+
+ -- Timer instantiation
+ timer : entity work.Timer
+ generic map(
+ prescaler_size => 16,
+ compare_size => 32
+ )
+ port map(
+ clock => clk,
+ reset => rst,
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => ddata_r_timer,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+ timer_interrupt => timer_interrupt,
+ ifcap => ifcap
+ );
+
+ -- Generic GPIO module instantiation
+ generic_gpio: entity work.gpio
+ port map(
+ clk => clk,
+ rst => rst,
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => ddata_r_gpio,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+ input => gpio_input,
+ output => gpio_output,
+ gpio_interrupts => gpio_interrupts
+ );
+
+ generic_displays : entity work.led_displays
+ port map(
+ clk => clk,
+ rst => rst,
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => ddata_r_segments,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+ hex0 => HEX0,
+ hex1 => HEX1,
+ hex2 => HEX2,
+ hex3 => HEX3,
+ hex4 => HEX4,
+ hex5 => HEX5,
+ hex6 => open,
+ hex7 => open
+ );
+
+ -- FileOutput DEBUG
+ debug : entity work.trace_debug
+ generic map(
+ MEMORY_WORDS => IMEMORY_WORDS
+ )
+ port map(
+ pc => iaddress,
+ data => idata,
+ inst => debugString
+ );
+
+
+ simple_serial_transmitter_inst : entity work.simple_serial_transmitter
+ port map(
+ clk => clk,
+ rst => rst,
+ daddress => daddress,
+ ddata_w => ddata_w,
+ ddata_r => open,
+ d_we => d_we,
+ d_rd => d_rd,
+ dcsel => dcsel,
+ dmask => dmask,
+ sdata => ARDUINO_IO(0)
+ );
+
+end architecture RTL;
diff --git a/software/_core/hardware.h b/software/_core/hardware.h
index 741777ff..57ecab67 100644
--- a/software/_core/hardware.h
+++ b/software/_core/hardware.h
@@ -79,8 +79,9 @@
#define FIR_FILT_BASE_ADDRESS (*(_IO32 *) (PERIPH_BASE + 13*16*4))
#define KEYBOARD_BASE_ADDRESS (*(_IO32 *) (PERIPH_BASE + 14*16*4))
#define CRC_BASE_ADDRESS (*(_IO32 *) (PERIPH_BASE + 15*16*4))
-#define SPWM_BASE_ADDRESS (*(_IO32 *) (PERIPH_BASE + 17*16*4))
-#define ACCELEROMETER_BASE_ADDRESS (*(_IO32 *) (PERIPH_BASE + 18*16*4))
+#define SPWM_BASE_ADDRESS (*(_IO32 *) (PERIPH_BASE + 17*16*4))
+#define ACCELEROMETER_BASE_ADDRESS (*(_IO32 *) (PERIPH_BASE + 18*16*4))
+#define SIMPLE_SERIAL_TRANSMITTER_ADDRESS (*(_IO32 *) (PERIPH_BASE + 19*16*4))
//#define TFT_DATA0 (*(_IO32 *) (PERIPH_BASE + 32))
diff --git a/software/simple_serial_transmitter/Makefile b/software/simple_serial_transmitter/Makefile
new file mode 100644
index 00000000..3773b562
--- /dev/null
+++ b/software/simple_serial_transmitter/Makefile
@@ -0,0 +1,53 @@
+ifndef RISCV_TOOLS_PREFIX
+RISCV_TOOLS_PREFIX = C:/Workspace_ProjetoFinal_DLP/riscv-multicycle-master/compiler/gcc/bin/riscv-none-embed-
+#RISCV_TOOLS_PREFIX = riscv-multicycle-master
+#RISCV_TOOLS_PREFIX =C:PROJETO_FINAL\riscv-multicycle-master\compiler\gcc
+#RISCV_TOOLS_PREFIX = C:PROJETO_FINAL\riscv-multicycle-master
+
+
+endif
+
+
+QUARTUS_DIR=~/Data/Apps/intelFPGA/20.1/quartus/bin/
+CXX = $(RISCV_TOOLS_PREFIX)g++ -march=rv32im
+CC = $(RISCV_TOOLS_PREFIX)gcc -march=rv32im -O1 -fpack-struct
+AS = $(RISCV_TOOLS_PREFIX)gcc -march=rv32im
+#CXXFLAGS = -MD -O1 -Wall -std=c++11
+#CCFLAGS = -MD -O1 -Wall
+#LDFLAGS = -Wl,--gc-sections,--no-relax
+LDFLAGS = -Wl
+LDLIBS =
+MAIN = simple_serial_transmitter
+
+quartus_$(MAIN).hex: $(MAIN)32.hex
+ python3 ../hex8tointel.py $(MAIN).tmp > quartus_$(MAIN).hex
+ del $(MAIN)32.hex
+
+$(MAIN)32.hex: $(MAIN).elf ../hex8tohex32.py
+ $(RISCV_TOOLS_PREFIX)objcopy -O verilog $(MAIN).elf $(MAIN).tmp
+ $(RISCV_TOOLS_PREFIX)objdump -h -S $(MAIN).elf > "$(MAIN).lss"
+ python3 ../hex8tohex32.py $(MAIN).tmp > $(MAIN)32.hex
+
+
+
+start.o: ../_core/start.S
+ $(CC) -c -nostdlib ../_core/start.S $(LDLIBS)
+
+$(MAIN).elf: $(MAIN).o start.o ../_core/syscalls.o ../_core/utils.o ../gpio/gpio.o simple_serial_transmitter.o
+ $(CC) $(LDFLAGS),-Map=$(MAIN).map -o $@ $^ -T ../_core/sections.ld $(LDLIBS)
+
+sint:
+ $(QUARTUS_DIR)quartus_sh --flow compile ../../peripherals/gpio/sint/de10_lite/de10_lite.cdf
+
+fpga:
+ $(QUARTUS_DIR)quartus_pgm -z -m JTAG -o "p;../../peripherals/gpio/sint/de10_lite/output_files/de10_lite.sof"
+
+flash: quartus_$(MAIN).hex
+ $(QUARTUS_DIR)quartus_stp_tcl -t "flash.tcl"
+
+clean:
+ del /f /q $(MAIN).elf $(MAIN).hex $(MAIN)32.hex quartus_$(MAIN).hex 2>nul
+ del /f $(MAIN).elf $(MAIN).hex $(MAIN)32.hex quartus_$(MAIN).hex
+
+-include *.d
+.PHONY: test clean
\ No newline at end of file
diff --git a/software/simple_serial_transmitter/quartus_simple_serial_transmitter.hex b/software/simple_serial_transmitter/quartus_simple_serial_transmitter.hex
new file mode 100644
index 00000000..77800ecf
--- /dev/null
+++ b/software/simple_serial_transmitter/quartus_simple_serial_transmitter.hex
@@ -0,0 +1,894 @@
+:0400000030047073e5
+:040001000000029762
+:040002005042829353
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diff --git a/software/simple_serial_transmitter/serial_transmitter.c b/software/simple_serial_transmitter/serial_transmitter.c
new file mode 100644
index 00000000..ece38d81
--- /dev/null
+++ b/software/simple_serial_transmitter/serial_transmitter.c
@@ -0,0 +1,34 @@
+// GABRIEL ROMERO E YURI MARQUES
+// SIMPLE SERIAL TRANSMITTER
+
+// Online C compiler to run C program online
+#include "../_core/utils.h"
+#include "../_core/hardware.h"
+#include "../gpio/gpio.h"
+
+#include
+#include
+#include
+
+#include "serial_transmitter.h"
+
+void main(){
+
+ uint32_t data = 0;
+
+ while(1){
+
+ SERIAL_TRANSMITTER->addr = 0xff;
+ SERIAL_TRANSMITTER->data = data;
+ SERIAL_TRANSMITTER->start = 1;
+ HEX0 = 1;
+ OUTBUS = data;
+
+ delay_(100000);
+
+ SERIAL_TRANSMITTER->start = 0;
+ HEX0 = 0;
+ data++;
+
+ };
+}
diff --git a/software/simple_serial_transmitter/serial_transmitter.h b/software/simple_serial_transmitter/serial_transmitter.h
new file mode 100644
index 00000000..eb33b00c
--- /dev/null
+++ b/software/simple_serial_transmitter/serial_transmitter.h
@@ -0,0 +1,20 @@
+// GABRIEL ROMERO E YURI MARQUES
+// SIMPLE SERIAL TRANSMITTER
+
+#ifndef __SERIAL_TRANSMITTER_H
+#define __SERIAL_TRANSMITTER_H
+
+#include "../_core/hardware.h"
+
+
+typedef struct {
+ _IO32 addr;
+ _IO32 data;
+ _IO32 start;
+
+}serial_transmitter_t;
+
+
+#define SERIAL_TRANSMITTER ((serial_transmitter_t *) &SIMPLE_SERIAL_TRANSMITTER_ADDRESS)
+
+#endif