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‎05XX0405.EC3

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‎061100A.EJL

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‎1800ST.C

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// DISCLAIMER
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//
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// AT KEITHLEY METRABYTE WE TAKE PRIDE IN OUR SERVICING
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// OUR CUSTOMERS. WE ARE PLEASED TO OFFER YOU THIS SOFTWARE
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// AID PROGRAM FREE OF CHARGE.
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//
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// *******BEFORE INSTALLING THIS SOFTWARE*******
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// *******PLEASE BE AWARE OF THE FOLLOWING******
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//
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// THIS IS NOT A STANDARD KEITHLEY METRABYTE PRODUCT.
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//
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// THIS SOFTWARE DOES NOT PROVIDE ANY WARRANTIES
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// AND IS NOT SUBJECT TO TECHNICAL SUPPORT.
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//
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// KEITHLEY INSTRUMENTS INC., SHALL NOT BE LIABLE
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// FOR ANY SPECIAL, INCIDENTAL OR CONSEQUENTIAL
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// DAMAGES RELATED TO THE USE OF THIS SOFTWARE.
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//
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// WE SINCERELY HOPE THAT THIS AID HELPS YOU GET THE
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// OPTIMAL USE OF YOUR KEITHLEY METRABYTE PRODUCT.
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//
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// DAS-1800ST Register Level Program Example
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#include <stdio.h>
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#include <conio.h>
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#include <dos.h>
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#define base_adr 0x320
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#define data_sel base_adr + 2 // Data Select Register,R/W
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#define dig_io base_adr + 3 // Digital I/O Register,R/W
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#define ctrl_a base_adr + 4 // Control Register A,R/W
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#define ctrl_b base_adr + 5 // Control Register B,R/W
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#define ctrl_c base_adr + 6 // Control Register C,R/W
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#define status base_adr + 7 // Status Register,R/W
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#define burst_length base_adr + 8 // Burst Length Register,R/W
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#define burst_rate base_adr + 9 // Burst Mode Conv. Rate,R/W
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#define qram_adr base_adr + 10 // QRAM Address Start,R/W
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#define counter_0 base_adr + 12 // Counter 0 Register,R/W
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#define counter_1 base_adr + 13 // Counter 1 Register,R/W
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#define counter_2 base_adr + 14 // Counter 2 Register,R/W
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#define ctr_ctrl base_adr + 15 // Counter Control Reg.,R/W
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int read_dig_in(void);
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void scan_burst(void);
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void scan_paced(void);
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void set_chan_list(void);
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void set_dig_out(int);
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void set_pace_clk(void);
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void software_measure(void);
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unsigned int ad_data, ad_status, choice = 0;
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unsigned int i;
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void main(void)
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{
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int dig_value;
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float vout;
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clrscr();
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do
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{
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gotoxy(1,1);
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printf("\n Enter 1 for Software Measure");
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printf("\n Enter 2 for Scan Burst Mode");
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printf("\n Enter 3 for Scan Paced Mode");
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printf("\n Enter 4 for Set Digital Out");
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printf("\n Enter 5 for Read Digital In");
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printf("\n\n");
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scanf("%d",&choice);
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switch(choice)
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{
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case 1:
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software_measure();
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break;
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case 2:
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scan_burst();
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break;
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case 3:
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scan_paced();
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break;
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case 4:
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printf("\n Enter Digital Output ");
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scanf("%d",&dig_value);
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set_dig_out(dig_value);
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break;
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case 5:
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i = read_dig_in();
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printf("\n Dig In = %d",i);
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break;
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}
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delay(250);
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}
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while (choice <6);
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printf("\n\n Done");
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}
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int read_dig_in()
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{
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return( (int)(inp(dig_io) & 0x0f));
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}
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void scan_burst()
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{
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set_pace_clk();
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set_chan_list();
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// Set up the A/D
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outp(ctrl_c, 0x45); // Bipolar, SE, Burst, Int Clk
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outp(data_sel, 0x00); // data from A/D
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outp(burst_length, 4); // Burse length 4 chan
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outp(burst_rate, 9); // 100Khz
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outp(ctrl_a, 0x00); // soft gate,disable ctr,rst fifo
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outp(ctrl_a, 0x05); // soft gate,start ctr,enab fifo
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outp(status, 0x80); // Enable A/D conversions
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while (((inp(status) & 0x20) == 0) && (!kbhit() ));
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outp(status, 0x00); // Disable A/D conversions
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outp(ctrl_a, 0x01); // soft gate,disable ctr,enab fifo
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outp(data_sel, 0x00); // select data from A/D
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printf("\n");
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for (i=0; i<4; i++)
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{
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ad_data = inpw(base_adr)& 0xfff;// Read A/D Twos Complement
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ad_data ^= 0x800; // XOR to get Comp Bin Code
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printf("%d %x h\t",i, ad_data);
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}
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}
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void scan_paced()
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{
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set_pace_clk();
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set_chan_list();
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// Set up the A/D
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outp(ctrl_c, 0x41); // Bipolar, SE, Burst, Int Clk
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outp(data_sel, 0x00); // data from A/D
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outp(ctrl_a, 0x00); // soft gate,disable ctr,rst fifo
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outp(ctrl_a, 0x05); // soft gate,start ctr,enab fifo
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outp(status, 0x80); // Enable A/D conversions
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while ( ((inp(status) & 0x20) == 0) && (!kbhit() ));
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outp(status, 0x00); // Disable A/D conversions
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outp(ctrl_a, 0x01); // soft gate,disable ctr,enab fifo
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outp(data_sel, 0x00); // select data from A/D
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printf("\n");
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for (i=0; i<4; i++)
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{
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ad_data = inpw(base_adr)& 0xfff;// Read A/D Twos Complement
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ad_data ^= 0x800; // XOR to get Comp Bin Code
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printf("%d %x h \t",i,ad_data);
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}
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}
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void set_chan_list()
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{
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outp(data_sel, 0x01); // select QRAM
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outp(qram_adr, 0x03); // # of mux channels = 4
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outpw(base_adr, 0x00); // chan 0, gain 1
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outpw(base_adr, 0x101); // chan 1, gain 2 or 10
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outpw(base_adr, 0x02); // chan 2, gain 1
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outpw(base_adr, 0x03); // chan 3, gain 1
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outp(qram_adr, 0x03); // reset to start addr of qram
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}
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void set_dig_out(int value)
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{
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value &= 0xff;
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outpw(dig_io, value);
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}
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void set_pace_clk()
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{
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// sample rate = 1KHz
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outp(ctr_ctrl, 0xb4); // Ctr 2, mode 2, lsb-msb
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outp(counter_2, 0x0a); // Lsb of 10 dec.
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outp(counter_2, 0x00); // Msb of 10 dec.
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outp(ctr_ctrl, 0x74); // Ctr 1, mode 2, lsb-msb
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outp(counter_1, 0xf4); // Lsb of 500 dec.
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outp(counter_1, 0x01); // Msb of 500 dec.
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}
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void software_measure()
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{
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// Set up the QRAM
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outp(data_sel, 0x01); // select QRAM
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outp(qram_adr, 0x00); // starting addr for mux chan
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outp(base_adr, 0x00); // chan 0, gain 1
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outp(qram_adr, 0x00); // reset to start addr of qram
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// Set up the A/D
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outp(ctrl_c, 0x40); // Bipolar, SE
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outp(ctrl_a, 0x00); // reset fifo
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outp(data_sel, 0x00); // data from A/D
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outp(ctrl_a, 0x01); // enable fifo
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outp(status, 0x80); // Enable A/D conversions
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outp(base_adr, 0x00); // start A/D
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while ( (inp(status) & 0x40) == 0x00); // wait for Fifo NOT Empty
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ad_data = inpw(base_adr)& 0xfff; // Read A/D Twos Complement
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outp(ctrl_a, 0x00); // disable fifo
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ad_data ^= 0x800; // XOR to get Comp Bin Code
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printf("\n A/D Data %x h",ad_data);
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}
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