Skip to content

Commit fc729b7

Browse files
committed
Makefile accepting arguements, tracefile and output file changed
1 parent 4724137 commit fc729b7

39 files changed

+317
-93
lines changed

.gitignore

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,9 @@
1+
work/
2+
transcript
13
sim/work
24
sim/transcript
35
sim/dram
6+
outs/
47
sim/*.wlf
58
sim/*.mti
69
sim/*.mpf

Makefile

Lines changed: 44 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,53 @@
11
# makefile for standard compilation
2-
.PHONY : queue parser all clean
2+
.PHONY : all clean VLOG
33

4-
queue:
5-
$(MAKE) -C sim queue
4+
sim_dir := $(shell pwd)/sim/
5+
source_dir := $(shell pwd)/hdl/
6+
traces_dir := $(shell pwd)/traces/
7+
out_dir := $(shell pwd)/outs/
8+
sv_files := $(shell find $(source_dir) -name '*.sv')
69

7-
parser:
8-
$(MAKE) -C sim parser
10+
top_module = "queue_tb"
911

10-
debug:
11-
$(MAKE) -C sim debug
12+
tracefile = $(traces_dir)/our_tracefiles/trace.txt
13+
outfile = $(out_dir)/dram
14+
plus_args := +tracefile=$(tracefile) +outfile=$(outfile)
1215

13-
all:
14-
$(MAKE) -C sim all
16+
silent: VLOG
17+
cd $(sim_dir)
18+
vsim -c -do "run -all ; q" +nowarn3691 \
19+
work.$(top_module) \
20+
$(plus_args)
1521

16-
gui:
17-
$(MAKE) -C sim gui
22+
VLIB:
23+
cd $(sim_dir)
24+
vlib work
25+
26+
VLOG: VLIB
27+
cd $(sim_dir)
28+
vlog hdl/global_defs.sv
29+
vlog $(sv_files)
30+
31+
all: VLOG
32+
cd $(sim_dir)
33+
vsim -c -do "run -all ; q" +nowarn3691 \
34+
work.$(top_module) \
35+
+debug_dram +debug_queue +per_clk \
36+
$(plus_args)
37+
38+
queue: VLOG
39+
cd $(sim_dir)
40+
vsim -c -do "run -all ; q" +nowarn3691 \
41+
work.$(top_module) \
42+
+debug_queue \
43+
$(plus_args)
44+
45+
dram: VLOG
46+
cd $(sim_dir)
47+
vsim -c -do "run -all ; q" +nowarn3691 \
48+
work.$(top_module) \
49+
+debug_dram \
50+
$(plus_args)
1851

1952
clean:
2053
echo "why?"

README.md

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,38 +1,38 @@
1-
# ECE 585 Fall 2021 Final Project
1+
# ECE 585 Fall 2021 Final Project Group 12
22

3-
output dram command trace file - `sim/dram`
3+
## some things
44

5-
## build instructions
5+
* [github repo](https://github.com/vtkhatri/ece585f21_final_project)
6+
* tracefiles from presentation - `traces/presentation_tracefiles/t*.trace`
7+
* output files for these stored in - `outs/t*.out`
8+
* group tracefiles or checking - `traces/our_tracefiles/*.txt`
69

7-
```
8-
make # just output to sim/dram with minimal prints
9-
make debug # output to sim/dram and enable all debugging prints
10-
make dram # output to sim/dram and enable dram prints
11-
make queue # output to sim/dram and enable queue prints
12-
```
10+
---
1311

14-
## custom tracefile
12+
To execute all presentation tracefiles use single line command -
1513

16-
for Makefile builds, the `traces/trace.txt` symbolic link is used as the input tracefile.\
17-
this behavior can be changed in 2 ways -
14+
```
15+
for i in {0..13}; do make silent tracefile=$PWD/traces/presentation_tracefiles/t$i.trace outfile=$PWD/outs/t$i.out; done
16+
```
1817

19-
### changing the symbolic link
18+
## build instructions
2019

21-
* remove `traces/trace.txt` symbolic link
22-
* make a new symbolic link
2320
```
24-
cd traces
25-
ln -s <full_path_to_custom_trace_file> trace.txt
26-
cd ../sim
27-
make
21+
make silent tracefile=<trace_file> outfile=<out_file>
22+
make all tracefile=<trace_file> outfile=<out_file> # to get all debug prints, with +per_clk
23+
make dram tracefile=<trace_file> outfile=<out_file> # to get dram debug prints only
24+
make queue tracefile=<trace_file> outfile=<out_file> # to get queue debug prints only
2825
```
29-
3026
### manually passing as plusarg to vsim command
3127

3228
```
3329
cd sim
3430
vlib work
3531
vlog ../hdl/global_defs.sv # this is done to ensure package is imported properly
3632
vlog ../hdl/*.sv
37-
vsim -c -do "run all ; q" +nowarn3691 work.queue_tb +tracefile=<full_path_to_custom_tracefile>
33+
vsim -c -do "run all ; q" +nowarn3691 work.queue_tb +tracefile=<trace_file> +outfile=<out_file>
3834
```
35+
36+
## report
37+
38+
report is present in `docs/report.md`

hdl/queue.sv

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,11 @@
1414

1515
import global_defs::*;
1616

17+
// we also need filepath with tracefile, so we extrace PWD using getenv function
18+
// make use of the SystemVerilog C programming interface
19+
// https://stackoverflow.com/questions/33394999/how-can-i-know-my-current-path-in-system-verilog
20+
import "DPI-C" function string getenv(input string env_name);
21+
1722
module queue
1823
(
1924
// inputs
@@ -62,7 +67,7 @@ prev_operation_t previous_operation;
6267
logic output_allowed_normal;
6368

6469
int unsigned dram_file;
65-
string dram_filename = "dram";
70+
string dram_filename;
6671

6772
// for access scheduling, checking if current queue entry is inserted
6873
logic [QUEUE_SIZE-1:0] is_active;
@@ -80,6 +85,12 @@ logic [TIMER_WIDTH-1:0] activate_countup;
8085
logic [TIMER_WIDTH-1:0] column_countup;
8186

8287
initial begin : dram_file_open
88+
if (!$value$plusargs("outfile=%s", dram_filename)) begin
89+
dram_filename = {getenv("PWD"), "/../outs/dram"};
90+
$display("No output file provided eg. +outfile=<full_path_to_file>");
91+
$display("taking output file as default (%s)", dram_filename);
92+
end
93+
8394
dram_file = $fopen(dram_filename, "w");
8495
if (dram_file == 0) begin
8596
$fatal("Could not open dram output file (%s)", dram_filename);

sim/Makefile

Lines changed: 0 additions & 59 deletions
This file was deleted.
File renamed without changes.
File renamed without changes.
File renamed without changes.

0 commit comments

Comments
 (0)