Syntax: Allow verilogExpression inside itself

vhda · vhda · commit dbfad2bbba38 · 2017-10-21T01:14:25.000+01:00
Fixes PR #157
diff --git a/plugin/verilog_systemverilog.vim b/plugin/verilog_systemverilog.vim
@@ -89,7 +89,7 @@ let g:verilog_syntax = {
                         \ 'syn_argument': 'transparent keepend contains=verilogComment,verilogNumber,verilogOperator,verilogString',
                         \ }],
       \ 'baseCluster' : [{
-                        \ 'cluster'     : 'verilogComment,verilogNumber,verilogOperator,verilogString,verilogConstant,verilogGlobal,verilogMethod,verilogObject,verilogIfdefContainer'
+                        \ 'cluster'     : 'verilogComment,verilogNumber,verilogOperator,verilogString,verilogConstant,verilogGlobal,verilogMethod,verilogObject,verilogConditional,verilogIfdefContainer'
                         \ }],
       \ 'block'       : [{
                         \ 'match_start' : '\<begin\>',
@@ -143,7 +143,7 @@ let g:verilog_syntax = {
                         \ 'match_start' : '(',
                         \ 'match_end'   : ')',
                         \ 'highlight'   : 'verilogOperator',
-                        \ 'syn_argument': 'transparent contains=@verilogBaseCluster,verilogStatement',
+                        \ 'syn_argument': 'transparent contains=@verilogBaseCluster,verilogExpression,verilogStatement',
                         \ 'no_fold'     : '1',
                         \ }],
       \ 'function'    : [{
diff --git a/test/syntax.sv b/test/syntax.sv
@@ -1,10 +1,14 @@
-module mymodule(
-  input  wire a,
-  input  wire b,
-  `ifdef MACRO
-  input  wire c,
-  `endif
-  output wire y
+module #(
+    parameter TEST1 = $clog(0),
+    parameter TEST2 = $clog(1),
+    parameter TEST3 = $clog(2)
+) mymodule(
+    input  wire a,
+    input  wire b,
+    `ifdef MACRO
+    input  wire c,
+    `endif
+    output wire y
 );
 
 endmodule
diff --git a/test/syntax.sv.html b/test/syntax.sv.html
@@ -1,12 +1,16 @@
 <body>
 <pre>
-<span class="Statement">module</span> <span class="Identifier">mymodule</span><span class="Special">(</span>
-  <span class="Statement">input</span>  <span class="Statement">wire</span> a<span class="Special">,</span>
-  <span class="Statement">input</span>  <span class="Statement">wire</span> b<span class="Special">,</span>
-  <span class="PreProc">`ifdef</span> <span class="Constant">MACRO</span>
-  <span class="Statement">input</span>  <span class="Statement">wire</span> c<span class="Special">,</span>
-  <span class="PreProc">`endif</span>
-  <span class="Statement">output</span> <span class="Statement">wire</span> y
+<span class="Statement">module</span> <span class="Special">#(</span>
+    <span class="Statement">parameter</span> <span class="Constant">TEST1</span> <span class="Special">=</span> <span class="PreProc">$clog</span><span class="Special">(</span><span class="Constant">0</span><span class="Special">),</span>
+    <span class="Statement">parameter</span> <span class="Constant">TEST2</span> <span class="Special">=</span> <span class="PreProc">$clog</span><span class="Special">(</span><span class="Constant">1</span><span class="Special">),</span>
+    <span class="Statement">parameter</span> <span class="Constant">TEST3</span> <span class="Special">=</span> <span class="PreProc">$clog</span><span class="Special">(</span><span class="Constant">2</span><span class="Special">)</span>
+<span class="Special">)</span> <span class="Identifier">mymodule</span><span class="Special">(</span>
+    <span class="Statement">input</span>  <span class="Statement">wire</span> a<span class="Special">,</span>
+    <span class="Statement">input</span>  <span class="Statement">wire</span> b<span class="Special">,</span>
+    <span class="PreProc">`ifdef</span> <span class="Constant">MACRO</span>
+    <span class="Statement">input</span>  <span class="Statement">wire</span> c<span class="Special">,</span>
+    <span class="PreProc">`endif</span>
+    <span class="Statement">output</span> <span class="Statement">wire</span> y
 <span class="Special">);</span>
 
 <span class="Statement">endmodule</span>
