fix: enable IRQ/FIQ interrupt mask using cpsr

Author: Tropix126

.gdbinit

@@ -6,6 +6,6 @@ set history remove-duplicates 128
 layout asm
 set print asm-demangle on
 
-add-symbol-file kernel/target/armv7a-none-eabi/debug/kernel
+add-symbol-file target/armv7a-none-eabi/debug/kernel
 
 target remote localhost:1234

packages/kernel/src/main.rs

@@ -59,6 +59,13 @@ pub extern "C" fn _start() -> ! {
         // `vectors` module.
         vectors::set_vbar(core::ptr::addr_of!(VECTORS_START) as u32);
 
+        // Enable IRQ and FIQ interrupts by masking CPSR with the IRQ and FIQ enable bits.
+        core::arch::asm!(
+            "mrs r1, cpsr
+             bic r1, r1, #0b11000000
+             msr cpsr_c, r1"
+            , options(nomem, nostack));
+
         // Register SDK exception handlers for data/prefetch/undefined aborts.
         vectors::register_sdk_exception_handlers();