Parser doesn't understand constraint implication operator ('->') #1064
Description
Author Name: Dave Storrar
Original Redmine Issue: 1064 from https://www.veripool.org
Original Date: 2016-05-29
The following code produces a parsing error:
class testcase;
rand bit [3:0] a, b;
constraint c { (a == 0) -> (b == 1); }
endclass
%Error: testcase.sv:3: syntax error, unexpected '}'
I see a comment in the VParseBison.y that seems to relate to a conflict between the 2009 and 2012 SystemVerilog versions, but I'm not familiar with Bison, so can't work out what should be happening.
Hope you can help.