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Add tileable RR Graph

docsDocumentationDocumentation

lang-cppC/C++ codeC/C++ code

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

libvtrutil

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 3134

#3134 In verilog-to-routing/vtr-verilog-to-routing;

· amin1377 opened on Jun 11, 2025

[Place] Centriod Initial Placement

lang-cppC/C++ codeC/C++ code

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 3018

#3018 In verilog-to-routing/vtr-verilog-to-routing;

· amin1377 opened on May 1, 2025

Merge master to openfpga feature branch

buildBuild systemBuild system

docsDocumentationDocumentation

external_libs

infraProject InfrastructureProject Infrastructure

lang-cppC/C++ codeC/C++ code

lang-makeCMake/Make codeCMake/Make code

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

libvtrutil

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2572

#2572 In verilog-to-routing/vtr-verilog-to-routing;

· Tulong4Dev opened on May 30, 2024

Support route constraint.

buildBuild systemBuild system

external_libs

lang-makeCMake/Make codeCMake/Make code

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

libvtrutil

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2233

#2233 In verilog-to-routing/vtr-verilog-to-routing;

· Tulong4Dev opened on Jan 26, 2023

Add support for falling edge clocking

external_libs

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2211

#2211 In verilog-to-routing/vtr-verilog-to-routing;

· lpawelcz opened on Nov 23, 2022

[WIP] Tileable Routing Resource Graph Builder

buildBuild systemBuild system

docsDocumentationDocumentation

external_libs

infraProject InfrastructureProject Infrastructure

lang-cppC/C++ codeC/C++ code

lang-hdlHardware Description Language (Verilog/VHDL)Hardware Description Language (Verilog/VHDL)

lang-makeCMake/Make codeCMake/Make code

lang-netlist

lang-pythonPython codePython code

lang-shellShell scripts (bash etc.)Shell scripts (bash etc.)

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

liblog

libpugiutil

libvtrutil

OdinOdin II Logic Synthesis Tool: Unsorted itemOdin II Logic Synthesis Tool: Unsorted item

Parmys

scriptsUtility & Infrastructure scriptsUtility & Infrastructure scripts

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2135

#2135 In verilog-to-routing/vtr-verilog-to-routing;

· tangxifan opened on Aug 16, 2022

XDC placement constraints support for interchange

buildBuild systemBuild system

external_libs

infraProject InfrastructureProject Infrastructure

lang-makeCMake/Make codeCMake/Make code

lang-shellShell scripts (bash etc.)Shell scripts (bash etc.)

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

libvtrutil

scriptsUtility & Infrastructure scriptsUtility & Infrastructure scripts

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2021

#2021 In verilog-to-routing/vtr-verilog-to-routing;

· kboronski-ant opened on May 5, 2022

FPGA interchange: add RR graph generation

external_libs

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 1999

#1999 In verilog-to-routing/vtr-verilog-to-routing;

· acomodi opened on Mar 16, 2022

VPR: interchange: add initial support for the interchange netlist frontend

buildBuild systemBuild system

external_libs

infraProject InfrastructureProject Infrastructure

lang-makeCMake/Make codeCMake/Make code

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

libvtrutil

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 1894

#1894 In verilog-to-routing/vtr-verilog-to-routing;

· acomodi opened on Oct 25, 2021

WIP: clang-tidy fixes around const std::string references.

ABCABC Logic Optimization & Technology Mapping ToolABC Logic Optimization & Technology Mapping Tool

external_libs

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

libpugiutil

libvtrutil

OdinOdin II Logic Synthesis Tool: Unsorted itemOdin II Logic Synthesis Tool: Unsorted item

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 1764

#1764 In verilog-to-routing/vtr-verilog-to-routing;

· mithro opened on Jun 3, 2021