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[WIP] Converting Yosys to Submodule

buildBuild systemBuild system

external_libs

lang-cppC/C++ codeC/C++ code

lang-hdlHardware Description Language (Verilog/VHDL)Hardware Description Language (Verilog/VHDL)

lang-makeCMake/Make codeCMake/Make code

lang-perlPerl codePerl code

lang-pythonPython codePython code

lang-shellShell scripts (bash etc.)Shell scripts (bash etc.)

Parmys

Status: Draft (not ready).

verilog-to-routing/vtr-verilog-to-routingnumber 3156

#3156 In verilog-to-routing/vtr-verilog-to-routing;

· loglav03 opened on Jun 20, 2025

[WIP] System Verilog Testing #3

external_libs

infraProject InfrastructureProject Infrastructure

lang-makeCMake/Make codeCMake/Make code

lang-pythonPython codePython code

Status: Draft (not ready).

verilog-to-routing/vtr-verilog-to-routingnumber 3114

#3114 In verilog-to-routing/vtr-verilog-to-routing;

· loglav03 opened on Jun 5, 2025

Bump libs/EXTERNAL/sockpp from <code>599f750</code> to <code>cff72d0</code>

dependenciesPull requests that update a dependency filePull requests that update a dependency file

external_libs

submodulesPull requests that update Submodules codePull requests that update Submodules code

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2957

#2957 In verilog-to-routing/vtr-verilog-to-routing;

· dependabot opened on Apr 1, 2025

[CI] Added System Verilog Regression Tests to GitHub Runners

external_libs

infraProject InfrastructureProject Infrastructure

lang-makeCMake/Make codeCMake/Make code

lang-pythonPython codePython code

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2885

#2885 In verilog-to-routing/vtr-verilog-to-routing;

· AlexandreSinger opened on Feb 7, 2025

[WIP] Router Lookahead Profiler

buildBuild systemBuild system

external_libs

infraProject InfrastructureProject Infrastructure

lang-cppC/C++ codeC/C++ code

lang-makeCMake/Make codeCMake/Make code

lang-pythonPython codePython code

scriptsUtility & Infrastructure scriptsUtility & Infrastructure scripts

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Draft (not ready).

verilog-to-routing/vtr-verilog-to-routingnumber 2683

#2683 In verilog-to-routing/vtr-verilog-to-routing;

· nedsels opened on Aug 12, 2024

Merge master to openfpga feature branch

buildBuild systemBuild system

docsDocumentationDocumentation

external_libs

infraProject InfrastructureProject Infrastructure

lang-cppC/C++ codeC/C++ code

lang-makeCMake/Make codeCMake/Make code

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

libvtrutil

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2572

#2572 In verilog-to-routing/vtr-verilog-to-routing;

· Tulong4Dev opened on May 30, 2024

Adding Number of Logic levels and number of timing graph levels to ti…

external_libs

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2383

#2383 In verilog-to-routing/vtr-verilog-to-routing;

· behnam-rs opened on Aug 31, 2023

Support route constraint.

buildBuild systemBuild system

external_libs

lang-makeCMake/Make codeCMake/Make code

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

libvtrutil

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2233

#2233 In verilog-to-routing/vtr-verilog-to-routing;

· Tulong4Dev opened on Jan 26, 2023

Add support for falling edge clocking

external_libs

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2211

#2211 In verilog-to-routing/vtr-verilog-to-routing;

· lpawelcz opened on Nov 23, 2022

CVE-2007-4559 Patch

external_libs

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2204

#2204 In verilog-to-routing/vtr-verilog-to-routing;

· TrellixVulnTeam opened on Nov 15, 2022

[WIP] Tileable Routing Resource Graph Builder

buildBuild systemBuild system

docsDocumentationDocumentation

external_libs

infraProject InfrastructureProject Infrastructure

lang-cppC/C++ codeC/C++ code

lang-hdlHardware Description Language (Verilog/VHDL)Hardware Description Language (Verilog/VHDL)

lang-makeCMake/Make codeCMake/Make code

lang-netlist

lang-pythonPython codePython code

lang-shellShell scripts (bash etc.)Shell scripts (bash etc.)

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

liblog

libpugiutil

libvtrutil

OdinOdin II Logic Synthesis Tool: Unsorted itemOdin II Logic Synthesis Tool: Unsorted item

Parmys

scriptsUtility & Infrastructure scriptsUtility & Infrastructure scripts

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2135

#2135 In verilog-to-routing/vtr-verilog-to-routing;

· tangxifan opened on Aug 16, 2022

XDC placement constraints support for interchange

buildBuild systemBuild system

external_libs

infraProject InfrastructureProject Infrastructure

lang-makeCMake/Make codeCMake/Make code

lang-shellShell scripts (bash etc.)Shell scripts (bash etc.)

libarchfpgaLibrary for handling FPGA Architecture descriptionsLibrary for handling FPGA Architecture descriptions

libvtrutil

scriptsUtility & Infrastructure scriptsUtility & Infrastructure scripts

VPRVPR FPGA Placement & Routing ToolVPR FPGA Placement & Routing Tool

Status: Open (in progress).

verilog-to-routing/vtr-verilog-to-routingnumber 2021

#2021 In verilog-to-routing/vtr-verilog-to-routing;

· kboronski-ant opened on May 5, 2022