Skip to content

Commit 8aa70b5

Browse files
fixed segfault
1 parent 84dbbe2 commit 8aa70b5

File tree

8 files changed

+36
-34
lines changed

8 files changed

+36
-34
lines changed

libs/libarchfpga/src/arch_util.cpp

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -51,8 +51,7 @@ InstPort::InstPort(const std::string& str) {
5151
instance_ = parse_name_index(inst_port[0]);
5252
port_ = parse_name_index(inst_port[1]);
5353
} else {
54-
std::string msg = vtr::string_fmt("Failed to parse instance port specification '%s'",
55-
str.c_str());
54+
std::string msg = vtr::string_fmt("Failed to parse instance port specification '%s'", str.c_str());
5655
throw ArchFpgaError(msg);
5756
}
5857
}
@@ -534,7 +533,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
534533
lut_pb_type->modes[0].interconnect[0].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 10, sizeof(char));
535534
sprintf(lut_pb_type->modes[0].interconnect[0].name, "complete:%s", lut_pb_type->name);
536535
lut_pb_type->modes[0].interconnect[0].type = COMPLETE_INTERC;
537-
lut_pb_type->modes[0].interconnect[0].input_string = vtr::string_fmt("%s.%s", lut_pb_type->name, in_port->name);
536+
lut_pb_type->modes[0].interconnect[0].input_string = vtr::string_fmt("%s.%s", lut_pb_type->name, in_port->name);
538537
lut_pb_type->modes[0].interconnect[0].output_string = vtr::string_fmt("%s.%s", lut_pb_type->name, out_port->name);
539538

540539
lut_pb_type->modes[0].interconnect[0].parent_mode_index = 0;
@@ -578,7 +577,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
578577
lut_pb_type->modes[1].interconnect[0].name = (char*)vtr::calloc(strlen(lut_pb_type->name) + 10, sizeof(char));
579578
sprintf(lut_pb_type->modes[1].interconnect[0].name, "direct:%s", lut_pb_type->name);
580579
lut_pb_type->modes[1].interconnect[0].type = DIRECT_INTERC;
581-
lut_pb_type->modes[1].interconnect[0].input_string = vtr::string_fmt(lut_pb_type->name, in_port->name);
580+
lut_pb_type->modes[1].interconnect[0].input_string = vtr::string_fmt("%s.%s", lut_pb_type->name, in_port->name);
582581
lut_pb_type->modes[1].interconnect[0].output_string = default_name + '.' + in_port->name;
583582
lut_pb_type->modes[1].interconnect[0].infer_annotations = true;
584583

@@ -686,14 +685,14 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
686685
mem_pb_type->modes[0].pb_type_children[0].ports[i].num_pins = 1;
687686
mem_pb_type->modes[0].pb_type_children[0].num_input_pins -= (mem_pb_type->ports[i].num_pins - 1);
688687

689-
mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s.%s", input_name, input_port_name);
690-
mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s[%d:0].%s", output_name, num_pb - 1, output_port_name);
688+
mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s.%s", input_name.data(), input_port_name);
689+
mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s[%d:0].%s", output_name.data(), num_pb - 1, output_port_name);
691690
} else {
692691
/* force data pins to be one bit wide and update stats */
693692
mem_pb_type->modes[0].pb_type_children[0].ports[i].num_pins = 1;
694693
mem_pb_type->modes[0].pb_type_children[0].num_output_pins -= (mem_pb_type->ports[i].num_pins - 1);
695-
mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s[%d:0].%s", input_name, num_pb - 1, input_port_name);
696-
mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s.%s", output_name, output_port_name);
694+
mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s[%d:0].%s", input_name.data(), num_pb - 1, input_port_name);
695+
mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s.%s", output_name.data(), output_port_name);
697696
}
698697

699698
/* Allocate interconnect power structures */
@@ -710,12 +709,12 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
710709

711710
if (mem_pb_type->ports[i].type == IN_PORT) {
712711
mem_pb_type->modes[0].interconnect[i_inter].type = DIRECT_INTERC;
713-
mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s.%s", input_name, input_port_name);
714-
mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s[%d:%d].%s", output_name, j, j, output_port_name);
712+
mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s.%s", input_name.data(), input_port_name);
713+
mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s[%d:%d].%s", output_name.data(), j, j, output_port_name);
715714
} else {
716715
mem_pb_type->modes[0].interconnect[i_inter].type = DIRECT_INTERC;
717-
mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s[%d:%d].%s", input_name, j, j, input_port_name);
718-
mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s.%s", output_name, output_port_name);
716+
mem_pb_type->modes[0].interconnect[i_inter].input_string = vtr::string_fmt("%s[%d:%d].%s", input_name.data(), j, j, input_port_name);
717+
mem_pb_type->modes[0].interconnect[i_inter].output_string = vtr::string_fmt("%s.%s", output_name.data(), output_port_name);
719718
}
720719

721720
/* Allocate interconnect power structures */

libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -395,8 +395,7 @@ static void process_bend(pugi::xml_node node, t_segment_inf& segment, const int
395395
*
396396
*/
397397

398-
/* Loads the given architecture file. */
399-
void xml_read_arch(const char* arch_file,
398+
void xml_read_arch(std::string_view arch_file,
400399
const bool timing_enabled,
401400
t_arch* arch,
402401
std::vector<t_physical_tile_type>& physical_tile_types,
@@ -408,7 +407,7 @@ void xml_read_arch(const char* arch_file,
408407
arch_file);
409408
}
410409

411-
//Create a unique identifier for this architecture file based on it's contents
410+
// Create a unique identifier for this architecture file based on it's contents
412411
arch->architecture_id = vtr::secure_digest_file(arch_file);
413412

414413
// Parse the file
@@ -418,11 +417,11 @@ void xml_read_arch(const char* arch_file,
418417
t_default_fc_spec arch_def_fc;
419418
pugi::xml_document doc;
420419
pugi::xml_node next;
421-
pugiutil::loc_data loc_data = pugiutil::load_xml(doc, arch_file);
420+
pugiutil::loc_data loc_data = pugiutil::load_xml(doc, arch_file.data());
422421

423-
set_arch_file_name(arch_file);
422+
set_arch_file_name(arch_file.data());
424423

425-
/* Root node should be architecture */
424+
// Root node should be architecture
426425
auto architecture = get_single_child(doc, "architecture", loc_data);
427426

428427
/* TODO: do version processing properly with string delimiting on the . */
@@ -565,7 +564,7 @@ void xml_read_arch(const char* arch_file,
565564

566565
mark_IO_types(physical_tile_types);
567566
} catch (pugiutil::XmlError& e) {
568-
archfpga_throw(arch_file, e.line(), e.what());
567+
archfpga_throw(arch_file.data(), e.line(), e.what());
569568
}
570569
}
571570

libs/libarchfpga/src/read_xml_arch_file.h

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
#pragma once
22

33
#include <vector>
4+
#include <string_view>
5+
46
#include "physical_types.h"
57

68
#ifdef __cplusplus
@@ -11,8 +13,10 @@ extern "C" {
1113
* should use the pointers to these type indices*/
1214
#define EMPTY_TYPE_INDEX 0
1315

14-
/* function declarations */
15-
void xml_read_arch(const char* arch_file,
16+
// function declarations
17+
18+
/// Loads the given architecture file
19+
void xml_read_arch(std::string_view arch_file,
1620
const bool timing_enabled,
1721
t_arch* arch,
1822
std::vector<t_physical_tile_type>& physical_tile_types,

libs/libvtrutil/src/vtr_digest.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,10 +14,10 @@
1414

1515
namespace vtr {
1616

17-
std::string secure_digest_file(const std::string& filepath) {
18-
std::ifstream is(filepath);
17+
std::string secure_digest_file(std::string_view filepath) {
18+
std::ifstream is(filepath.data());
1919
if (!is) {
20-
throw VtrError("Failed to open file", filepath);
20+
throw VtrError("Failed to open file", filepath.data());
2121
}
2222
return secure_digest_stream(is);
2323
}

libs/libvtrutil/src/vtr_digest.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
namespace vtr {
77

88
///@brief Generate a secure hash of the file at filepath
9-
std::string secure_digest_file(const std::string& filepath);
9+
std::string secure_digest_file(std::string_view filepath);
1010

1111
///@brief Generate a secure hash of a stream
1212
std::string secure_digest_stream(std::istream& is);

libs/libvtrutil/src/vtr_util.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ std::string string_fmt(const char* fmt, ...) {
6565
// Initialize variable argument list
6666
va_start(va_args, fmt);
6767

68-
//Format string
68+
// Format string
6969
std::string str = vstring_fmt(fmt, va_args);
7070

7171
// Reset variable argument list

vpr/src/pack/pb_type_graph.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -967,13 +967,13 @@ t_pb_graph_pin*** alloc_and_load_port_pin_ptrs_from_string(const int line_num,
967967
if (tokens[i].type == e_token_type::OPEN_SQUIG_BRACKET) {
968968
if (in_squig_bracket) {
969969
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num,
970-
"{ inside { in port %s\n", port_string);
970+
"{ inside { in port %s\n", port_string.data());
971971
}
972972
in_squig_bracket = true;
973973
} else if (tokens[i].type == e_token_type::CLOSE_SQUIG_BRACKET) {
974974
if (!in_squig_bracket) {
975975
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num,
976-
"No matching '{' for '}' in port %s\n", port_string);
976+
"No matching '{' for '}' in port %s\n", port_string.data());
977977
}
978978
(*num_sets)++;
979979
in_squig_bracket = false;
@@ -987,7 +987,7 @@ t_pb_graph_pin*** alloc_and_load_port_pin_ptrs_from_string(const int line_num,
987987
if (in_squig_bracket) {
988988
(*num_sets)++;
989989
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num,
990-
"No matching '{' for '}' in port %s\n", port_string);
990+
"No matching '{' for '}' in port %s\n", port_string.data());
991991
}
992992

993993
t_pb_graph_pin*** pb_graph_pins = new t_pb_graph_pin**[*num_sets];
@@ -1003,17 +1003,17 @@ t_pb_graph_pin*** alloc_and_load_port_pin_ptrs_from_string(const int line_num,
10031003
if (tokens[i].type == e_token_type::OPEN_SQUIG_BRACKET) {
10041004
if (in_squig_bracket) {
10051005
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num,
1006-
"{ inside { in port %s\n", port_string);
1006+
"{ inside { in port %s\n", port_string.data());
10071007
}
10081008
in_squig_bracket = true;
10091009
} else if (tokens[i].type == e_token_type::CLOSE_SQUIG_BRACKET) {
10101010
if ((*num_ptrs)[curr_set] == 0) {
10111011
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num,
1012-
"No data contained in {} in port %s\n", port_string);
1012+
"No data contained in {} in port %s\n", port_string.data());
10131013
}
10141014
if (!in_squig_bracket) {
10151015
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num,
1016-
"No matching '{' for '}' in port %s\n", port_string);
1016+
"No matching '{' for '}' in port %s\n", port_string.data());
10171017
}
10181018
curr_set++;
10191019
in_squig_bracket = false;
@@ -1026,7 +1026,7 @@ t_pb_graph_pin*** alloc_and_load_port_pin_ptrs_from_string(const int line_num,
10261026
&((*num_ptrs)[curr_set]), &pb_graph_pins[curr_set]);
10271027
} catch (VprError& e) {
10281028
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num,
1029-
"Syntax error processing port string '%s' (%s)\n", port_string, e.what());
1029+
"Syntax error processing port string '%s' (%s)\n", port_string.data(), e.what());
10301030
}
10311031
VTR_ASSERT(success);
10321032

vpr/src/pack/pb_type_graph_annotations.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -568,7 +568,7 @@ static t_pb_graph_pin* find_clock_pin(t_pb_graph_node* gnode, std::string_view c
568568
}
569569
}
570570

571-
if (clock_pin != nullptr) {
571+
if (clock_pin == nullptr) {
572572
vpr_throw(VPR_ERROR_ARCH, get_arch_file_name(), line_num,
573573
"Failed to find associated clock pin");
574574
}

0 commit comments

Comments
 (0)