@@ -51,8 +51,7 @@ InstPort::InstPort(const std::string& str) {
5151 instance_ = parse_name_index (inst_port[0 ]);
5252 port_ = parse_name_index (inst_port[1 ]);
5353 } else {
54- std::string msg = vtr::string_fmt (" Failed to parse instance port specification '%s'" ,
55- str.c_str ());
54+ std::string msg = vtr::string_fmt (" Failed to parse instance port specification '%s'" , str.c_str ());
5655 throw ArchFpgaError (msg);
5756 }
5857}
@@ -534,7 +533,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
534533 lut_pb_type->modes [0 ].interconnect [0 ].name = (char *)vtr::calloc (strlen (lut_pb_type->name ) + 10 , sizeof (char ));
535534 sprintf (lut_pb_type->modes [0 ].interconnect [0 ].name , " complete:%s" , lut_pb_type->name );
536535 lut_pb_type->modes [0 ].interconnect [0 ].type = COMPLETE_INTERC;
537- lut_pb_type->modes [0 ].interconnect [0 ].input_string = vtr::string_fmt (" %s.%s" , lut_pb_type->name , in_port->name );
536+ lut_pb_type->modes [0 ].interconnect [0 ].input_string = vtr::string_fmt (" %s.%s" , lut_pb_type->name , in_port->name );
538537 lut_pb_type->modes [0 ].interconnect [0 ].output_string = vtr::string_fmt (" %s.%s" , lut_pb_type->name , out_port->name );
539538
540539 lut_pb_type->modes [0 ].interconnect [0 ].parent_mode_index = 0 ;
@@ -578,7 +577,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
578577 lut_pb_type->modes [1 ].interconnect [0 ].name = (char *)vtr::calloc (strlen (lut_pb_type->name ) + 10 , sizeof (char ));
579578 sprintf (lut_pb_type->modes [1 ].interconnect [0 ].name , " direct:%s" , lut_pb_type->name );
580579 lut_pb_type->modes [1 ].interconnect [0 ].type = DIRECT_INTERC;
581- lut_pb_type->modes [1 ].interconnect [0 ].input_string = vtr::string_fmt (lut_pb_type->name , in_port->name );
580+ lut_pb_type->modes [1 ].interconnect [0 ].input_string = vtr::string_fmt (" %s.%s " , lut_pb_type->name , in_port->name );
582581 lut_pb_type->modes [1 ].interconnect [0 ].output_string = default_name + ' .' + in_port->name ;
583582 lut_pb_type->modes [1 ].interconnect [0 ].infer_annotations = true ;
584583
@@ -686,14 +685,14 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
686685 mem_pb_type->modes [0 ].pb_type_children [0 ].ports [i].num_pins = 1 ;
687686 mem_pb_type->modes [0 ].pb_type_children [0 ].num_input_pins -= (mem_pb_type->ports [i].num_pins - 1 );
688687
689- mem_pb_type->modes [0 ].interconnect [i_inter].input_string = vtr::string_fmt (" %s.%s" , input_name, input_port_name);
690- mem_pb_type->modes [0 ].interconnect [i_inter].output_string = vtr::string_fmt (" %s[%d:0].%s" , output_name, num_pb - 1 , output_port_name);
688+ mem_pb_type->modes [0 ].interconnect [i_inter].input_string = vtr::string_fmt (" %s.%s" , input_name. data () , input_port_name);
689+ mem_pb_type->modes [0 ].interconnect [i_inter].output_string = vtr::string_fmt (" %s[%d:0].%s" , output_name. data () , num_pb - 1 , output_port_name);
691690 } else {
692691 /* force data pins to be one bit wide and update stats */
693692 mem_pb_type->modes [0 ].pb_type_children [0 ].ports [i].num_pins = 1 ;
694693 mem_pb_type->modes [0 ].pb_type_children [0 ].num_output_pins -= (mem_pb_type->ports [i].num_pins - 1 );
695- mem_pb_type->modes [0 ].interconnect [i_inter].input_string = vtr::string_fmt (" %s[%d:0].%s" , input_name, num_pb - 1 , input_port_name);
696- mem_pb_type->modes [0 ].interconnect [i_inter].output_string = vtr::string_fmt (" %s.%s" , output_name, output_port_name);
694+ mem_pb_type->modes [0 ].interconnect [i_inter].input_string = vtr::string_fmt (" %s[%d:0].%s" , input_name. data () , num_pb - 1 , input_port_name);
695+ mem_pb_type->modes [0 ].interconnect [i_inter].output_string = vtr::string_fmt (" %s.%s" , output_name. data () , output_port_name);
697696 }
698697
699698 /* Allocate interconnect power structures */
@@ -710,12 +709,12 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
710709
711710 if (mem_pb_type->ports [i].type == IN_PORT) {
712711 mem_pb_type->modes [0 ].interconnect [i_inter].type = DIRECT_INTERC;
713- mem_pb_type->modes [0 ].interconnect [i_inter].input_string = vtr::string_fmt (" %s.%s" , input_name, input_port_name);
714- mem_pb_type->modes [0 ].interconnect [i_inter].output_string = vtr::string_fmt (" %s[%d:%d].%s" , output_name, j, j, output_port_name);
712+ mem_pb_type->modes [0 ].interconnect [i_inter].input_string = vtr::string_fmt (" %s.%s" , input_name. data () , input_port_name);
713+ mem_pb_type->modes [0 ].interconnect [i_inter].output_string = vtr::string_fmt (" %s[%d:%d].%s" , output_name. data () , j, j, output_port_name);
715714 } else {
716715 mem_pb_type->modes [0 ].interconnect [i_inter].type = DIRECT_INTERC;
717- mem_pb_type->modes [0 ].interconnect [i_inter].input_string = vtr::string_fmt (" %s[%d:%d].%s" , input_name, j, j, input_port_name);
718- mem_pb_type->modes [0 ].interconnect [i_inter].output_string = vtr::string_fmt (" %s.%s" , output_name, output_port_name);
716+ mem_pb_type->modes [0 ].interconnect [i_inter].input_string = vtr::string_fmt (" %s[%d:%d].%s" , input_name. data () , j, j, input_port_name);
717+ mem_pb_type->modes [0 ].interconnect [i_inter].output_string = vtr::string_fmt (" %s.%s" , output_name. data () , output_port_name);
719718 }
720719
721720 /* Allocate interconnect power structures */
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