formatting fixes

Signed-off-by: Pawel Czarnecki <[email protected]>

Author: lpawelcz

libs/libarchfpga/src/arch_util.cpp

@@ -171,7 +171,7 @@ void free_arch(t_arch* arch) {
 
     delete arch->architecture_id;
 
-	//Free internal model library
+    //Free internal model library
     if (arch->model_library) {
         for (int i = 0; i < num_models_lib; ++i) {
             vtr::t_linked_vptr* vptr = arch->model_library[i].pb_types;
@@ -183,7 +183,7 @@ void free_arch(t_arch* arch) {
         }
 
         //Each model has different number of inputs/outputs - delete each model separately
-		//Free INPAD
+        //Free INPAD
         delete arch->model_library[LIB_INPUT].name;
         delete arch->model_library[LIB_INPUT].outputs->name;
         delete[] arch->model_library[LIB_INPUT].outputs;
@@ -216,7 +216,7 @@ void free_arch(t_arch* arch) {
         delete arch->model_library[LIB_NAMES].outputs->name;
         delete[] arch->model_library[LIB_NAMES].outputs;
 
-		//Free the library array
+        //Free the library array
         delete[] arch->model_library;
     }
 
@@ -687,7 +687,7 @@ void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
     for (i = 0; i < copy->num_annotations; i++) {
         copy->annotations[i].clock = vtr::strdup(pb_type->annotations[i].clock);
         dot = strstr(pb_type->annotations[i].input_pins, ".");
-        copy->annotations[i].input_pins =  new char[strlen(new_name) + strlen(dot) + 1];
+        copy->annotations[i].input_pins = new char[strlen(new_name) + strlen(dot) + 1];
         copy->annotations[i].input_pins[0] = '\0';
         strcat(copy->annotations[i].input_pins, new_name);
         strcat(copy->annotations[i].input_pins, dot);
@@ -852,7 +852,7 @@ void ProcessLutClass(t_pb_type* lut_pb_type) {
     sprintf(lut_pb_type->modes[1].interconnect[1].input_string, "%s.%s",
             default_name, out_port->name);
     lut_pb_type->modes[1].interconnect[1].output_string = new char[strlen(lut_pb_type->name) + strlen(out_port->name)
-                                                                                 + strlen(in_port->name) + 2];
+                                                                   + strlen(in_port->name) + 2];
     sprintf(lut_pb_type->modes[1].interconnect[1].output_string, "%s.%s",
             lut_pb_type->name, out_port->name);
     lut_pb_type->modes[1].interconnect[1].infer_annotations = true;
@@ -955,7 +955,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
                 sprintf(mem_pb_type->modes[0].interconnect[i_inter].input_string,
                         "%s.%s", input_name, input_port_name);
                 mem_pb_type->modes[0].interconnect[i_inter].output_string = new char[strlen(output_name) + strlen(output_port_name)
-                                                                                                   + 2 * (6 + num_pb / 10)];
+                                                                                     + 2 * (6 + num_pb / 10)];
                 sprintf(mem_pb_type->modes[0].interconnect[i_inter].output_string,
                         "%s[%d:0].%s", output_name, num_pb - 1,
                         output_port_name);
@@ -965,11 +965,11 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
                 mem_pb_type->modes[0].pb_type_children[0].num_output_pins -= (mem_pb_type->ports[i].num_pins - 1);
 
                 mem_pb_type->modes[0].interconnect[i_inter].input_string = new char[strlen(input_name) + strlen(input_port_name)
-                                                                                                  + 2 * (6 + num_pb / 10)];
+                                                                                    + 2 * (6 + num_pb / 10)];
                 sprintf(mem_pb_type->modes[0].interconnect[i_inter].input_string,
                         "%s[%d:0].%s", input_name, num_pb - 1, input_port_name);
                 mem_pb_type->modes[0].interconnect[i_inter].output_string = new char[strlen(output_name) + strlen(output_port_name)
-                                                                                                   + 2];
+                                                                                     + 2];
                 sprintf(mem_pb_type->modes[0].interconnect[i_inter].output_string,
                         "%s.%s", output_name, output_port_name);
             }
@@ -997,7 +997,7 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
                 } else {
                     mem_pb_type->modes[0].interconnect[i_inter].type = DIRECT_INTERC;
                     mem_pb_type->modes[0].interconnect[i_inter].input_string = new char[strlen(input_name) + strlen(input_port_name)
-                                                                                                           + 2 * (6 + num_pb / 10)];
+                                                                                        + 2 * (6 + num_pb / 10)];
                     sprintf(mem_pb_type->modes[0].interconnect[i_inter].input_string,
                             "%s[%d:%d].%s", input_name, j, j, input_port_name);
                     mem_pb_type->modes[0].interconnect[i_inter].output_string = new char[strlen(output_name) + strlen(output_port_name) + 2];
@@ -1111,25 +1111,25 @@ void CreateModelLibrary(t_arch* arch) {
     model_library[LIB_LATCH_RE].outputs[0].clock = "clk";
     model_library[LIB_LATCH_RE].outputs[0].trigg_edge = TriggeringEdge::RISING_EDGE;
 
-	/*
-	 * Duplicate LATCH model.
-	 * Second separate model is required for falling edge support.
-	 * It is a copy of LIB_LATCH_RE but with different trigg_edge configuration
-	 * for inputs/outputs t_model_ports. It is used to represent FFs triggered at
-	 * the falling edge of the clock, while LIB_LATCH_RE represents FFs triggered
-	 * at the rising edge.
-	 *
-	 * VPR uses single model of each blif primitive type (e.g. '.latch', '.names') parsed from input blif file.
-	 * That means models are used as configuration reference for parsed blif primitives when
-	 * Latch instances are created in circuit evaluation, meaning:
-	 *   1 unique blif primitive configuration (parsed from blif file) maps to
-	 *   1 unique model (defined here, in VPR internal library) which represents configuration of
-	 *   multiple primitive instances (of given type and configuration) used in the circuit
-	 *
-	 * Models have to be duplicated because otherwise VPR will use the configuration
-	 * of the last parsed '.latch' for each FF in the design
-	 *
-	 */
+    /*
+     * Duplicate LATCH model.
+     * Second separate model is required for falling edge support.
+     * It is a copy of LIB_LATCH_RE but with different trigg_edge configuration
+     * for inputs/outputs t_model_ports. It is used to represent FFs triggered at
+     * the falling edge of the clock, while LIB_LATCH_RE represents FFs triggered
+     * at the rising edge.
+     *
+     * VPR uses single model of each blif primitive type (e.g. '.latch', '.names') parsed from input blif file.
+     * That means models are used as configuration reference for parsed blif primitives when
+     * Latch instances are created in circuit evaluation, meaning:
+     *   1 unique blif primitive configuration (parsed from blif file) maps to
+     *   1 unique model (defined here, in VPR internal library) which represents configuration of
+     *   multiple primitive instances (of given type and configuration) used in the circuit
+     *
+     * Models have to be duplicated because otherwise VPR will use the configuration
+     * of the last parsed '.latch' for each FF in the design
+     *
+     */
     //LATCH triggered at FALLING EDGE
     model_library[LIB_LATCH_FE].name = vtr::strdup(MODEL_LATCH);
     model_library[LIB_LATCH_FE].index = LIB_LATCH_FE;

libs/libarchfpga/src/arch_util.h

@@ -20,11 +20,11 @@ constexpr const int num_models_lib = 5;
 constexpr const int LATCH_CLOCK_INPUT_ID = 1;
 
 enum InternalModel {
-	LIB_INPUT,
-	LIB_OUTPUT,
-	LIB_LATCH_RE,
-	LIB_LATCH_FE,
-	LIB_NAMES
+    LIB_INPUT,
+    LIB_OUTPUT,
+    LIB_LATCH_RE,
+    LIB_LATCH_FE,
+    LIB_NAMES
 };
 
 class InstPort {

vpr/src/base/atom_netlist_utils.cpp

@@ -196,7 +196,7 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) {
                     type = "fe";
                 } else {
                     //Otherwise always assume rising edge (.latch could be also configured as:
-					//'active high', 'active low', 'asynchronous')
+                    //'active high', 'active low', 'asynchronous')
                     type = "re";
                 }
             }

vpr/src/timing/read_sdc.cpp

@@ -741,9 +741,7 @@ class SdcParseCallback : public sdcparse::Callback {
 
             constraint = launch_clock.period;
 
-        } else if ((std::fabs(launch_clock.period - capture_clock.period) < EPSILON) &&
-				   (std::fabs((launch_clock.period / 2) - std::fabs(launch_clock.rise_edge - capture_clock.rise_edge)) < EPSILON) &&
-				   (std::fabs((launch_clock.period / 2) - std::fabs(launch_clock.fall_edge - capture_clock.fall_edge)) < EPSILON)) {
+        } else if ((std::fabs(launch_clock.period - capture_clock.period) < EPSILON) && (std::fabs((launch_clock.period / 2) - std::fabs(launch_clock.rise_edge - capture_clock.rise_edge)) < EPSILON) && (std::fabs((launch_clock.period / 2) - std::fabs(launch_clock.fall_edge - capture_clock.fall_edge)) < EPSILON)) {
             //The source and sink domains have the same period but are inverted, the constraint is half of the common clock period.
 
             constraint = (launch_clock.period / 2);

vpr/src/util/vpr_utils.cpp

@@ -918,8 +918,8 @@ bool primitive_type_feasible(const AtomBlockId blk_id, t_pb_graph_node* curr_pb_
     if (cur_pb_type->model != atom_ctx.nlist.block_model(blk_id)) {
         //Check if the AtomBlock is related to FF (LATCH model)
         if ((strcmp(atom_ctx.nlist.block_model(blk_id)->name, MODEL_LATCH) == 0) && (strcmp(atom_ctx.nlist.block_model(blk_id)->name, cur_pb_type->model->name) == 0)) {
-             //Special case for .latch: this model exists in 2 variations which are
-             //defined one after another in linked list, check if the second variant match
+            //Special case for .latch: this model exists in 2 variations which are
+            //defined one after another in linked list, check if the second variant match
             if (cur_pb_type->model->next == atom_ctx.nlist.block_model(blk_id) && atom_ctx.nlist.block_model(blk_id)->inputs[LATCH_CLOCK_INPUT_ID].trigg_edge == TriggeringEdge::FALLING_EDGE) {
                 // Next primitive matched AtomBlock
                 // VPR will need data in secondary pin structs in curr_pb_graph_node