Fix parse configs for xilinx architecture

Author: AmirhosseinPoolad

vtr_flow/parse/pass_requirements/pass_requirements_vpr_xilinx_fixed_width.txt

@@ -8,8 +8,8 @@ routed_wirelength;RangeAbs(0.50,1.50,5)
 #Area metrics
 logic_block_area_total;Range(0.5,1.6)
 logic_block_area_used;Range(0.5,1.6)
-min_chan_width_routing_area_total;Range(0.5,1.6)
-min_chan_width_routing_area_per_tile;Range(0.5,1.6)
+routing_area_total;Range(0.5,1.6)
+routing_area_per_tile;Range(0.5,1.6)
 
 #Run-time metrics
 crit_path_route_time;RangeAbs(0.10,10.0,2)

vtr_flow/parse/qor_config/qor_vpr_xilinx.txt

@@ -1,12 +1,15 @@
 vpr_status;output.txt;vpr_status=(.*)
-total_wirelength;vpr.out;\s*Total wirelength: (\d+)
-#total_wirelength_(mcw);vpr.out;Total wirelength:\s*(\d+)
-#total_wirelength_(1.3mcw);vpr.crit_path.out;Total wirelength:\s*(\d+)
+
 total_runtime;vpr.out;The entire flow of VPR took (.*) seconds
-#pack_time;vpr.out;Packing took (.*) seconds
-#place_time;vpr.out;Placement took (.*) seconds
-#route_time;vpr.out;Routing took (.*) seconds
-#num_pre_packed_nets;vpr.out;Total Nets: (\d+)
-#num_post_packed_nets;vpr.out;Netlist num_nets:\s*(\d+)
-crit_path_delay;vpr.crit_path.out;Final critical path: (.*) ns
+pack_time;vpr.out;\s*Packing took (.*) seconds
+place_time;vpr.out;\s*Placement took (.*) seconds
+route_time;vpr.out;\s*Routing took (.*) seconds .*
+
+num_pre_packed_nets;vpr.out;Total Nets: (\d+)
+num_post_packed_nets;vpr.out;Netlist num_nets:\s*(\d+)
 
+num_pre_packed_blocks;vpr.out;\s+Blocks\s*:\s*(\d+)
+num_post_packed_blocks;vpr.out;Netlist num_blocks:\s*(\d+)
+
+total_wirelength;vpr.out;\s*Total wirelength: (\d+)
+critical_path_delay;vpr.out;Final critical path delay \(least slack\): (.*) ns