diff --git a/.cproject b/.cproject
new file mode 100644
index 0000000..af3a16b
--- /dev/null
+++ b/.cproject
@@ -0,0 +1,209 @@
+
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diff --git a/.project b/.project
new file mode 100644
index 0000000..829aacc
--- /dev/null
+++ b/.project
@@ -0,0 +1,26 @@
+
+
+ cm3_1602_lcd
+
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ org.eclipse.cdt.core.cnature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml
new file mode 100644
index 0000000..badce69
--- /dev/null
+++ b/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/CORE/core_cm3.c b/CORE/core_cm3.c
new file mode 100644
index 0000000..67dd85b
--- /dev/null
+++ b/CORE/core_cm3.c
@@ -0,0 +1,784 @@
+/**************************************************************************//**
+ * @file core_cm3.c
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version V1.30
+ * @date 30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+ mrs r0, psp
+ bx lr
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+ msr psp, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+ mrs r0, msp
+ bx lr
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+ msr msp, r0
+ bx lr
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+ clrex
+}
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t __get_BASEPRI(void)
+{
+ mrs r0, basepri
+ bx lr
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+ msr basepri, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+ mrs r0, primask
+ bx lr
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+ msr primask, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t __get_FAULTMASK(void)
+{
+ mrs r0, faultmask
+ bx lr
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+ msr faultmask, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+ mrs r0, control
+ bx lr
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+ msr control, r0
+ bx lr
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+ __ASM("mrs r0, psp");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM("msr psp, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+ __ASM("mrs r0, msp");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM("msr msp, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+ __ASM("rev16 r0, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+ __ASM("rbit r0, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive (8 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+ __ASM("ldrexb r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive (16 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+ __ASM("ldrexh r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive (32 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+ __ASM("ldrex r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive (8 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+ __ASM("strexb r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive (16 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+ __ASM("strexh r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive (32 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+ __ASM("strex r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void) __attribute__( ( naked ) );
+uint32_t __get_PSP(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, psp\n\t"
+ "MOV r0, %0 \n\t"
+ "BX lr \n\t" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
+void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n\t"
+ "BX lr \n\t" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void) __attribute__( ( naked ) );
+uint32_t __get_MSP(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, msp\n\t"
+ "MOV r0, %0 \n\t"
+ "BX lr \n\t" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
+void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n\t"
+ "BX lr \n\t" : : "r" (topOfMainStack) );
+}
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+uint32_t __get_PRIMASK(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+/**
+ * @brief Return the Control Register value
+*
+* @return Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive (8 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+ uint8_t result=0;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive (16 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+ uint16_t result=0;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive (32 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive (8 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive (16 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive (32 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
diff --git a/CORE/core_cm3.h b/CORE/core_cm3.h
new file mode 100644
index 0000000..7ab7b4b
--- /dev/null
+++ b/CORE/core_cm3.h
@@ -0,0 +1,1818 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V1.30
+ * @date 30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CM3_CORE_H__
+#define __CM3_CORE_H__
+
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
+ *
+ * List of Lint messages which will be suppressed and not shown:
+ * - Error 10: \n
+ * register uint32_t __regBasePri __asm("basepri"); \n
+ * Error 10: Expecting ';'
+ * .
+ * - Error 530: \n
+ * return(__regBasePri); \n
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized
+ * .
+ * - Error 550: \n
+ * __regBasePri = (basePri & 0x1ff); \n
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed
+ * .
+ * - Error 754: \n
+ * uint32_t RESERVED0[24]; \n
+ * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced
+ * .
+ * - Error 750: \n
+ * #define __CM3_CORE_H__ \n
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
+ * .
+ * - Error 528: \n
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
+ * .
+ * - Error 751: \n
+ * } InterruptType_Type; \n
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
+ * .
+ * Note: To re-enable a Message, insert a space before 'lint' *
+ *
+ */
+
+/*lint -save */
+/*lint -e10 */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
+ This file defines all structures and symbols for CMSIS core:
+ - CMSIS version number
+ - Cortex-M core registers and bitfields
+ - Cortex-M core peripheral base address
+ @{
+ */
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+#include /* Include standard types */
+
+#if defined (__ICCARM__)
+ #include /* IAR Intrinsics */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
+#endif
+
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#ifdef __cplusplus
+ #define __I volatile /*!< defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ ******************************************************************************/
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
+ @{
+*/
+
+
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
+ memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
+ @{
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
+} NVIC_Type;
+/*@}*/ /* end of group CMSIS_CM3_NVIC */
+
+
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
+ memory mapped structure for System Control Block (SCB)
+ @{
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+/*@}*/ /* end of group CMSIS_CM3_SCB */
+
+
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
+ memory mapped structure for SysTick
+ @{
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+/*@}*/ /* end of group CMSIS_CM3_SysTick */
+
+
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
+ memory mapped structure for Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
+ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
+ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+/*@}*/ /* end of group CMSIS_CM3_ITM */
+
+
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
+ memory mapped structure for Interrupt Type
+ @{
+ */
+typedef struct
+{
+ uint32_t RESERVED0;
+ __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
+#else
+ uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
+#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
+
+#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+
+#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
+ memory mapped structure for Memory Protection Unit (MPU)
+ @{
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
+#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
+#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
+#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
+#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
+#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
+#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@}*/ /* end of group CMSIS_CM3_MPU */
+#endif
+
+
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
+ memory mapped structure for Core Debug Register
+ @{
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
+
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
+
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#endif
+
+/*@}*/ /* end of group CMSIS_CM3_core_register */
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+#define __NOP __nop
+#define __WFI __wfi
+#define __WFE __wfe
+#define __SEV __sev
+#define __ISB() __isb(0)
+#define __DSB() __dsb(0)
+#define __DMB() __dmb(0)
+#define __REV __rev
+#define __RBIT __rbit
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
+#define __STREXB(value, ptr) __strex(value, ptr)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+extern void __CLREX(void);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+#else /* (__ARMCC_VERSION >= 400000) */
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+#define __CLREX __clrex
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+static __INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & 1);
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
+
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
+
+#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
+static __INLINE void __WFI() { __ASM ("wfi"); }
+static __INLINE void __WFE() { __ASM ("wfe"); }
+static __INLINE void __SEV() { __ASM ("sev"); }
+static __INLINE void __CLREX() { __ASM ("clrex"); }
+
+/* intrinsic void __ISB(void) */
+/* intrinsic void __DSB(void) */
+/* intrinsic void __DMB(void) */
+/* intrinsic void __set_PRIMASK(); */
+/* intrinsic void __get_PRIMASK(); */
+/* intrinsic void __set_FAULTMASK(); */
+/* intrinsic void __get_FAULTMASK(); */
+/* intrinsic uint32_t __REV(uint32_t value); */
+/* intrinsic uint32_t __REVSH(uint32_t value); */
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
+/* intrinsic unsigned long __LDREX(unsigned long *); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive (8 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive (16 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive (32 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive (8 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive (16 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive (32 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
+static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
+
+static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
+static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
+
+static __INLINE void __NOP() { __ASM volatile ("nop"); }
+static __INLINE void __WFI() { __ASM volatile ("wfi"); }
+static __INLINE void __WFE() { __ASM volatile ("wfe"); }
+static __INLINE void __SEV() { __ASM volatile ("sev"); }
+static __INLINE void __ISB() { __ASM volatile ("isb"); }
+static __INLINE void __DSB() { __ASM volatile ("dsb"); }
+static __INLINE void __DMB() { __ASM volatile ("dmb"); }
+static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param topOfProcStack Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param topOfMainStack Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param basePri BasePriority
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param priMask PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param faultMask faultMask value
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+*
+* @return Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param control Control value
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in integer value
+ */
+extern uint32_t __REV(uint32_t value);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param value value to reverse
+ * @return reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive (8 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive (16 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive (32 bit)
+ *
+ * @param *addr address pointer
+ * @return value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive (8 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive (16 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive (32 bit)
+ *
+ * @param value value to store
+ * @param *addr address pointer
+ * @return successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
+ Core Function Interface containing:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Reset Functions
+*/
+/*@{*/
+
+/* ########################## NVIC functions #################################### */
+
+/**
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller
+ *
+ * @param PriorityGroup is priority grouping field
+ *
+ * Set the priority grouping field using the required unlock sequence.
+ * The parameter priority_grouping is assigned to the field
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+/**
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller
+ *
+ * @return priority grouping field
+ *
+ * Get the priority grouping from NVIC Interrupt Controller.
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+/**
+ * @brief Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param IRQn The positive number of the external interrupt to enable
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+/**
+ * @brief Disable the interrupt line for external interrupt specified
+ *
+ * @param IRQn The positive number of the external interrupt to disable
+ *
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+/**
+ * @brief Read the interrupt pending bit for a device specific interrupt source
+ *
+ * @param IRQn The number of the device specifc interrupt
+ * @return 1 = interrupt pending, 0 = interrupt not pending
+ *
+ * Read the pending register in NVIC and return 1 if its status is pending,
+ * otherwise it returns 0
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+/**
+ * @brief Set the pending bit for an external interrupt
+ *
+ * @param IRQn The number of the interrupt for set pending
+ *
+ * Set the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+/**
+ * @brief Clear the pending bit for an external interrupt
+ *
+ * @param IRQn The number of the interrupt for clear pending
+ *
+ * Clear the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+/**
+ * @brief Read the active bit for an external interrupt
+ *
+ * @param IRQn The number of the interrupt for read active bit
+ * @return 1 = interrupt active, 0 = interrupt not active
+ *
+ * Read the active register in NVIC and returns 1 if its status is active,
+ * otherwise it returns 0.
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+/**
+ * @brief Set the priority for an interrupt
+ *
+ * @param IRQn The number of the interrupt for set priority
+ * @param priority The priority to set
+ *
+ * Set the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+/**
+ * @brief Read the priority for an interrupt
+ *
+ * @param IRQn The number of the interrupt for get priority
+ * @return The priority for the interrupt
+ *
+ * Read the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * The returned priority value is automatically aligned to the implemented
+ * priority bits of the microcontroller.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/**
+ * @brief Encode the priority for an interrupt
+ *
+ * @param PriorityGroup The used priority group
+ * @param PreemptPriority The preemptive priority value (starting from 0)
+ * @param SubPriority The sub priority value (starting from 0)
+ * @return The encoded priority for the interrupt
+ *
+ * Encode the priority for an interrupt with the given priority group,
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The returned priority value can be used for NVIC_SetPriority(...) function
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/**
+ * @brief Decode the priority of an interrupt
+ *
+ * @param Priority The priority for the interrupt
+ * @param PriorityGroup The used priority group
+ * @param pPreemptPriority The preemptive priority value (starting from 0)
+ * @param pSubPriority The sub priority value (starting from 0)
+ *
+ * Decode an interrupt priority value with the given priority group to
+ * preemptive priority value and sub priority value.
+ * In case of a conflict between priority grouping and available
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ *
+ * The priority value can be retrieved with NVIC_GetPriority(...) function
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+
+/* ################################## SysTick function ############################################ */
+
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
+
+/**
+ * @brief Initialize and start the SysTick counter and its interrupt.
+ *
+ * @param ticks number of ticks between two interrupts
+ * @return 1 = failed, 0 = successful
+ *
+ * Initialise the system tick timer and its interrupt and start the
+ * system tick timer / counter in free running mode to generate
+ * periodical interrupts.
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+
+
+
+/* ################################## Reset function ############################################ */
+
+/**
+ * @brief Initiate a system reset request.
+ *
+ * Initiate a system reset request to reset the MCU
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
+ Core Debug Interface containing:
+ - Core Debug Receive / Transmit Functions
+ - Core Debug Defines
+ - Core Debug Variables
+*/
+/*@{*/
+
+extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/**
+ * @brief Outputs a character via the ITM channel 0
+ *
+ * @param ch character to output
+ * @return character to output
+ *
+ * The function outputs a character via the ITM channel 0.
+ * The function returns when no debugger is connected that has booked the output.
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/**
+ * @brief Inputs a character via variable ITM_RxBuffer
+ *
+ * @return received character, -1 = no character received
+ *
+ * The function inputs a character via variable ITM_RxBuffer.
+ * The function returns when no debugger is connected that has booked the output.
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ */
+static __INLINE int ITM_ReceiveChar (void) {
+ int ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ * @brief Check if a character via variable ITM_RxBuffer is available
+ *
+ * @return 1 = character available, 0 = no character available
+ *
+ * The function checks variable ITM_RxBuffer whether a character is available or not.
+ * The function returns '1' if a character is available and '0' if no character is available.
+ */
+static __INLINE int ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */
+
+#endif /* __CM3_CORE_H__ */
+
+/*lint -restore */
diff --git a/CORE/core_cmFunc.h b/CORE/core_cmFunc.h
new file mode 100644
index 0000000..de1ce67
--- /dev/null
+++ b/CORE/core_cmFunc.h
@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V3.20
+ * @date 25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009-2017 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief Get IPSR Register
+
+ This function returns the content of the IPSR Register.
+
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/CORE/core_cmInstr.h b/CORE/core_cmInstr.h
new file mode 100644
index 0000000..d9afd55
--- /dev/null
+++ b/CORE/core_cmInstr.h
@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V3.20
+ * @date 05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009-2017 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/** \brief Rotate Right in unsigned value (32 bit)
+
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief Breakpoint
+
+ This function causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/Debug/CORE/core_cm3.d b/Debug/CORE/core_cm3.d
new file mode 100644
index 0000000..050e5d6
--- /dev/null
+++ b/Debug/CORE/core_cm3.d
@@ -0,0 +1 @@
+CORE/core_cm3.o: ../CORE/core_cm3.c
diff --git a/Debug/CORE/core_cm3.o b/Debug/CORE/core_cm3.o
new file mode 100644
index 0000000..c953099
Binary files /dev/null and b/Debug/CORE/core_cm3.o differ
diff --git a/Debug/CORE/subdir.mk b/Debug/CORE/subdir.mk
new file mode 100644
index 0000000..49e02c5
--- /dev/null
+++ b/Debug/CORE/subdir.mk
@@ -0,0 +1,24 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../CORE/core_cm3.c
+
+OBJS += \
+./CORE/core_cm3.o
+
+C_DEPS += \
+./CORE/core_cm3.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+CORE/%.o: ../CORE/%.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: GNU ARM Cross C Compiler'
+ arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE" -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes" -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM" -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_gpio.d b/Debug/PERIPHERAL/Sources/gw1ns4c_gpio.d
new file mode 100644
index 0000000..4cc1fe0
--- /dev/null
+++ b/Debug/PERIPHERAL/Sources/gw1ns4c_gpio.d
@@ -0,0 +1,40 @@
+PERIPHERAL/Sources/gw1ns4c_gpio.o: ../PERIPHERAL/Sources/gw1ns4c_gpio.c \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h:
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_gpio.o b/Debug/PERIPHERAL/Sources/gw1ns4c_gpio.o
new file mode 100644
index 0000000..7635127
Binary files /dev/null and b/Debug/PERIPHERAL/Sources/gw1ns4c_gpio.o differ
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_i2c.d b/Debug/PERIPHERAL/Sources/gw1ns4c_i2c.d
new file mode 100644
index 0000000..e4358e6
--- /dev/null
+++ b/Debug/PERIPHERAL/Sources/gw1ns4c_i2c.d
@@ -0,0 +1,40 @@
+PERIPHERAL/Sources/gw1ns4c_i2c.o: ../PERIPHERAL/Sources/gw1ns4c_i2c.c \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h:
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_i2c.o b/Debug/PERIPHERAL/Sources/gw1ns4c_i2c.o
new file mode 100644
index 0000000..2562bc5
Binary files /dev/null and b/Debug/PERIPHERAL/Sources/gw1ns4c_i2c.o differ
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_misc.d b/Debug/PERIPHERAL/Sources/gw1ns4c_misc.d
new file mode 100644
index 0000000..f94bfa0
--- /dev/null
+++ b/Debug/PERIPHERAL/Sources/gw1ns4c_misc.d
@@ -0,0 +1,40 @@
+PERIPHERAL/Sources/gw1ns4c_misc.o: ../PERIPHERAL/Sources/gw1ns4c_misc.c \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h:
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_misc.o b/Debug/PERIPHERAL/Sources/gw1ns4c_misc.o
new file mode 100644
index 0000000..367f88a
Binary files /dev/null and b/Debug/PERIPHERAL/Sources/gw1ns4c_misc.o differ
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_rtc.d b/Debug/PERIPHERAL/Sources/gw1ns4c_rtc.d
new file mode 100644
index 0000000..ffeade3
--- /dev/null
+++ b/Debug/PERIPHERAL/Sources/gw1ns4c_rtc.d
@@ -0,0 +1,40 @@
+PERIPHERAL/Sources/gw1ns4c_rtc.o: ../PERIPHERAL/Sources/gw1ns4c_rtc.c \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h:
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_rtc.o b/Debug/PERIPHERAL/Sources/gw1ns4c_rtc.o
new file mode 100644
index 0000000..f0160dd
Binary files /dev/null and b/Debug/PERIPHERAL/Sources/gw1ns4c_rtc.o differ
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_spi.d b/Debug/PERIPHERAL/Sources/gw1ns4c_spi.d
new file mode 100644
index 0000000..9d494f5
--- /dev/null
+++ b/Debug/PERIPHERAL/Sources/gw1ns4c_spi.d
@@ -0,0 +1,40 @@
+PERIPHERAL/Sources/gw1ns4c_spi.o: ../PERIPHERAL/Sources/gw1ns4c_spi.c \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h:
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_spi.o b/Debug/PERIPHERAL/Sources/gw1ns4c_spi.o
new file mode 100644
index 0000000..8931a79
Binary files /dev/null and b/Debug/PERIPHERAL/Sources/gw1ns4c_spi.o differ
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_syscon.d b/Debug/PERIPHERAL/Sources/gw1ns4c_syscon.d
new file mode 100644
index 0000000..33f09a5
--- /dev/null
+++ b/Debug/PERIPHERAL/Sources/gw1ns4c_syscon.d
@@ -0,0 +1,41 @@
+PERIPHERAL/Sources/gw1ns4c_syscon.o: \
+ ../PERIPHERAL/Sources/gw1ns4c_syscon.c \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h:
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_syscon.o b/Debug/PERIPHERAL/Sources/gw1ns4c_syscon.o
new file mode 100644
index 0000000..c0470da
Binary files /dev/null and b/Debug/PERIPHERAL/Sources/gw1ns4c_syscon.o differ
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_timer.d b/Debug/PERIPHERAL/Sources/gw1ns4c_timer.d
new file mode 100644
index 0000000..49fa236
--- /dev/null
+++ b/Debug/PERIPHERAL/Sources/gw1ns4c_timer.d
@@ -0,0 +1,40 @@
+PERIPHERAL/Sources/gw1ns4c_timer.o: ../PERIPHERAL/Sources/gw1ns4c_timer.c \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h:
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_timer.o b/Debug/PERIPHERAL/Sources/gw1ns4c_timer.o
new file mode 100644
index 0000000..023a384
Binary files /dev/null and b/Debug/PERIPHERAL/Sources/gw1ns4c_timer.o differ
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_uart.d b/Debug/PERIPHERAL/Sources/gw1ns4c_uart.d
new file mode 100644
index 0000000..2e6a8c7
--- /dev/null
+++ b/Debug/PERIPHERAL/Sources/gw1ns4c_uart.d
@@ -0,0 +1,40 @@
+PERIPHERAL/Sources/gw1ns4c_uart.o: ../PERIPHERAL/Sources/gw1ns4c_uart.c \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h:
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_uart.o b/Debug/PERIPHERAL/Sources/gw1ns4c_uart.o
new file mode 100644
index 0000000..0a5746f
Binary files /dev/null and b/Debug/PERIPHERAL/Sources/gw1ns4c_uart.o differ
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_wdog.d b/Debug/PERIPHERAL/Sources/gw1ns4c_wdog.d
new file mode 100644
index 0000000..97fdb27
--- /dev/null
+++ b/Debug/PERIPHERAL/Sources/gw1ns4c_wdog.d
@@ -0,0 +1,40 @@
+PERIPHERAL/Sources/gw1ns4c_wdog.o: ../PERIPHERAL/Sources/gw1ns4c_wdog.c \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h:
diff --git a/Debug/PERIPHERAL/Sources/gw1ns4c_wdog.o b/Debug/PERIPHERAL/Sources/gw1ns4c_wdog.o
new file mode 100644
index 0000000..827de83
Binary files /dev/null and b/Debug/PERIPHERAL/Sources/gw1ns4c_wdog.o differ
diff --git a/Debug/PERIPHERAL/Sources/subdir.mk b/Debug/PERIPHERAL/Sources/subdir.mk
new file mode 100644
index 0000000..adb2bde
--- /dev/null
+++ b/Debug/PERIPHERAL/Sources/subdir.mk
@@ -0,0 +1,48 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../PERIPHERAL/Sources/gw1ns4c_gpio.c \
+../PERIPHERAL/Sources/gw1ns4c_i2c.c \
+../PERIPHERAL/Sources/gw1ns4c_misc.c \
+../PERIPHERAL/Sources/gw1ns4c_rtc.c \
+../PERIPHERAL/Sources/gw1ns4c_spi.c \
+../PERIPHERAL/Sources/gw1ns4c_syscon.c \
+../PERIPHERAL/Sources/gw1ns4c_timer.c \
+../PERIPHERAL/Sources/gw1ns4c_uart.c \
+../PERIPHERAL/Sources/gw1ns4c_wdog.c
+
+OBJS += \
+./PERIPHERAL/Sources/gw1ns4c_gpio.o \
+./PERIPHERAL/Sources/gw1ns4c_i2c.o \
+./PERIPHERAL/Sources/gw1ns4c_misc.o \
+./PERIPHERAL/Sources/gw1ns4c_rtc.o \
+./PERIPHERAL/Sources/gw1ns4c_spi.o \
+./PERIPHERAL/Sources/gw1ns4c_syscon.o \
+./PERIPHERAL/Sources/gw1ns4c_timer.o \
+./PERIPHERAL/Sources/gw1ns4c_uart.o \
+./PERIPHERAL/Sources/gw1ns4c_wdog.o
+
+C_DEPS += \
+./PERIPHERAL/Sources/gw1ns4c_gpio.d \
+./PERIPHERAL/Sources/gw1ns4c_i2c.d \
+./PERIPHERAL/Sources/gw1ns4c_misc.d \
+./PERIPHERAL/Sources/gw1ns4c_rtc.d \
+./PERIPHERAL/Sources/gw1ns4c_spi.d \
+./PERIPHERAL/Sources/gw1ns4c_syscon.d \
+./PERIPHERAL/Sources/gw1ns4c_timer.d \
+./PERIPHERAL/Sources/gw1ns4c_uart.d \
+./PERIPHERAL/Sources/gw1ns4c_wdog.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+PERIPHERAL/Sources/%.o: ../PERIPHERAL/Sources/%.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: GNU ARM Cross C Compiler'
+ arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE" -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes" -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM" -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
diff --git a/Debug/STARTUP/startup_gw1ns4c.d b/Debug/STARTUP/startup_gw1ns4c.d
new file mode 100644
index 0000000..b3c0d97
--- /dev/null
+++ b/Debug/STARTUP/startup_gw1ns4c.d
@@ -0,0 +1 @@
+STARTUP/startup_gw1ns4c.o: ../STARTUP/startup_gw1ns4c.S
diff --git a/Debug/STARTUP/startup_gw1ns4c.o b/Debug/STARTUP/startup_gw1ns4c.o
new file mode 100644
index 0000000..52b6d81
Binary files /dev/null and b/Debug/STARTUP/startup_gw1ns4c.o differ
diff --git a/Debug/STARTUP/subdir.mk b/Debug/STARTUP/subdir.mk
new file mode 100644
index 0000000..0cb80b9
--- /dev/null
+++ b/Debug/STARTUP/subdir.mk
@@ -0,0 +1,24 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+S_UPPER_SRCS += \
+../STARTUP/startup_gw1ns4c.S
+
+OBJS += \
+./STARTUP/startup_gw1ns4c.o
+
+S_UPPER_DEPS += \
+./STARTUP/startup_gw1ns4c.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+STARTUP/%.o: ../STARTUP/%.S
+ @echo 'Building file: $<'
+ @echo 'Invoking: GNU ARM Cross Assembler'
+ arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -x assembler-with-cpp -D__STARTUP_CLEAR_BSS -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
diff --git a/Debug/SYSTEM/subdir.mk b/Debug/SYSTEM/subdir.mk
new file mode 100644
index 0000000..ca172fc
--- /dev/null
+++ b/Debug/SYSTEM/subdir.mk
@@ -0,0 +1,24 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../SYSTEM/system_gw1ns4c.c
+
+OBJS += \
+./SYSTEM/system_gw1ns4c.o
+
+C_DEPS += \
+./SYSTEM/system_gw1ns4c.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+SYSTEM/%.o: ../SYSTEM/%.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: GNU ARM Cross C Compiler'
+ arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE" -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes" -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM" -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
diff --git a/Debug/SYSTEM/system_gw1ns4c.d b/Debug/SYSTEM/system_gw1ns4c.d
new file mode 100644
index 0000000..1e3ce85
--- /dev/null
+++ b/Debug/SYSTEM/system_gw1ns4c.d
@@ -0,0 +1,42 @@
+SYSTEM/system_gw1ns4c.o: ../SYSTEM/system_gw1ns4c.c ../SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h \
+ ../SYSTEM/system_gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h
+
+../SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h:
+
+../SYSTEM/system_gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h:
diff --git a/Debug/SYSTEM/system_gw1ns4c.o b/Debug/SYSTEM/system_gw1ns4c.o
new file mode 100644
index 0000000..6273ec1
Binary files /dev/null and b/Debug/SYSTEM/system_gw1ns4c.o differ
diff --git a/Debug/USER/gw1ns4c_it.d b/Debug/USER/gw1ns4c_it.d
new file mode 100644
index 0000000..a56b08c
--- /dev/null
+++ b/Debug/USER/gw1ns4c_it.d
@@ -0,0 +1,42 @@
+USER/gw1ns4c_it.o: ../USER/gw1ns4c_it.c ../USER/gw1ns4c_it.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h
+
+../USER/gw1ns4c_it.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h:
diff --git a/Debug/USER/gw1ns4c_it.o b/Debug/USER/gw1ns4c_it.o
new file mode 100644
index 0000000..9571d2c
Binary files /dev/null and b/Debug/USER/gw1ns4c_it.o differ
diff --git a/Debug/USER/main.d b/Debug/USER/main.d
new file mode 100644
index 0000000..da9c7f3
--- /dev/null
+++ b/Debug/USER/main.d
@@ -0,0 +1,40 @@
+USER/main.o: ../USER/main.c \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h \
+ C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE/core_cm3.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM/system_gw1ns4c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER/gw1ns4c_conf.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_gpio.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_wdog.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_uart.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_timer.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_spi.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_i2c.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_misc.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_syscon.h:
+
+C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes/gw1ns4c_rtc.h:
diff --git a/Debug/USER/main.o b/Debug/USER/main.o
new file mode 100644
index 0000000..7b79eb3
Binary files /dev/null and b/Debug/USER/main.o differ
diff --git a/Debug/USER/subdir.mk b/Debug/USER/subdir.mk
new file mode 100644
index 0000000..ce33a19
--- /dev/null
+++ b/Debug/USER/subdir.mk
@@ -0,0 +1,27 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../USER/gw1ns4c_it.c \
+../USER/main.c
+
+OBJS += \
+./USER/gw1ns4c_it.o \
+./USER/main.o
+
+C_DEPS += \
+./USER/gw1ns4c_it.d \
+./USER/main.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+USER/%.o: ../USER/%.c
+ @echo 'Building file: $<'
+ @echo 'Invoking: GNU ARM Cross C Compiler'
+ arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\CORE" -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\PERIPHERAL\Includes" -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\SYSTEM" -I"C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\USER" -std=gnu11 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
+ @echo 'Finished building: $<'
+ @echo ' '
+
+
diff --git a/Debug/cm3_1602_lcd.bin b/Debug/cm3_1602_lcd.bin
new file mode 100644
index 0000000..98ce1c4
Binary files /dev/null and b/Debug/cm3_1602_lcd.bin differ
diff --git a/Debug/cm3_1602_lcd.elf b/Debug/cm3_1602_lcd.elf
new file mode 100644
index 0000000..97f6c18
Binary files /dev/null and b/Debug/cm3_1602_lcd.elf differ
diff --git a/Debug/cm3_1602_lcd.map b/Debug/cm3_1602_lcd.map
new file mode 100644
index 0000000..48072a7
--- /dev/null
+++ b/Debug/cm3_1602_lcd.map
@@ -0,0 +1,2311 @@
+Archive member included to satisfy reference by file (symbol)
+
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-exit.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/crt0.o (exit)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-impure.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-exit.o) (_global_impure_ptr)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-init.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/crt0.o (__libc_init_array)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-memset.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/crt0.o (memset)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-printf.o)
+ ./USER/main.o (printf)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-printf.o) (_vfprintf_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-wsetup.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (__swsetup_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-__call_atexit.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-exit.o) (__call_exitprocs)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-atexit.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-__call_atexit.o) (atexit)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-dtoa.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (_dtoa_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-fflush.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (_fflush_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-findfp.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (__sinit)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-fini.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-__call_atexit.o) (__libc_fini_array)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-freer.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (_free_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-fwalk.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-findfp.o) (_fwalk)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-localeconv.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (_localeconv_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-lock.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (__retarget_lock_init_recursive)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-makebuf.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-wsetup.o) (__smakebuf_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-mallocr.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (_malloc_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-memchr-stub.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (memchr)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-memcpy.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-dtoa.o) (memcpy)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-mlock.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-freer.o) (__malloc_lock)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-mprec.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-dtoa.o) (_Balloc)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-s_frexp.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (frexp)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-sbrkr.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-freer.o) (_sbrk_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-stdio.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-findfp.o) (__sread)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-strlen-stub.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (strlen)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-strncpy.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (strncpy)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfiprintf.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o) (__sprint_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-writer.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-stdio.o) (_write_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-__atexit.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-atexit.o) (__register_exitproc)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-callocr.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-mprec.o) (_calloc_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-closer.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-stdio.o) (_close_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-fclose.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-findfp.o) (_fclose_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-fputwc.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfiprintf.o) (_fputwc_r)
+c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-fstatr.o)
+ c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-makebuf.o) (_fstat_r)
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+ .text 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(isatty.o)
+ .data 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(isatty.o)
+ .bss 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(isatty.o)
+ .text 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(lseek.o)
+ .data 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(lseek.o)
+ .bss 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(lseek.o)
+ .text 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(read.o)
+ .data 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(read.o)
+ .bss 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(read.o)
+ .text 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(sbrk.o)
+ .data 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(sbrk.o)
+ .bss 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(sbrk.o)
+ .text 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(write.o)
+ .data 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(write.o)
+ .bss 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(write.o)
+ .text 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(_exit.o)
+ .data 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(_exit.o)
+ .bss 0x00000000 0x0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(_exit.o)
+
+Memory Configuration
+
+Name Origin Length Attributes
+FLASH 0x00000000 0x00008000 xr
+RAM 0x20000000 0x00004000 xrw
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/thumb/v7-m/nofp/crti.o
+LOAD c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/thumb/v7-m/nofp/crtbegin.o
+LOAD c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp/crt0.o
+LOAD ./USER/gw1ns4c_it.o
+LOAD ./USER/main.o
+LOAD ./SYSTEM/system_gw1ns4c.o
+LOAD ./STARTUP/startup_gw1ns4c.o
+LOAD ./PERIPHERAL/Sources/gw1ns4c_gpio.o
+LOAD ./PERIPHERAL/Sources/gw1ns4c_i2c.o
+LOAD ./PERIPHERAL/Sources/gw1ns4c_misc.o
+LOAD ./PERIPHERAL/Sources/gw1ns4c_rtc.o
+LOAD ./PERIPHERAL/Sources/gw1ns4c_spi.o
+LOAD ./PERIPHERAL/Sources/gw1ns4c_syscon.o
+LOAD ./PERIPHERAL/Sources/gw1ns4c_timer.o
+LOAD ./PERIPHERAL/Sources/gw1ns4c_uart.o
+LOAD ./PERIPHERAL/Sources/gw1ns4c_wdog.o
+LOAD ./CORE/core_cm3.o
+START GROUP
+LOAD c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/thumb/v7-m/nofp\libgcc.a
+LOAD c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a
+LOAD c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc.a
+END GROUP
+LOAD c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/thumb/v7-m/nofp/crtend.o
+LOAD c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/thumb/v7-m/nofp/crtn.o
+START GROUP
+LOAD c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/thumb/v7-m/nofp\libgcc.a
+LOAD c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libc.a
+LOAD c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libm.a
+LOAD c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a
+END GROUP
+
+.text 0x00000000 0x63f5
+ *(.isr_vector)
+ .isr_vector 0x00000000 0xc0 ./STARTUP/startup_gw1ns4c.o
+ 0x00000000 __isr_vector
+ *(.text*)
+ .text.NMI_Handler
+ 0x000000c0 0xc ./USER/gw1ns4c_it.o
+ 0x000000c0 NMI_Handler
+ .text.HardFault_Handler
+ 0x000000cc 0x6 ./USER/gw1ns4c_it.o
+ 0x000000cc HardFault_Handler
+ .text.MemManage_Handler
+ 0x000000d2 0x6 ./USER/gw1ns4c_it.o
+ 0x000000d2 MemManage_Handler
+ .text.BusFault_Handler
+ 0x000000d8 0x6 ./USER/gw1ns4c_it.o
+ 0x000000d8 BusFault_Handler
+ .text.UsageFault_Handler
+ 0x000000de 0x6 ./USER/gw1ns4c_it.o
+ 0x000000de UsageFault_Handler
+ .text.SVC_Handler
+ 0x000000e4 0xc ./USER/gw1ns4c_it.o
+ 0x000000e4 SVC_Handler
+ .text.DebugMon_Handler
+ 0x000000f0 0xc ./USER/gw1ns4c_it.o
+ 0x000000f0 DebugMon_Handler
+ .text.PendSV_Handler
+ 0x000000fc 0xc ./USER/gw1ns4c_it.o
+ 0x000000fc PendSV_Handler
+ .text.SysTick_Handler
+ 0x00000108 0xc ./USER/gw1ns4c_it.o
+ 0x00000108 SysTick_Handler
+ .text.USER_INT0_Handler
+ 0x00000114 0xc ./USER/gw1ns4c_it.o
+ 0x00000114 USER_INT0_Handler
+ .text.USER_INT1_Handler
+ 0x00000120 0xc ./USER/gw1ns4c_it.o
+ 0x00000120 USER_INT1_Handler
+ .text.USER_INT2_Handler
+ 0x0000012c 0xc ./USER/gw1ns4c_it.o
+ 0x0000012c USER_INT2_Handler
+ .text.USER_INT3_Handler
+ 0x00000138 0xc ./USER/gw1ns4c_it.o
+ 0x00000138 USER_INT3_Handler
+ .text.USER_INT4_Handler
+ 0x00000144 0xc ./USER/gw1ns4c_it.o
+ 0x00000144 USER_INT4_Handler
+ .text.USER_INT5_Handler
+ 0x00000150 0xc ./USER/gw1ns4c_it.o
+ 0x00000150 USER_INT5_Handler
+ .text.UART0_Handler
+ 0x0000015c 0xc ./USER/gw1ns4c_it.o
+ 0x0000015c UART0_Handler
+ .text.UART1_Handler
+ 0x00000168 0xc ./USER/gw1ns4c_it.o
+ 0x00000168 UART1_Handler
+ .text.TIMER0_Handler
+ 0x00000174 0xc ./USER/gw1ns4c_it.o
+ 0x00000174 TIMER0_Handler
+ .text.TIMER1_Handler
+ 0x00000180 0xc ./USER/gw1ns4c_it.o
+ 0x00000180 TIMER1_Handler
+ .text.I2C_Handler
+ 0x0000018c 0xc ./USER/gw1ns4c_it.o
+ 0x0000018c I2C_Handler
+ .text.RTC_Handler
+ 0x00000198 0xc ./USER/gw1ns4c_it.o
+ 0x00000198 RTC_Handler
+ .text.PORT0_0_Handler
+ 0x000001a4 0xc ./USER/gw1ns4c_it.o
+ 0x000001a4 PORT0_0_Handler
+ .text.PORT0_1_Handler
+ 0x000001b0 0xc ./USER/gw1ns4c_it.o
+ 0x000001b0 PORT0_1_Handler
+ .text.PORT0_2_Handler
+ 0x000001bc 0xc ./USER/gw1ns4c_it.o
+ 0x000001bc PORT0_2_Handler
+ .text.PORT0_3_Handler
+ 0x000001c8 0xc ./USER/gw1ns4c_it.o
+ 0x000001c8 PORT0_3_Handler
+ .text.PORT0_4_Handler
+ 0x000001d4 0xc ./USER/gw1ns4c_it.o
+ 0x000001d4 PORT0_4_Handler
+ .text.PORT0_5_Handler
+ 0x000001e0 0xc ./USER/gw1ns4c_it.o
+ 0x000001e0 PORT0_5_Handler
+ .text.PORT0_6_Handler
+ 0x000001ec 0xc ./USER/gw1ns4c_it.o
+ 0x000001ec PORT0_6_Handler
+ .text.PORT0_7_Handler
+ 0x000001f8 0xc ./USER/gw1ns4c_it.o
+ 0x000001f8 PORT0_7_Handler
+ .text.PORT0_8_Handler
+ 0x00000204 0xc ./USER/gw1ns4c_it.o
+ 0x00000204 PORT0_8_Handler
+ .text.PORT0_9_Handler
+ 0x00000210 0xc ./USER/gw1ns4c_it.o
+ 0x00000210 PORT0_9_Handler
+ .text.PORT0_10_Handler
+ 0x0000021c 0xc ./USER/gw1ns4c_it.o
+ 0x0000021c PORT0_10_Handler
+ .text.PORT0_11_Handler
+ 0x00000228 0xc ./USER/gw1ns4c_it.o
+ 0x00000228 PORT0_11_Handler
+ .text.PORT0_12_Handler
+ 0x00000234 0xc ./USER/gw1ns4c_it.o
+ 0x00000234 PORT0_12_Handler
+ .text.PORT0_13_Handler
+ 0x00000240 0xc ./USER/gw1ns4c_it.o
+ 0x00000240 PORT0_13_Handler
+ .text.PORT0_14_Handler
+ 0x0000024c 0xc ./USER/gw1ns4c_it.o
+ 0x0000024c PORT0_14_Handler
+ .text.PORT0_15_Handler
+ 0x00000258 0xc ./USER/gw1ns4c_it.o
+ 0x00000258 PORT0_15_Handler
+ .text.main 0x00000264 0x3c ./USER/main.o
+ 0x00000264 main
+ .text.GPIOInit
+ 0x000002a0 0x30 ./USER/main.o
+ 0x000002a0 GPIOInit
+ .text.delay_ms
+ 0x000002d0 0x34 ./USER/main.o
+ 0x000002d0 delay_ms
+ .text.SystemInit
+ 0x00000304 0x40 ./SYSTEM/system_gw1ns4c.o
+ 0x00000304 SystemInit
+ .text 0x00000344 0x98 ./STARTUP/startup_gw1ns4c.o
+ 0x00000344 Reset_Handler
+ 0x000003aa PORT0_COMB_Handler
+ 0x000003b4 UARTOVF_Handler
+ 0x000003ba Spare15_Handler
+ .text.GPIO_Init
+ 0x000003dc 0x190 ./PERIPHERAL/Sources/gw1ns4c_gpio.o
+ 0x000003dc GPIO_Init
+ .text.GPIO_SetBit
+ 0x0000056c 0x20 ./PERIPHERAL/Sources/gw1ns4c_gpio.o
+ 0x0000056c GPIO_SetBit
+ .text.GPIO_ResetBit
+ 0x0000058c 0x22 ./PERIPHERAL/Sources/gw1ns4c_gpio.o
+ 0x0000058c GPIO_ResetBit
+ *fill* 0x000005ae 0x2
+ .text.exit 0x000005b0 0x20 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-exit.o)
+ 0x000005b0 exit
+ .text.memset 0x000005d0 0xa0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-memset.o)
+ 0x000005d0 memset
+ .text.printf 0x00000670 0x28 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-printf.o)
+ 0x00000670 printf
+ .text._vfprintf_r
+ 0x00000698 0x1b04 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o)
+ 0x00000698 _vfprintf_r
+ .text.__sbprintf
+ 0x0000219c 0x88 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-vfprintf.o)
+ .text.__swsetup_r
+ 0x00002224 0xcc c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-wsetup.o)
+ 0x00002224 __swsetup_r
+ .text.__call_exitprocs
+ 0x000022f0 0xb0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-__call_atexit.o)
+ 0x000022f0 __call_exitprocs
+ .text.quorem 0x000023a0 0x12c c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-dtoa.o)
+ *fill* 0x000024cc 0x4
+ .text._dtoa_r 0x000024d0 0xe6c c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-dtoa.o)
+ 0x000024d0 _dtoa_r
+ .text.__sflush_r
+ 0x0000333c 0x144 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-fflush.o)
+ 0x0000333c __sflush_r
+ .text._fflush_r
+ 0x00003480 0x5c c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-fflush.o)
+ 0x00003480 _fflush_r
+ .text.std 0x000034dc 0x50 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-findfp.o)
+ .text._cleanup_r
+ 0x0000352c 0xc c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-findfp.o)
+ 0x0000352c _cleanup_r
+ .text.__sinit 0x00003538 0x5c c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-findfp.o)
+ 0x00003538 __sinit
+ .text.__sfp_lock_acquire
+ 0x00003594 0xc c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-findfp.o)
+ 0x00003594 __sfp_lock_acquire
+ .text.__sfp_lock_release
+ 0x000035a0 0xc c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-findfp.o)
+ 0x000035a0 __sfp_lock_release
+ .text._malloc_trim_r
+ 0x000035ac 0xa0 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-freer.o)
+ 0x000035ac _malloc_trim_r
+ .text._free_r 0x0000364c 0x1f4 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-freer.o)
+ 0x0000364c _free_r
+ .text._fwalk_reent
+ 0x00003840 0x50 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-fwalk.o)
+ 0x00003840 _fwalk_reent
+ .text._localeconv_r
+ 0x00003890 0x8 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-localeconv.o)
+ 0x00003890 _localeconv_r
+ .text.__retarget_lock_init_recursive
+ 0x00003898 0x4 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-lock.o)
+ 0x00003898 __retarget_lock_init_recursive
+ .text.__retarget_lock_close_recursive
+ 0x0000389c 0x4 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-lock.o)
+ 0x0000389c __retarget_lock_close_recursive
+ .text.__retarget_lock_acquire_recursive
+ 0x000038a0 0x4 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-lock.o)
+ 0x000038a0 __retarget_lock_acquire_recursive
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+ 0x000038a4 __retarget_lock_release_recursive
+ .text.__swhatbuf_r
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+ 0x000038a8 __swhatbuf_r
+ .text.__smakebuf_r
+ 0x00003904 0x94 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-makebuf.o)
+ 0x00003904 __smakebuf_r
+ .text._malloc_r
+ 0x00003998 0x558 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-mallocr.o)
+ 0x00003998 _malloc_r
+ .text.memchr 0x00003ef0 0x8c c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-memchr-stub.o)
+ 0x00003ef0 memchr
+ .text 0x00003f7c 0xec c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-memcpy.o)
+ 0x00003f7c memcpy
+ .text.__malloc_lock
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+ 0x00004068 __malloc_lock
+ .text.__malloc_unlock
+ 0x00004074 0xc c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-mlock.o)
+ 0x00004074 __malloc_unlock
+ .text._Balloc 0x00004080 0x4c c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-mprec.o)
+ 0x00004080 _Balloc
+ .text._Bfree 0x000040cc 0x14 c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libg.a(lib_a-mprec.o)
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+ 0x24 (size before relaxing)
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+ 0x24 (size before relaxing)
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+ 0x24 (size before relaxing)
+
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+ .stabstr 0x00000000 0x14d c:/gmd/toolchain/arm_toolchain/bin/../lib/gcc/arm-none-eabi/8.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/nofp\libnosys.a(close.o)
diff --git a/Debug/makefile b/Debug/makefile
new file mode 100644
index 0000000..e989248
--- /dev/null
+++ b/Debug/makefile
@@ -0,0 +1,74 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include USER/subdir.mk
+-include SYSTEM/subdir.mk
+-include STARTUP/subdir.mk
+-include PERIPHERAL/Sources/subdir.mk
+-include CORE/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(ASM_DEPS)),)
+-include $(ASM_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+# Add inputs and outputs from these tool invocations to the build variables
+SECONDARY_FLASH += \
+cm3_1602_lcd.bin \
+
+SECONDARY_SIZE += \
+cm3_1602_lcd.siz \
+
+
+# All Target
+all: cm3_1602_lcd.elf secondary-outputs
+
+# Tool invocations
+cm3_1602_lcd.elf: $(OBJS) $(USER_OBJS)
+ @echo 'Building target: $@'
+ @echo 'Invoking: GNU ARM Cross C Linker'
+ arm-none-eabi-gcc -mcpu=cortex-m3 -mthumb -O0 -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -g3 -T "C:\Users\Dorian\Documents\MCU_Projects\cm3_1602_lcd\gw1ns4c_flash.ld" -Xlinker --gc-sections -Wl,-Map,"cm3_1602_lcd.map" -o "cm3_1602_lcd.elf" $(OBJS) $(USER_OBJS) $(LIBS)
+ @echo 'Finished building target: $@'
+ @echo ' '
+
+cm3_1602_lcd.bin: cm3_1602_lcd.elf
+ @echo 'Invoking: GNU ARM Cross Create Flash Image'
+ arm-none-eabi-objcopy -O binary "cm3_1602_lcd.elf" "cm3_1602_lcd.bin"
+ @echo 'Finished building: $@'
+ @echo ' '
+
+cm3_1602_lcd.siz: cm3_1602_lcd.elf
+ @echo 'Invoking: GNU ARM Cross Print Size'
+ arm-none-eabi-size --format=berkeley "cm3_1602_lcd.elf"
+ @echo 'Finished building: $@'
+ @echo ' '
+
+# Other Targets
+clean:
+ -$(RM) $(OBJS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS) cm3_1602_lcd.elf
+ -@echo ' '
+
+secondary-outputs: $(SECONDARY_FLASH) $(SECONDARY_SIZE)
+
+.PHONY: all clean dependents
+.SECONDARY:
+
+-include ../makefile.targets
diff --git a/Debug/objects.mk b/Debug/objects.mk
new file mode 100644
index 0000000..742c2da
--- /dev/null
+++ b/Debug/objects.mk
@@ -0,0 +1,8 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/Debug/sources.mk b/Debug/sources.mk
new file mode 100644
index 0000000..1ea9459
--- /dev/null
+++ b/Debug/sources.mk
@@ -0,0 +1,25 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+################################################################################
+
+ELF_SRCS :=
+OBJ_SRCS :=
+ASM_SRCS :=
+C_SRCS :=
+S_UPPER_SRCS :=
+O_SRCS :=
+OBJS :=
+SECONDARY_FLASH :=
+SECONDARY_SIZE :=
+ASM_DEPS :=
+S_UPPER_DEPS :=
+C_DEPS :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+CORE \
+PERIPHERAL/Sources \
+STARTUP \
+SYSTEM \
+USER \
+
diff --git a/PERIPHERAL/Includes/gw1ns4c_gpio.h b/PERIPHERAL/Includes/gw1ns4c_gpio.h
new file mode 100644
index 0000000..e2e1672
--- /dev/null
+++ b/PERIPHERAL/Includes/gw1ns4c_gpio.h
@@ -0,0 +1,224 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_gpio.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the GPIO firmware library.
+ ******************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GW1NS4C_GPIO_H
+#define __GW1NS4C_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/** @defgroup GPIO_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief GPIO Mode definition
+ */
+typedef enum
+{
+ GPIO_Mode_IN = 0, /* GPIO input */
+ GPIO_Mode_OUT, /* GPIO output */
+ GPIO_Mode_AF /* GPIO alternate function */
+}GPIOMode_TypeDef;
+
+/**
+ * @brief GPIO Interrupt definition
+ */
+typedef enum
+{
+ GPIO_Int_Disable = 0, /* Disable : Interrupt enable=0 */
+ GPIO_Int_Low_Level, /* Low-level : Interrupt enable=1 */
+ GPIO_Int_High_Level, /* High-level : Interrupt enable=1 & polarity=1 */
+ GPIO_Int_Falling_Edge, /* Falling edge : Interrupt enable=1 & type=1 */
+ GPIO_Int_Rising_Edge /* Rising edge : Interrupt enable=1 & polarity=1 & type=1 */
+}GPIOInt_TypeDef;
+
+/**
+ * @brief GPIO Initialization Structure definition
+ */
+typedef struct
+{
+ uint32_t GPIO_Pin; /* GPIO pin definition */
+
+ GPIOMode_TypeDef GPIO_Mode; /* GPIO mode */
+
+ GPIOInt_TypeDef GPIO_Int; /* GPIO interrupt */
+
+}GPIO_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Macros
+ * @{
+ */
+
+#define GPIO_Pin_0 ((uint32_t)0x00000001) /*!< Pin 0 selected */
+#define GPIO_Pin_1 ((uint32_t)0x00000002) /*!< Pin 1 selected */
+#define GPIO_Pin_2 ((uint32_t)0x00000004) /*!< Pin 2 selected */
+#define GPIO_Pin_3 ((uint32_t)0x00000008) /*!< Pin 3 selected */
+#define GPIO_Pin_4 ((uint32_t)0x00000010) /*!< Pin 4 selected */
+#define GPIO_Pin_5 ((uint32_t)0x00000020) /*!< Pin 5 selected */
+#define GPIO_Pin_6 ((uint32_t)0x00000040) /*!< Pin 6 selected */
+#define GPIO_Pin_7 ((uint32_t)0x00000080) /*!< Pin 7 selected */
+#define GPIO_Pin_8 ((uint32_t)0x00000100) /*!< Pin 8 selected */
+#define GPIO_Pin_9 ((uint32_t)0x00000200) /*!< Pin 9 selected */
+#define GPIO_Pin_10 ((uint32_t)0x00000400) /*!< Pin 10 selected */
+#define GPIO_Pin_11 ((uint32_t)0x00000800) /*!< Pin 11 selected */
+#define GPIO_Pin_12 ((uint32_t)0x00001000) /*!< Pin 12 selected */
+#define GPIO_Pin_13 ((uint32_t)0x00002000) /*!< Pin 13 selected */
+#define GPIO_Pin_14 ((uint32_t)0x00004000) /*!< Pin 14 selected */
+#define GPIO_Pin_15 ((uint32_t)0x00008000) /*!< Pin 15 selected */
+#define GPIO_Pin_All ((uint32_t)0x0000FFFF) /*!< All pins selected */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Exported_Functions
+ * @{
+ */
+
+/**
+ * @brief GPIO Initialization.
+ */
+extern void GPIO_Init(GPIO_TypeDef* GPIOx,GPIO_InitTypeDef* GPIO_InitStruct);
+
+/**
+ * @brief Set GPIO Output Enable.
+ */
+extern void GPIO_SetOutEnable(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Clear GPIO Output Enable.
+ */
+extern void GPIO_ClrOutEnable(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Returns GPIO Output Enable.
+ */
+extern uint32_t GPIO_GetOutEnable(GPIO_TypeDef* GPIOx);
+
+/**
+ * @brief Set GPIO Output = "1"
+ */
+extern void GPIO_SetBit(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Set GPIO Output = "0"
+ */
+extern void GPIO_ResetBit(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Write GPIO Output
+ */
+extern void GPIO_WriteBits(GPIO_TypeDef* GPIOx,uint32_t value);
+
+/**
+ * @brief Read GPIO Input
+ */
+extern uint32_t GPIO_ReadBits(GPIO_TypeDef* GPIOx);
+
+/**
+ * @brief Set GPIO Alternate function Enable.
+ */
+extern void GPIO_SetAltFunc(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Clear GPIO Alternate function Enable.
+ */
+extern void GPIO_ClrAltFunc(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Returns GPIO Alternate function Enable.
+ */
+extern uint32_t GPIO_GetAltFunc(GPIO_TypeDef* GPIOx);
+
+/**
+ * @brief Clear GPIO Interrupt request.
+ */
+extern void GPIO_IntClear(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Get GPIO Interrupt request.
+ */
+extern uint32_t GPIO_GetIntStatus(GPIO_TypeDef* GPIOx);
+
+/**
+ * @brief Enable GPIO Interrupt request.
+ */
+extern uint32_t GPIO_SetIntEnable(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Disable GPIO Interrupt request.
+ */
+extern uint32_t GPIO_ClrIntEnable(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Setup GPIO Interrupt as high level.
+ */
+extern void GPIO_SetIntHighLevel(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Setup GPIO Interrupt as rising edge.
+ */
+extern void GPIO_SetIntRisingEdge(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Setup GPIO Interrupt as low level.
+ */
+extern void GPIO_SetIntLowLevel(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Setup GPIO Interrupt as falling edge.
+ */
+extern void GPIO_SetIntFallingEdge(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin);
+
+/**
+ * @brief Setup GPIO output value using Masked access.
+ */
+extern void GPIO_MaskedWrite(GPIO_TypeDef* GPIOx,uint32_t value,uint32_t mask);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GW1NS4C_GPIO_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Includes/gw1ns4c_i2c.h b/PERIPHERAL/Includes/gw1ns4c_i2c.h
new file mode 100644
index 0000000..67ce688
--- /dev/null
+++ b/PERIPHERAL/Includes/gw1ns4c_i2c.h
@@ -0,0 +1,110 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_i2c.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the I2C firmware library.
+ ******************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GW1NS4C_I2C_H
+#define __GW1NS4C_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c.h"
+
+#define I2C_CTR_EN ((uint32_t)0x00000080) /* Control Register : Enable I2C Core [7] */
+#define I2C_CTR_IEN ((uint32_t)0x00000040)
+#define I2C_CTR_PERE ((uint32_t)0x0000FFFF) /* Prescale Register : prescale value [15:0] */
+#define I2C_CMD_IACK ((uint32_t)0x00000001) /* Command Register : Interrupt acknowledage [0] */
+#define I2C_CMD_ACK ((uint32_t)0x00000008) /* Command Register : acknowledage [3] */
+#define I2C_CMD_WR ((uint32_t)0x00000010) /* Command Register : write data to slave [4] */
+#define I2C_CMD_RD ((uint32_t)0x00000020) /* Command Register : read data from slave [5] */
+#define I2C_CMD_STO ((uint32_t)0x00000040) /* Command Register : end to transmit[6] */
+#define I2C_CMD_STA ((uint32_t)0x00000080) /* Command Register : begin to transmit [7] */
+#define I2C_SR_TIP ((uint32_t)0x00000002) /* Status Register : data transmit status flag [1] */
+#define I2C_SR_AL ((uint32_t)0x00000020) /* Status Register : arbitration lose [5] */
+#define I2C_SR_BUSY ((uint32_t)0x00000040) /* Status Register : I2C busy status [6] */
+#define I2C_SR_RXACK ((uint32_t)0x00000080) /* Status Register : receive slave acknowledge signal [7] */
+
+/**
+ * @brief Initialize I2C.
+ */
+extern ErrorStatus I2C_Init(I2C_TypeDef * i2c, uint16_t speed);
+
+/**
+ * @brief Send byte to I2C serial bus
+ */
+extern void I2C_SendByte(I2C_TypeDef *i2c ,uint8_t slv_data,uint8_t data_address,uint8_t data);
+
+/**
+ * @brief Send the data to the serial bus.
+ */
+extern void I2C_SendBytes(I2C_TypeDef *i2c ,uint8_t slv_address,uint8_t data_start_address,uint8_t *data,int32_t data_num);
+
+/**
+ * @brief Send the data to the serial bus.
+ */
+extern void I2C_ReadBytes(I2C_TypeDef *i2c ,uint8_t slv_address,uint8_t data_start_address,uint8_t *data,int32_t data_num);
+
+/**
+ * @brief Receives 8-bits data from the serial bus.
+ */
+extern uint8_t I2C_ReceiveByte(I2C_TypeDef *i2c ,uint8_t slv_addr,uint8_t mem_addr);
+
+/**
+ * @brief Receive several bytes data a time from the serial bus.
+ */
+extern void I2C_ReceiveData(I2C_TypeDef *i2c ,uint8_t slv_addr,uint8_t data_addr,uint8_t *data,uint32_t data_size);
+
+/**
+ * @brief Send several bytes data a time to the serial bus.
+ */
+extern void I2C_SendData(I2C_TypeDef *i2c ,uint8_t slv_addr,uint8_t data_addr,uint8_t* data,uint32_t data_size);
+
+/**
+ * @brief Delay .
+ */
+extern void Delay_ms_i2c(__IO uint32_t delay_ms);
+
+/**
+ * @brief Initialize I2C Rate.
+ */
+extern uint16_t I2C_Rate_Set(I2C_TypeDef * i2c,uint16_t Rate);
+
+/**
+ * @brief Enable the I2C Core
+ */
+extern void I2C_Enable(I2C_TypeDef * i2c);
+
+/**
+ * @brief Close the I2C Core
+ */
+extern void I2C_UnEnable(I2C_TypeDef * i2c);
+
+/**
+ * @brief Open the i2C Interrupt.
+ */
+extern void I2C_InterruptOpen(I2C_TypeDef *i2c);
+
+/**
+ * @brief close the i2C Interrupt.
+ */
+extern void I2C_InterruptClose(I2C_TypeDef *i2c);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GW1NS4C_I2C_H */
+
+/*************************GowinSemiconductor*****END OF FILE*********************/
diff --git a/PERIPHERAL/Includes/gw1ns4c_misc.h b/PERIPHERAL/Includes/gw1ns4c_misc.h
new file mode 100644
index 0000000..b1db084
--- /dev/null
+++ b/PERIPHERAL/Includes/gw1ns4c_misc.h
@@ -0,0 +1,162 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_misc.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the miscellaneous firmware library.
+ ******************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GW1NS4C_MISC_H
+#define __GW1NS4C_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/** @defgroup MISC_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /* the IRQ channel to be enabled or disabled
+ param : IRQn_Type */
+
+ uint8_t NVIC_IRQChannelPreemptionPriority; /* the pre-emption priority
+ param : 0~7 NVIC_Priority_Table */
+
+ uint8_t NVIC_IRQChannelSubPriority; /* the subpriority level
+ param : 0~7 in NVIC_Priority_Table */
+
+ FunctionalState NVIC_IRQChannelCmd; /* whether the IRQ channel defined in NVIC_IRQChannel
+ param : enabled or disabled */
+}NVIC_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup NVIC_Priority_Table
+ * @{
+ */
+
+/**
+@code
+ The table below gives the allowed values of the pre-emption priority and subpriority according to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-7 | 0 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-3 | 1 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-1 | 2 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0 | 3 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ============================================================================================================================
+@endcode
+*/
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Macros
+ * @{
+ */
+
+/**
+ * @brief Vector Table Base
+ */
+#define NVIC_VectTab_RAM SRAM_BASE
+#define NVIC_VectTab_FLASH FLASH_BASE
+
+/**
+ * @brief Preemption Priority Group
+ */
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+ 0 bits for subpriority */
+
+/**
+ * @brief SysTick clock source
+ */
+#define SysTick_CLKSource_HCLK ((uint32_t) 0x00000004)
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Exported_Functions
+ * @{
+ */
+
+/**
+ * @brief Sets interrupt priority groups
+ */
+extern void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+
+/**
+ * @brief Initial interrupt priority
+ */
+extern void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+
+/**
+ * @brief Sets interrupt vector table location and offset
+ */
+extern void NVIC_SetVectorTable(uint32_t NVIC_VecTab,uint32_t Offset);
+
+/**
+ * @brief Sets systick clock source
+ */
+extern void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GW1NS4C_MISC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Includes/gw1ns4c_rtc.h b/PERIPHERAL/Includes/gw1ns4c_rtc.h
new file mode 100644
index 0000000..312f83b
--- /dev/null
+++ b/PERIPHERAL/Includes/gw1ns4c_rtc.h
@@ -0,0 +1,45 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_rtc.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the RTC firmware library.
+ ******************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GW1NS4C_RTC_H
+#define __GW1NS4C_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include
+#include "gw1ns4c.h"
+
+/* Functions ------------------------------------------------------------------*/
+extern uint32_t Get_Current_Value(void);
+extern void Set_Match_Value(uint32_t match_value);
+extern uint32_t Get_Match_Value(void);
+extern void Set_Load_Value(uint32_t load_value);
+extern uint32_t Get_Load_Value(void);
+extern void Start_RTC(void);
+extern void Close_RTC(void);
+extern void RTC_Inter_Mask_Set(void);
+extern uint8_t Get_RTC_Control_value(void);
+extern void RTC_Inter_Mask_Clr(void);
+extern uint8_t Get_RTC_Inter_Mask_value(void);
+extern void Clear_RTC_interrupt(void);
+extern void RTC_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GW1NS4C_RTC_H */
diff --git a/PERIPHERAL/Includes/gw1ns4c_spi.h b/PERIPHERAL/Includes/gw1ns4c_spi.h
new file mode 100644
index 0000000..6eb11b1
--- /dev/null
+++ b/PERIPHERAL/Includes/gw1ns4c_spi.h
@@ -0,0 +1,227 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_spi.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the SPI firmware library.
+ ******************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GW1NS4C_SPI_H
+#define __GW1NS4C_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SPI
+ * @{
+ */
+
+/** @defgroup SPI_Exported_Types
+ * @{
+ */
+
+/* SPI InitTypeDef */
+typedef struct
+{
+ FunctionalState DIRECTION; /* @arg: ENABLE MSB first transmission;
+ @arg: DISABLE LSB first transmission;
+ */
+ FunctionalState PHASE; /* @arg: ENABLE Posedge transmit data;
+ @arg: DISABLE Negedge transmit data;
+ */
+ FunctionalState POLARITY; /* @arg: ENABLE Initial polarity to 1
+ @arg: DISABLE Initial polarity to 0;
+ */
+ uint32_t CLKSEL; /* Clock Selection */
+
+}SPI_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Macros
+ * @{
+ */
+
+/* Clock Selection */
+#define CLKSEL_CLK_DIV_2 ((uint32_t) 0x00000000) //CLK/2
+#define CLKSEL_CLK_DIV_4 ((uint32_t) 0x00000001) //CLK/4
+#define CLKSEL_CLK_DIV_6 ((uint32_t) 0x00000003) //CLK/6
+#define CLKSEL_CLK_DIV_8 ((uint32_t) 0x00000004) //CLK/8
+
+/* Register Bit Position */
+#define SPI_CR_DIRECTION_Pos 0 /* CTRL register DIRECTION bit position */
+#define SPI_CR_PHASE_Pos 1 /* CTRL register PHASE bit position */
+#define SPI_CR_POLARITY_Pos 2 /* CTRL register POLARITY bit position */
+#define SPI_STATUS_ROE_Pos 2 /* STATUS register ROE bit position */
+#define SPI_STATUS_TOE_Pos 3 /* STATUS register TOE bit position */
+#define SPI_STATUS_TMT_Pos 4 /* STATUS register TMT bit position */
+#define SPI_STATUS_TRDY_Pos 5 /* STATUS register TRDY bit position */
+#define SPI_STATUS_RRDY_Pos 6 /* STATUS register RRDY bit position */
+#define SPI_STATUS_ERR_Pos 7 /* STATUS register ERR bit position */
+
+#define SPI_CR_CLKSEL_Pos ((uint32_t) 0x00000003) /* CTRL register CLKSEL Position */
+#define SPI_CR_CLKSEL_Mask ((uint32_t) 0x00000003) /* CTRL register CLKSEL mask */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Exported_Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes SPI
+ */
+extern void SPI_Init(SPI_InitTypeDef* SPI_InitStruct);
+
+/**
+ * @brief Sets Direction
+ */
+extern void SPI_SetDirection(void);
+
+/**
+ * @brief Clears Direction
+ */
+extern void SPI_ClrDirection(void);
+
+/**
+ * @brief Returns Direction
+ */
+extern uint32_t SPI_GetDirection(void);
+
+/**
+ * @brief Sets Phase
+ */
+extern void SPI_SetPhase(void);
+
+/**
+ * @brief Clears Phase
+ */
+extern void SPI_ClrPhase(void);
+
+/**
+ * @brief Returns Phase
+ */
+extern uint32_t SPI_GetPhase(void);
+
+/**
+ * @brief Returns Polarity
+ */
+extern uint32_t SPI_GetPolarity(void);
+
+/**
+ * @brief Clears Polarity
+ */
+extern void SPI_ClrPolarity(void);
+
+/**
+ * @brief Sets Polarity
+ */
+extern void SPI_SetPolarity(void);
+
+/**
+ * @brief Sets ClkSel
+ */
+extern void SPI_SetClkSel(uint32_t clksel);
+
+/**
+ * @brief Returns ClkSel
+ */
+extern uint32_t SPI_GetClkSel(void);
+
+/**
+ * @brief Reads transmit overrun error status
+ */
+extern FlagStatus SPI_GetToeStatus(void);
+
+/**
+ * @brief Reads receive overrun error status
+ */
+extern FlagStatus SPI_GetRoeStatus(void);
+
+/**
+ * @brief Reads transmitting status
+ */
+extern FlagStatus SPI_GetTmtStatus(void);
+
+/**
+ * @brief Reads transmit ready status
+ */
+extern FlagStatus SPI_GetTrdyStatus(void);
+
+/**
+ * @brief Reads receive ready status
+ */
+extern FlagStatus SPI_GetRrdyStatus(void);
+
+/**
+ * @brief Reads error status
+ */
+extern FlagStatus SPI_GetErrStatus(void);
+
+/**
+ * @brief Clears transmit overrun error status
+ */
+extern void SPI_ClrToeStatus(void);
+
+/**
+ * @brief Clear receive overrun error status
+ */
+extern void SPI_ClrRoeStatus(void);
+
+/**
+ * @brief Clears error status
+ */
+extern void SPI_ClrErrStatus(void);
+
+/**
+ * @brief Writes Data
+ */
+extern void SPI_WriteData(uint8_t data);
+
+/**
+ * @brief Reads Data
+ */
+extern uint8_t SPI_ReadData(void);
+
+/**
+ * @brief SPI_Slave Select
+ */
+extern void SPI_Select_Slave(uint32_t Slave_address);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GW1NS4C_SPI_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Includes/gw1ns4c_syscon.h b/PERIPHERAL/Includes/gw1ns4c_syscon.h
new file mode 100644
index 0000000..73621d4
--- /dev/null
+++ b/PERIPHERAL/Includes/gw1ns4c_syscon.h
@@ -0,0 +1,110 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_syscon.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the SYSCON firmware library.
+ ******************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GW1NS4C_SYSCON_H
+#define __GW1NS4C_SYSCON_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup SYSCON
+ * @{
+ */
+
+/** @defgroup SYSCON_Exported_Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCON_Exported_Macros
+ * @{
+ */
+
+#define SYSCON_RSTINFO_SYSRESETREQ_Pos 0 /* System Reset Request bit position */
+#define SYSCON_RSTINFO_WDOGRESETREQ_Pos 1 /* WatchDog Reset Requestt bit position */
+#define SYSCON_RSTINFO_LOCKUPRESET_Pos 2 /* Lockup Resett bit position */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCON_Exported_Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes SYSCON
+ */
+void SYSCON_Init(void);
+
+/**
+ * @brief Returns REMAP
+ */
+uint32_t SYSCON_GetRemap(void);
+
+/**
+ * @brief Returns PMUCTRL Enable
+ */
+uint32_t SYSCON_GetPmuctrlEnable(void);
+
+/**
+ * @brief Returns RESETOP LOCKUPRST
+ */
+uint32_t SYSCON_GetResetopLockuprst(void);
+
+/**
+ * @brief Returns RSTINFO SYSRESETREQ
+ */
+FlagStatus SYSCON_GetRstinfoSysresetreq(void);
+
+/**
+ * @brief Returns RSTINFO WDOGRESETREQ
+ */
+FlagStatus SYSCON_GetRstinfoWdogresetreq(void);
+
+/**
+ * @brief Returns RSTINFO LOCKRESET
+ */
+FlagStatus SYSCON_GetRstinfoLockreset(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GW1NS4C_SYSCON_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Includes/gw1ns4c_timer.h b/PERIPHERAL/Includes/gw1ns4c_timer.h
new file mode 100644
index 0000000..b77913a
--- /dev/null
+++ b/PERIPHERAL/Includes/gw1ns4c_timer.h
@@ -0,0 +1,165 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_timer.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the TIMER firmware library.
+ ******************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GW1NS4C_TIMER_H
+#define __GW1NS4C_TIMER_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup TIMER
+ * @{
+ */
+
+/** @defgroup TIMER_Exported_Types
+ * @{
+ */
+
+/* TIMER interrupt typedef */
+typedef FunctionalState TIMERInt_TypeDef; /* ENABLE/DISABLE */
+
+/* TIMER External input typedef */
+typedef enum
+{
+ TIMER_DISABLE = 0, /* External Disable */
+ TIMER_EXTI_EN, /* Select external input as enable */
+ TIMER_EXTI_CLK /* Select external input as clock */
+}TIMERExti_TypeDef;
+
+/**
+ * @brief TIMER Init Structure definition
+ */
+typedef struct
+{
+ uint32_t Reload; /* Reload value, sets the current value */
+
+ TIMERInt_TypeDef TIMER_Int; /* Timer interrupt */
+
+ TIMERExti_TypeDef TIMER_Exti; /* Select timer external input */
+
+}TIMER_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMER_Exported_Macros
+ * @{
+ */
+
+#define TIMER_CTRL_EN_Pos 0 /* TIMER CTRL: Enable Position */
+#define TIMER_CTRL_SELEXTEN_Pos 1 /* TIMER CTRL: External Enable Position */
+#define TIMER_CTRL_SELEXTCLK_Pos 2 /* TIMER CTRL: External Clock Position */
+#define TIMER_CTRL_IRQEN_Pos 3 /* TIMER CTRL: Interrupt Enable Position */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMER_Exported_Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes Timer module.
+ */
+extern void TIMER_Init(TIMER_TypeDef* TIMERx,TIMER_InitTypeDef* TIMER_InitStruct);
+
+/**
+ * @brief Starts Timer.
+ */
+extern void TIMER_StartTimer(TIMER_TypeDef* TIMERx);
+
+/**
+ * @brief Stops Timer.
+ */
+extern void TIMER_StopTimer(TIMER_TypeDef* TIMERx);
+
+/**
+ * @brief Returns timer IRQ status
+ */
+extern ITStatus TIMER_GetIRQStatus(TIMER_TypeDef* TIMERx);
+
+/**
+ * @brief Timer interrupt clear
+ */
+extern void TIMER_ClearIRQ(TIMER_TypeDef* TIMERx);
+
+/**
+ * @brief Returns Timer Reload value.
+ */
+extern uint32_t TIMER_GetReload(TIMER_TypeDef* TIMERx);
+
+/**
+ * @brief Sets Timer Reload value.
+ */
+extern void TIMER_SetReload(TIMER_TypeDef* TIMERx,uint32_t value);
+
+/**
+ * @brief Returns Timer current value.
+ */
+extern uint32_t TIMER_GetValue(TIMER_TypeDef* TIMERx);
+
+/**
+ * @brief Sets Timer current value.
+ */
+extern void TIMER_SetValue(TIMER_TypeDef* TIMERx,uint32_t value);
+
+/**
+ * @brief Enables Timer Interrupt requests.
+ */
+extern void TIMER_EnableIRQ(TIMER_TypeDef* TIMERx);
+
+/**
+ * @brief Disables Timer Interrupt requests.
+ */
+extern void TIMER_DisableIRQ(TIMER_TypeDef* TIMERx);
+
+/**
+ * @brief Select Ext input Enable.
+ */
+extern void TIMER_SelExtEnable(TIMER_TypeDef *TIMER);
+
+/**
+ * @brief Select Ext input Clock.
+ */
+extern void TIMER_SelExtClock(TIMER_TypeDef *TIMER);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GW1NS4C_TIMER_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Includes/gw1ns4c_uart.h b/PERIPHERAL/Includes/gw1ns4c_uart.h
new file mode 100644
index 0000000..f2a090b
--- /dev/null
+++ b/PERIPHERAL/Includes/gw1ns4c_uart.h
@@ -0,0 +1,243 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_uart.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the UART firmware library.
+ ******************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GW1NS4C_UART_H
+#define __GW1NS4C_UART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup UART
+ * @{
+ */
+
+/** @defgroup UART_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief UART mode typedef
+ */
+typedef struct
+{
+ FunctionalState UARTMode_Tx; /* TX Enable */
+ FunctionalState UARTMode_Rx; /* RX Enable */
+}UARTMode_TypeDef;
+
+/**
+ * @brief UART interrupt typedef
+ */
+typedef struct
+{
+ FunctionalState UARTInt_Tx; /* Tx Interrupt Enable */
+ FunctionalState UARTInt_Rx; /* Rx Interrupt Enable */
+}UARTInt_TypeDef;
+
+/**
+ * @brief UART overrun typedef
+ */
+typedef struct
+{
+ FunctionalState UARTOvr_Tx; /* Tx Overrun Interrupt Enable */
+ FunctionalState UARTOvr_Rx; /* Rx Overrun Interrupt Enable */
+}UARTOvr_TypeDef;
+
+/**
+ * @brief UART Initialization Structure definition
+ */
+typedef struct
+{
+ uint32_t UART_BaudRate; /* Baud Rate */
+
+ UARTMode_TypeDef UART_Mode; /* UART Mode */
+
+ UARTInt_TypeDef UART_Int; /* UART Interrupt */
+
+ UARTOvr_TypeDef UART_Ovr; /* UART Overrun */
+
+ FunctionalState UART_Hstm; /* UART High Speed Test Mode */
+
+}UART_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Macros
+ * @{
+ */
+
+#define UART_STATE_TXBF_Pos 0 /* UART STATE: TXBF Position */
+#define UART_STATE_RXBF_Pos 1 /* UART STATE: RXBF Position */
+#define UART_STATE_TXOR_Pos 2 /* UART STATE: TXOR Position */
+#define UART_STATE_RXOR_Pos 3 /* UART STATE: RXOR Position */
+
+#define UART_CTRL_TXEN_Pos 0 /* UART CTRL: TXEN Position */
+#define UART_CTRL_RXEN_Pos 1 /* UART CTRL: RXEN Position */
+#define UART_CTRL_TXIRQEN_Pos 2 /* UART CTRL: TXIRQEN Position */
+#define UART_CTRL_RXIRQEN_Pos 3 /* UART CTRL: RXIRQEN Position */
+#define UART_CTRL_TXORIRQEN_Pos 4 /* UART CTRL: TXORIRQEN Position */
+#define UART_CTRL_RXORIRQEN_Pos 5 /* UART CTRL: RXORIRQEN Position */
+#define UART_CTRL_HSTM_Pos 6 /* UART CTRL: HSTM Position */
+
+#define UART_INTSTATUS_TXIRQ_Pos 0 /* UART INTSTATUS: TXIRQ Position */
+#define UART_INTSTATUS_RXIRQ_Pos 1 /* UART INTSTATUS: RXIRQ Position */
+#define UART_INTSTATUS_TXORIRQ_Pos 2 /* UART INTSTATUS: TXORIRQ Position */
+#define UART_INTSTATUS_RXORIRQ_Pos 3 /* UART INTSTATUS: RXORIRQ Position */
+
+#define UART_INTCLEAR_TXIRQ_Pos 0 /* UART INTCLEAR: TXIRQ Position */
+#define UART_INTCLEAR_RXIRQ_Pos 1 /* UART INTCLEAR: RXIRQ Position */
+#define UART_INTCLEAR_TXORIRQ_Pos 2 /* UART INTCLEAR: TXORIRQ Position */
+#define UART_INTCLEAR_RXORIRQ_Pos 3 /* UART INTCLEAR: RXORIRQ Position */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Exported_Functions
+ * @{
+ */
+
+/**
+ * @brief Initializes UART module.
+ */
+extern ErrorStatus UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct);
+
+/**
+ * @brief Returns whether the UART RX Buffer is Full.
+ */
+extern FlagStatus UART_GetRxBufferFull(UART_TypeDef* UARTx);
+
+/**
+ * @brief Returns whether the UART TX Buffer is Full.
+ */
+extern FlagStatus UART_GetTxBufferFull(UART_TypeDef* UARTx);
+
+/**
+ * @brief Returns whether the UART RX Buffer is Overrun.
+ */
+extern FlagStatus UART_GetRxBufferOverrunStatus(UART_TypeDef* UARTx);
+
+/**
+ * @brief Returns whether the UART TX Buffer is Overrun.
+ */
+extern FlagStatus UART_GetTxBufferOverrunStatus(UART_TypeDef* UARTx);
+
+/**
+ * @brief Clears RxBuffer overrun status.
+ */
+extern void UART_ClearRxBufferOverrunStatus(UART_TypeDef* UARTx);
+
+/**
+ * @brief Clears TxBuffer overrun status.
+ */
+extern void UART_ClearTxBufferOverrunStatus(UART_TypeDef* UARTx);
+
+/**
+ * @brief Sends a character to the UART TX Buffer.
+ */
+extern void UART_SendChar(UART_TypeDef* UARTx, char txchar);
+
+/**
+ * @brief Sends a string to the UART TX Buffer.
+ */
+extern void UART_SendString(UART_TypeDef* UARTx, char *str);
+
+/**
+ * @brief Receives a character from the UART RX Buffer.
+ */
+extern char UART_ReceiveChar(UART_TypeDef* UARTx);
+
+/**
+ * @brief Returns UART Baud rate Divider value.
+ */
+extern uint32_t UART_GetBaudDivider(UART_TypeDef* UARTx);
+
+/**
+ * @brief Return UART TX Interrupt Status.
+ */
+extern ITStatus UART_GetTxIRQStatus(UART_TypeDef* UARTx);
+
+/**
+ * @brief Return UART RX Interrupt Status.
+ */
+extern ITStatus UART_GetRxIRQStatus(UART_TypeDef* UARTx);
+
+/**
+ * @brief Clear UART TX Interrupt request.
+ */
+extern void UART_ClearTxIRQ(UART_TypeDef* UART);
+
+/**
+ * @brief Clear UART RX Interrupt request.
+ */
+extern void UART_ClearRxIRQ(UART_TypeDef* UART);
+
+/**
+ * @brief Return UART TX Overrun Interrupt Status.
+ */
+extern ITStatus UART_GetTxOverrunIRQStatus(UART_TypeDef* UARTx);
+
+/**
+ * @brief Return UART RX Overrun Interrupt Status.
+ */
+extern ITStatus UART_GetRxOverrunIRQStatus(UART_TypeDef* UARTx);
+
+/**
+ * @brief Clear UART TX Overrun Interrupt request.
+ */
+extern void UART_ClearTxOverrunIRQ(UART_TypeDef* UARTx);
+
+/**
+ * @brief Clear UART RX Overrun Interrupt request.
+ */
+extern void UART_ClearRxOverrunIRQ(UART_TypeDef* UARTx);
+
+/**
+ * @brief Sets Tx High Speed Test Mode
+ */
+extern void UART_SetHSTM(UART_TypeDef* UARTx);
+
+/**
+ * @brief Clears Tx High Speed Test Mode
+ */
+extern void UART_ClrHSTM(UART_TypeDef* UARTx);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GW1NS4C_UART_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Includes/gw1ns4c_wdog.h b/PERIPHERAL/Includes/gw1ns4c_wdog.h
new file mode 100644
index 0000000..ce62c89
--- /dev/null
+++ b/PERIPHERAL/Includes/gw1ns4c_wdog.h
@@ -0,0 +1,212 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_wdog.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the WatchDog firmware library.
+ ******************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GW1NS4C_WDOG_H
+#define __GW1NS4C_WDOG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup WatchDog
+ * @{
+ */
+
+/** @defgroup WDOG_Exported_Types
+ * @{
+ */
+
+/**
+ * @brief WatchDog Lock TypeDef.
+ */
+typedef FunctionalState WDOGLock_TypeDef;
+
+/**
+ * @brief WatchDog Interrupt TypeDef.
+ */
+typedef FunctionalState WDOGInt_TypeDef;
+
+/**
+ * @brief WatchDog Reset TypeDef.
+ */
+typedef FunctionalState WDOGRes_TypeDef;
+
+/**
+ * @brief WatchDog Integration Test Mode TypeDef.
+ */
+typedef FunctionalState WDOGMode_Typedef;
+
+/**
+ * @brief WatchDog Initialization TypeDef.
+ */
+typedef struct
+{
+ uint32_t WDOG_Reload; /* WatchDog Reload value */
+
+ WDOGLock_TypeDef WDOG_Lock; /* WatchDog Lock register write access */
+
+ WDOGInt_TypeDef WDOG_Int; /* WatchDog Interrupt enable flag */
+
+ WDOGRes_TypeDef WDOG_Res; /* WatchDog Reset enable flag */
+
+ WDOGMode_Typedef WDOG_ITMode; /* WatchDog Integration Test Mode enable flag */
+
+}WDOG_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup WDOG_Exported_Macros
+ * @{
+ */
+
+#define WDOG_LOCK_EN_Pos 1 /*[31:1] write register access enable */
+#define WDOG_CTRL_INTEN_Pos 0 /* CTRL register INTEN bit position */
+#define WDOG_CTRL_RESEN_Pos 1 /* CTRL register RESEN bit position */
+#define WDOG_RAWINTSTAT_Pos 0 /* Raw Interrupt Status bit position */
+#define WDOG_MASKINTSTAT_Pos 0 /* Masked Interrupt Status bit position */
+#define WDOG_ITCR_INTEGTESTEN_Pos 0 /* Integration Test Mode bit position */
+#define WDOG_ITOP_WDOGRES_Pos 0 /* ITOP WDOGRES bit position */
+#define WDOG_ITOP_WDOGINT_Pos 1 /* ITOP WDOGINT bit position */
+
+/**
+ * @}
+ */
+
+/** @defgroup WDOG_Exported_Functions
+ * @{
+ */
+
+/**
+ * @brief WatchDog initialization.
+ */
+extern ErrorStatus WDOG_Init(WDOG_InitTypeDef* WDOG_InitStruct);
+
+/**
+ * @brief Restart watchdog counter.
+ */
+extern void WDOG_RestartCounter(uint32_t reload);
+
+/**
+ * @brief Returns counter value.
+ */
+extern uint32_t WDOG_GetCounterValue(void);
+
+/**
+ * @brief Sets reset enable.
+ */
+extern void WDOG_SetResetEnable(void);
+
+/**
+ * @brief Returns reset status.
+ */
+extern FlagStatus WDOG_GetResStatus(void);
+
+/**
+ * @brief Sets interrupt enable.
+ */
+extern void WDOG_SetIntEnable(void);
+
+/**
+ * @brief Returns interrupt status.
+ */
+extern FlagStatus WDOG_GetIntStatus(void);
+
+/**
+ * @brief Clears interrupt enable.
+ */
+extern void WDOG_ClrIntEnable(void);
+
+/**
+ * @brief Returns raw interrupt status.
+ */
+extern FlagStatus WDOG_GetRawIntStatus(void);
+
+/**
+ * @brief Returns masked interrupt status.
+ */
+extern FlagStatus WDOG_GetMaskIntStatus(void);
+
+/**
+ * @brief Disable write access all registers.
+ */
+extern void WDOG_LockWriteAccess(void);
+
+/**
+ * @brief Enable write access all registers.
+ */
+extern void WDOG_UnlockWriteAccess(void);
+
+/**
+ * @brief Sets integration test mode enable.
+ */
+extern void WDOG_SetITModeEnable(void);
+
+/**
+ * @brief Clears integration test mode enable.
+ */
+extern void WDOG_ClrITModeEnable(void);
+
+/**
+ * @brief Returns integration test mode status.
+ */
+extern FlagStatus WDOG_GetITModeStatus(void);
+
+/**
+ * @brief Sets integration test output WDOGINT or WDOGRES.
+ */
+extern void WDOG_SetITOP(uint32_t itop);
+
+/**
+ * @brief Returns integration test output WDOGRES status.
+ */
+extern FlagStatus WDOG_GetITOPResStatus(void);
+
+/**
+ * @brief Returns integration test output WDOGINT status.
+ */
+extern FlagStatus WDOG_GetITOPIntStatus(void);
+
+/**
+ * @brief Clear integration test output WDOGINT or WDOGRES.
+ */
+extern void WDOG_ClrITOP(uint32_t itop);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GW1NS4C_WDOG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Sources/gw1ns4c_gpio.c b/PERIPHERAL/Sources/gw1ns4c_gpio.c
new file mode 100644
index 0000000..fe8aead
--- /dev/null
+++ b/PERIPHERAL/Sources/gw1ns4c_gpio.c
@@ -0,0 +1,387 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_gpio.c
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the GPIO firmware library.
+ ******************************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c_gpio.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+/** @defgroup GPIO_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Private_Functions
+ * @{
+ */
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param GPIO_InitTypeDef Pointer
+ * @return none
+ * @brief Initials GPIO.
+ */
+void GPIO_Init(GPIO_TypeDef* GPIOx,GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ uint32_t pos = 0;
+ uint32_t GPIO_Pin = GPIO_InitStruct->GPIO_Pin;
+ GPIOMode_TypeDef GPIO_Mode = GPIO_InitStruct->GPIO_Mode;
+ GPIOInt_TypeDef GPIO_Int = GPIO_InitStruct->GPIO_Int;
+
+ /* Initial all register to zero */
+ GPIOx->DATA = 0;
+ GPIOx->DATAOUT = 0;
+ GPIOx->OUTENSET = 0;
+ GPIOx->OUTENCLR = 0;
+ GPIOx->ALTFUNCSET = 0;
+ GPIOx->ALTFUNCCLR = 0;
+ GPIOx->INTENSET = 0;
+ GPIOx->INTENCLR = 0;
+ GPIOx->INTTYPESET = 0;
+ GPIOx->INTTYPECLR = 0;
+ GPIOx->INTPOLSET = 0;
+ GPIOx->INTPOLCLR = 0;
+ GPIOx->INTCLEAR = 0;
+ for(pos = 0;pos < 256;pos++)
+ {
+ GPIOx->MASKLOWBYTE[pos] = 0;
+ GPIOx->MASKHIGHBYTE[pos] = 0;
+ }
+
+ /* Set GPIO Mode registers */
+ if(GPIO_Mode == GPIO_Mode_IN)
+ {
+ GPIOx->OUTENSET &= (~GPIO_Pin);//Clear Out Enable
+ }
+ else if(GPIO_Mode == GPIO_Mode_OUT)
+ {
+ GPIOx->OUTENSET |= GPIO_Pin;//Set Out Enable
+ }
+ else if(GPIO_Mode == GPIO_Mode_AF)
+ {
+ GPIOx->ALTFUNCSET |= GPIO_Pin;
+ }
+
+ /* Set GPIO Interrupt registers */
+ if(GPIO_Int == GPIO_Int_Low_Level)
+ {
+ GPIOx->INTENSET |= GPIO_Pin;
+ GPIOx->INTTYPECLR |= GPIO_Pin;
+ GPIOx->INTPOLCLR |= GPIO_Pin;
+ }
+ else if(GPIO_Int == GPIO_Int_High_Level)
+ {
+ GPIOx->INTENSET |= GPIO_Pin;
+ GPIOx->INTTYPECLR |= GPIO_Pin;
+ GPIOx->INTPOLSET |= GPIO_Pin;
+ }
+ else if(GPIO_Int == GPIO_Int_Falling_Edge)
+ {
+ GPIOx->INTENSET |= GPIO_Pin;
+ GPIOx->INTTYPESET |= GPIO_Pin;
+ GPIOx->INTPOLCLR |= GPIO_Pin;
+ }
+ else if(GPIO_Int == GPIO_Int_Rising_Edge)
+ {
+ GPIOx->INTENSET |= GPIO_Pin;
+ GPIOx->INTPOLSET |= GPIO_Pin;
+ GPIOx->INTTYPESET |= GPIO_Pin;
+ }
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param uint32_t GPIO Pin
+ * @arg GPIO_Pin_0...GPIO_Pin_15
+ * @return none
+ * @brief Sets pins on a port as an output.
+ * Set the bit corresponding to the pin number to 1 for output.
+ * Set bit 1 of outenset to 1 to set pin 1 as an output.
+ * This function is thread safe.
+ */
+void GPIO_SetOutEnable(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->OUTENSET |= GPIO_Pin;
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param uint32_t GPIO Pin
+ * @arg GPIO_Pin_0...GPIO_Pin_15
+ * @return none
+ * @brief Sets pins on a port as an input.
+ * Set the bit corresponding to the pin number to 1 for input.
+ * Set bit 1 of outenclr to 1 to set pin 1 as an input.
+ * This function is thread safe.
+ */
+void GPIO_ClrOutEnable(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->OUTENCLR = GPIO_Pin;
+}
+
+/**
+ * @brief Set GPIO Output = "1"
+ */
+void GPIO_SetBit(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->DATAOUT |= GPIO_Pin;
+}
+
+/**
+ * @brief Set GPIO Output = "0"
+ */
+void GPIO_ResetBit(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->DATAOUT &= ~GPIO_Pin;
+}
+
+/**
+ * @brief Write GPIO Output
+ */
+void GPIO_WriteBits(GPIO_TypeDef* GPIOx,uint32_t value)
+{
+ GPIOx->DATAOUT = value;
+}
+
+/**
+ * @brief Read GPIO Input
+ */
+uint32_t GPIO_ReadBits(GPIO_TypeDef* GPIOx)
+{
+ return GPIOx->DATA;
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @return Output status
+ * @brief Returns whether pins on a port are set as inputs or outputs.
+ * If bit 1 of the returned is 1,this is an output.
+ */
+uint32_t GPIO_GetOutEnable(GPIO_TypeDef* GPIOx)
+{
+ return GPIOx->OUTENSET;
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param uint32_t GPIO Pin
+ * @arg GPIO_Pin_0...GPIO_Pin_15
+ * @return none
+ * @brief Enables the alternative function for pins.
+ * Set the bit corresponding to the pin number to 1 for alternate function.
+ * Set bit 1 of ALtFunc to 1 to set pin 1 to its alternative function.
+ * This function is thread safe.
+ */
+void GPIO_SetAltFunc(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->ALTFUNCSET |= GPIO_Pin;
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param uint32_t GPIO Pin
+ * @arg GPIO_Pin_0...GPIO_Pin_15
+ * @return none
+ * @brief Disables the alternative function for pins.
+ * Set the bit corresponding to the pin number to 1 to disable alternate function.
+ * Set bit 1 of ALtFunc to 1 to set pin 1 to the orignal output function.
+ * This function is thread safe.
+ */
+void GPIO_ClrAltFunc(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->ALTFUNCCLR = GPIO_Pin;
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @return AltFunc status
+ * @brief Returns whether pins on a port are set to their alternative or their original output functionality.
+ * If bit 1 of the returned is 1,this is alternative function.
+ */
+uint32_t GPIO_GetAltFunc(GPIO_TypeDef* GPIOx)
+{
+ return GPIOx->ALTFUNCSET;
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param uint32_t GPIO Pin
+ * @arg GPIO_Pin_0...GPIO_Pin_15
+ * @return none
+ * @brief Clears the interrupt flag for the specified pin.
+ */
+void GPIO_IntClear(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->INTCLEAR |= GPIO_Pin;
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @return Interrupt status
+ * @brief Returns GPIO Interrupt request status.
+ */
+uint32_t GPIO_GetIntStatus(GPIO_TypeDef* GPIOx)
+{
+ return GPIOx->INTSTATUS;
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param uint32_t GPIO Pin
+ * @arg GPIO_Pin_0...GPIO_Pin_15
+ * @return Interrupt enable set
+ * @brief Enables interrupts for the specified pin.
+ * Returns the new interrupt enable status of the pin.
+ * This function is thread safe.
+ */
+uint32_t GPIO_SetIntEnable(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->INTENSET |= GPIO_Pin;
+ return GPIOx->INTENSET;
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param GPIO Pin
+ * @arg GPIO_Pin_0...GPIO_Pin_15
+ * @return Interrupt enable clear
+ * @brief Disables interrupts for the specified pin.
+ * Returns the new interrupt enable status of the pin.
+ * This function is thread safe.
+ */
+uint32_t GPIO_ClrIntEnable(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->INTENCLR |= GPIO_Pin;
+ return GPIOx->INTENCLR;
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param GPIO Pin
+ * @arg GPIO_Pin_0...GPIO_Pin_15
+ * @return none
+ * @brief Changes the interrupt type for the specified pin to a high level interrupt.
+ * This function is thread safe.
+ */
+void GPIO_SetIntHighLevel(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->INTENSET |= GPIO_Pin; /* Set INT Enable bit */
+ GPIOx->INTTYPECLR |= GPIO_Pin; /* Clear INT TYPE bit */
+ GPIOx->INTPOLSET |= GPIO_Pin; /* Set INT POLarity bit */
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param GPIO Pin
+ * @arg GPIO_Pin_0...GPIO_Pin_15
+ * @return none
+ * @brief Changes the interrupt type for the specified pin to a rising edge interrupt.
+ * This function is thread safe.
+ */
+void GPIO_SetIntRisingEdge(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->INTENSET |= GPIO_Pin; /* Set INT Enable bit */
+ GPIOx->INTTYPESET |= GPIO_Pin; /* Set INT TYPE bit */
+ GPIOx->INTPOLSET |= GPIO_Pin; /* Set INT POLarity bit */
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param GPIO Pin
+ * @arg GPIO_Pin_0...GPIO_Pin_15
+ * @return none
+ * @brief Changes the interrupt type for the specified pin to a low level interrupt.
+ * This function is thread safe.
+ */
+void GPIO_SetIntLowLevel(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->INTENSET |= GPIO_Pin; /* Set INT Enable bit */
+ GPIOx->INTTYPECLR |= GPIO_Pin; /* Clear INT TYPE bit */
+ GPIOx->INTPOLCLR |= GPIO_Pin; /* Clear INT POLarity bit */
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param GPIO Pin
+ * @arg GPIO_Pin_0...GPIO_Pin_15
+ * @return none
+ * @brief Changes the interrupt type for the specified pin to a falling edge interrupt.
+ * This function is thread safe.
+ */
+void GPIO_SetIntFallingEdge(GPIO_TypeDef* GPIOx,uint32_t GPIO_Pin)
+{
+ GPIOx->INTENSET |= GPIO_Pin; /* Set INT Enable bit */
+ GPIOx->INTTYPESET |= GPIO_Pin; /* Set INT TYPE bit */
+ GPIOx->INTPOLCLR |= GPIO_Pin; /* Clear INT POLarity bit */
+}
+
+/**
+ * @param GPIO_TypeDef Pointer
+ * @param uint32_t mask The output port mask.
+ * @param uint32_t value The value to output to the specified port.
+ * @return none
+ * @brief Outputs the specified value on the desired port using the user defined mask to perform Masked access.
+ */
+void GPIO_MaskedWrite(GPIO_TypeDef* GPIOx,uint32_t value,uint32_t mask)
+{
+ GPIOx->MASKLOWBYTE[0x00FF & mask] = value;
+ GPIOx->MASKHIGHBYTE[((0xFF00 & mask) >> 8)] = value;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Sources/gw1ns4c_i2c.c b/PERIPHERAL/Sources/gw1ns4c_i2c.c
new file mode 100644
index 0000000..8e553fc
--- /dev/null
+++ b/PERIPHERAL/Sources/gw1ns4c_i2c.c
@@ -0,0 +1,297 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_i2c.c
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the I2C firmware library.
+ ******************************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c_i2c.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/**
+ * @param i2c is I2C Master address
+ * @return none
+ * @brief Close the I2C Core
+ */
+void I2C_UnEnable(I2C_TypeDef * i2c)
+{
+ i2c->CTR = ~I2C_CTR_EN;
+}
+
+/**
+ * @param i2c is I2C Master address
+ * @return none
+ * @brief Enable the I2C Core
+ */
+void I2C_Enable(I2C_TypeDef * i2c)
+{
+ i2c->CTR |= I2C_CTR_EN;
+}
+
+/**
+ * @param The Rate of the I2C Range
+ * @param i2c is I2C Master address
+ * @return ErrorStatus indicate the State of the Init program
+ * @brief Initialize I2C.
+ */
+uint16_t I2C_Rate_Set(I2C_TypeDef * i2c,uint16_t Rate)
+{
+ uint16_t prescal = 0;
+
+ prescal = (uint32_t) (SystemCoreClock/(5000*Rate)-1);
+ i2c->PRER = (prescal&I2C_CTR_PERE);
+
+ return prescal;
+}
+
+/**
+ * @param the ms will be delay
+ * @return none
+ * @brief Delay .
+ */
+void Delay_ms_i2c(__IO uint32_t delay_ms)
+{
+ for(delay_ms=delay_ms*(SystemCoreClock>>13); delay_ms != 0; delay_ms--);
+}
+
+/**
+ * @param none
+ * @param i2c is I2C Master address
+ * @return ErrorStatus indicate the State of the Init program
+ * @brief Initialize I2C.
+ */
+ErrorStatus I2C_Init(I2C_TypeDef * i2c, uint16_t Rate)
+{
+ uint16_t temp_save;
+
+ I2C_Enable(i2c);
+ temp_save=I2C_Rate_Set(i2c,Rate);
+
+ if((i2c->CTR&I2C_CTR_EN)&&(i2c->PRER == (uint32_t) (temp_save&I2C_CTR_PERE)))
+ {
+ return SUCCESS;
+ }
+ else
+ {
+ return ERROR;
+ }
+}
+
+/**
+ * @param none
+ * @param i2c is I2C Master address
+ * @param slv_address is slave peripheral address
+ * @param data_address is the address which we will send data
+ * @param data is a byte data
+ * @return none
+ * @brief Send byte to I2C serial bus
+ */
+void I2C_SendByte(I2C_TypeDef *i2c ,uint8_t slv_address,uint8_t data_address,uint8_t data)
+{
+ i2c->TXR = (slv_address <<1) |0;
+ i2c->CR = I2C_CMD_STA|I2C_CMD_WR;
+ while(i2c->SR&I2C_SR_TIP);//wait TIP
+ while(i2c->SR&I2C_SR_RXACK);//wait ack-----Over Here
+
+ i2c->TXR = data_address;
+ i2c->CR = (I2C_CMD_WR);
+ while(i2c->SR&I2C_SR_TIP);//wait TIP
+ while(i2c->SR&I2C_SR_RXACK);//wait ack
+
+ i2c->TXR = data;
+ i2c->CR = (I2C_CMD_STO|I2C_CMD_WR);
+ while(i2c->SR&I2C_SR_TIP);//wait TIP
+ while(i2c->SR&I2C_SR_RXACK);//wait ack
+ while(i2c->SR&I2C_SR_BUSY);
+
+ Delay_ms_i2c(3);//Wait the data to I2C Ready
+}
+
+/**
+ * @param none
+ * @param i2c is I2C Master address
+ * @param slv_addr is slave peripheral address
+ * @param data is several bytes data
+ * @param data_size is byte number
+ * @return none
+ * @brief Send several bytes a time to I2C serial bus
+ */
+void I2C_SendData(I2C_TypeDef *i2c ,uint8_t slv_addr,uint8_t data_addr,uint8_t* data,uint32_t data_size)
+{
+ uint32_t i;
+
+ i2c->TXR = (slv_addr <<1) |0;
+ i2c->CR = I2C_CMD_STA|I2C_CMD_WR;
+ while(i2c->SR&I2C_SR_TIP);//wait TIP
+ while(i2c->SR&I2C_SR_RXACK);//wait ack-----Over Here
+
+ i2c->TXR = data_addr;
+ i2c->CR = (I2C_CMD_WR);
+ while(i2c->SR&I2C_SR_TIP);//wait TIP
+ while(i2c->SR&I2C_SR_RXACK);//wait ack
+
+ for(i=0;iTXR = data[i];
+ if((data_size-1) == i)
+ {
+ i2c->CR = (I2C_CMD_STO|I2C_CMD_WR);
+ }
+ else
+ {
+ i2c->CR = (I2C_CMD_WR);
+ }
+
+ while(i2c->SR&I2C_SR_TIP);//wait TIP
+ while(i2c->SR&I2C_SR_RXACK);//wait ack
+ }
+
+ while(i2c->SR&I2C_SR_BUSY);
+ Delay_ms_i2c(3);//Wait the data to I2C Ready
+}
+
+/**
+ * @param i2c is I2C Master address
+ * @param slv_addr is I2C slave address
+ * @param data_addr is The data which we will read address
+ * @return uint8_t receives character
+ * @brief Receives 8-bits data from the serial bus.
+ */
+uint8_t I2C_ReceiveByte(I2C_TypeDef *i2c ,uint8_t slv_addr,uint8_t data_addr)
+{
+ uint8_t data=0;
+
+ i2c->TXR = (slv_addr <<1) |0;
+ i2c->CR = I2C_CMD_STA|I2C_CMD_WR;
+ while(i2c->SR&I2C_SR_TIP);
+ while(i2c->SR&I2C_SR_RXACK);//wait ack-----Over Here
+
+ i2c->TXR = data_addr;
+ i2c->CR = I2C_CMD_WR;//stop
+ while(i2c->SR&I2C_SR_TIP);//wait TIP
+ while(i2c->SR&I2C_SR_RXACK);//wait ack
+
+ i2c->TXR = (slv_addr <<1) |1;
+ i2c->CR = (I2C_CMD_STA|I2C_CMD_WR);
+ while(i2c->SR&I2C_SR_TIP);
+ while(i2c->SR&I2C_SR_RXACK);//wait ack
+
+ i2c->CR = (I2C_CMD_ACK|I2C_CMD_STO|I2C_CMD_RD);//send nack
+ while(i2c->SR&I2C_SR_TIP);
+ data = i2c->RXR;
+ Delay_ms_i2c(3);
+
+ return data;
+}
+
+/**
+ * @param i2c is I2C Master address
+ * @param slv_addr is I2C slave address
+ * @param data_addr is The data which we will read address
+ * @param data_size is received data number
+ * @param data is what we receive several bytes data
+ * @brief Receives several bytes data a time from the serial bus.
+ */
+void I2C_ReceiveData(I2C_TypeDef *i2c ,uint8_t slv_addr,uint8_t data_addr,uint8_t *data,uint32_t data_size)
+{
+ uint32_t i;
+
+ i2c->TXR = (slv_addr <<1) |0;
+ i2c->CR = I2C_CMD_STA|I2C_CMD_WR;
+ while(i2c->SR&I2C_SR_TIP);
+ while(i2c->SR&I2C_SR_RXACK);//wait ack-----Over Here
+
+ i2c->TXR = data_addr;
+ i2c->CR = I2C_CMD_WR;//stop
+ while(i2c->SR&I2C_SR_TIP);//wait TIP
+ while(i2c->SR&I2C_SR_RXACK);//wait ack
+
+ i2c->TXR = (slv_addr <<1) |1;
+ i2c->CR = (I2C_CMD_STA|I2C_CMD_WR);
+ while(i2c->SR&I2C_SR_TIP);
+ while(i2c->SR&I2C_SR_RXACK);//wait ack
+
+ for(i=0;iCR = (I2C_CMD_ACK|I2C_CMD_STO|I2C_CMD_RD);//send nack
+ }
+ else
+ {
+ i2c->CR = (~I2C_CMD_ACK&I2C_CMD_RD);//send ack
+ }
+
+ while(i2c->SR&I2C_SR_TIP);
+ data[i] = i2c->RXR;
+ }
+
+ while(i2c->SR&I2C_SR_BUSY);
+}
+
+/**
+ * @param i2c is I2C Master address
+ * @param slv_addr is I2C slave address
+ * @param data_start_address is The first data address
+ * @param data is the buff of the send bytes
+ * @return No returns
+ * @brief Send the data to the serial bus.
+ */
+void I2C_SendBytes(I2C_TypeDef *i2c ,uint8_t slv_address,uint8_t data_start_address,uint8_t *data,int32_t data_num)
+{
+ int32_t i;
+
+ for(i=0;iCTR = I2C_CTR_IEN | i2c->CTR;
+}
+
+/**
+ * @param I2Cx is I2C Master address
+ * @brief close the i2C Interrupt.
+ */
+void I2C_InterruptClose(I2C_TypeDef *i2c)
+{
+ i2c->CTR &= ~I2C_CTR_IEN;
+}
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Sources/gw1ns4c_misc.c b/PERIPHERAL/Sources/gw1ns4c_misc.c
new file mode 100644
index 0000000..3f30559
--- /dev/null
+++ b/PERIPHERAL/Sources/gw1ns4c_misc.c
@@ -0,0 +1,153 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_misc.c
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the miscellaneous firmware library.
+ ******************************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c_misc.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/** @defgroup MISC_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Macros
+ * @{
+ */
+
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @param the priority grouping bits length
+ * This parameter can be one of the following value:
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+ * 3 bits for subpriority
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+ * 2 bits for subpriority
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+ * 1 bits for subpriority
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+ * 0 bits for subpriority
+ * @return none
+ * @brief Sets interrupt priority groups.
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @param NVIC_InitTypeDef Pointer
+ * @return none
+ * @brief Initial interrupt priority.
+ */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+ uint32_t tmppriority=0x00,tmppre=0x00,tmpsub=0x0F;
+
+ if(NVIC_InitStruct->NVIC_IRQChannelCmd!=DISABLE)
+ {
+ /* Compute the corresponding IRQ priority */
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels */
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels */
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+/**
+ * @param NVIC_VecTabb Ram or Flash Memory
+ * @arg NVIC_VecTab_RAM
+ * @arg NVIC_VecTab_FLASH
+ * @param uint32_t Offset vector table base offset field
+ * @return none
+ * @brief Sets interrupt vector table.
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VecTab,uint32_t Offset)
+{
+ SCB->VTOR = NVIC_VecTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @param uint32_t the SysTick clock source
+ * @return none
+ * @brief Sets systick clock source.
+ */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Sources/gw1ns4c_rtc.c b/PERIPHERAL/Sources/gw1ns4c_rtc.c
new file mode 100644
index 0000000..55f89f5
--- /dev/null
+++ b/PERIPHERAL/Sources/gw1ns4c_rtc.c
@@ -0,0 +1,87 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_rtc.c
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the RTC firmware library.
+ ******************************************************************************************
+ */
+
+ /* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c_rtc.h"
+
+//THE CLOCK OF RTC is 1HZ
+uint32_t Get_Current_Value(void)
+{
+ return RTC->RTC_CURRENT_DATA;
+}
+
+void Set_Match_Value(uint32_t match_value)
+{
+ RTC->RTC_MATCH_VALUE =match_value;
+}
+
+uint32_t Get_Match_Value(void)
+{
+ return RTC->RTC_MATCH_VALUE;
+}
+
+void Set_Load_Value(uint32_t load_value)
+{
+ RTC->RTC_LOAD_VALUE = load_value;
+}
+
+uint32_t Get_Load_Value(void)
+{
+ return RTC->RTC_LOAD_VALUE;
+}
+
+void Start_RTC(void)
+{
+ RTC->RTC_CTROLLER_REG =0x01;
+}
+
+void Close_RTC(void)
+{
+ RTC->RTC_CTROLLER_REG =0x00;
+}
+
+uint8_t Get_RTC_Control_value(void)
+{
+ return RTC->RTC_CTROLLER_REG;
+}
+
+void RTC_Inter_Mask_Set(void)
+{
+ RTC->RTC_IMSC = 0x01;
+}
+
+void RTC_Inter_Mask_Clr(void)//MASK Interrupt FLAG
+{
+ RTC->RTC_IMSC = 0x00;
+}
+
+uint8_t Get_RTC_Inter_Mask_value(void)
+{
+ return RTC->RTC_IMSC;
+}
+
+void Clear_RTC_interrupt(void)
+{
+ RTC->RTC_INTR_CLEAR = 0x01;
+}
+
+void RTC_init(void)
+{
+ Set_Match_Value(30);//Match 30
+ Set_Load_Value(0);//0 Statr
+ RTC_Inter_Mask_Set();
+ //RTC_Inter_Mask_Clr();
+ Start_RTC();
+}
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Sources/gw1ns4c_spi.c b/PERIPHERAL/Sources/gw1ns4c_spi.c
new file mode 100644
index 0000000..68a64d4
--- /dev/null
+++ b/PERIPHERAL/Sources/gw1ns4c_spi.c
@@ -0,0 +1,338 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_spi.c
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the SPI firmware library.
+ ******************************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c_spi.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SPI
+ * @brief SPI driver modules
+ * @{
+ */
+
+/** @defgroup SPI_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SPI_Private_Functions
+ * @{
+ */
+
+/**
+ * @param SPI_InitTypeDef Pointer
+ * @return none
+ * @brief Initializes SPI
+ */
+void SPI_Init(SPI_InitTypeDef* SPI_InitStruct)
+{
+ uint32_t new_ctrl = 0;
+
+ SPI->CTRL = 0;
+ SPI->STATUS = 0;
+
+ /* Set Direction */
+ if(SPI_InitStruct->DIRECTION == ENABLE)
+ {
+ new_ctrl |= SPI_CR_DIRECTION;
+ }
+
+ /*Set Phase*/
+ if(SPI_InitStruct->PHASE == ENABLE)
+ {
+ new_ctrl |= SPI_CR_PHASE;
+ }
+
+ /*Set Polarity*/
+ if(SPI_InitStruct->POLARITY == ENABLE)
+ {
+ new_ctrl |= SPI_CR_POLARITY;
+ }
+
+ /*Set ClkSel*/
+ new_ctrl |= (SPI_InitStruct->CLKSEL << SPI_CR_CLKSEL_Pos);
+
+ SPI->CTRL = new_ctrl;
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Sets Direction
+ */
+void SPI_SetDirection(void)
+{
+ SPI->CTRL |= SPI_CR_DIRECTION;
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Clears Direction
+ */
+void SPI_ClrDirection(void)
+{
+ SPI->CTRL &= ~SPI_CR_DIRECTION;
+}
+
+/**
+ * @param none
+ * @return uint32_t
+ * @brief Returns Direction
+ */
+uint32_t SPI_GetDirection(void)
+{
+ return ((SPI->CTRL&SPI_CR_DIRECTION)==SPI_CR_DIRECTION);
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Sets Phase
+ */
+void SPI_SetPhase(void)
+{
+ SPI->CTRL |= SPI_CR_PHASE;
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Clears Phase
+ */
+void SPI_ClrPhase(void)
+{
+ SPI->CTRL &= ~SPI_CR_PHASE;
+}
+/**
+ * @param none
+ * @return uint32_t
+ * @brief Returns Phase
+ */
+uint32_t SPI_GetPhase(void)
+{
+ return ((SPI->CTRL&SPI_CR_PHASE)==SPI_CR_PHASE);
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Sets Polarity
+ */
+void SPI_SetPolarity(void)
+{
+ SPI->CTRL |= SPI_CR_POLARITY;
+}
+/**
+ * @param none
+ * @return none
+ * @brief Clears Polarity
+ */
+void SPI_ClrPolarity(void)
+{
+ SPI->CTRL &= ~SPI_CR_POLARITY;
+}
+
+/**
+ * @param none
+ * @return uint32_t
+ * @brief Returns Polarity
+ */
+uint32_t SPI_GetPolarity(void)
+{
+ return ((SPI->CTRL&SPI_CR_POLARITY)==SPI_CR_POLARITY);
+}
+
+/**
+ * @param uint32_t
+ * @return none
+ * @brief Set ClkSel
+ */
+void SPI_SetClkSel(uint32_t clksel)
+{
+ SPI->CTRL &= ~SPI_CR_CLKSEL;
+ SPI->CTRL |= ((clksel&SPI_CR_CLKSEL_Mask)<CTRL >>SPI_CR_CLKSEL_Pos)&SPI_CR_CLKSEL_Mask);
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @brief Reads transmit overrun error status
+ */
+FlagStatus SPI_GetToeStatus(void)
+{
+ return (FlagStatus)((SPI->STATUS&SPI_STATUS_TOE)==SPI_STATUS_TOE);
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @brief Returns receive overrun error status
+ */
+FlagStatus SPI_GetRoeStatus(void)
+{
+ return (FlagStatus)((SPI->STATUS&SPI_STATUS_ROE)==SPI_STATUS_ROE);
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @brief Returns transmitting status
+ */
+FlagStatus SPI_GetTmtStatus(void)
+{
+ return (FlagStatus)((SPI->STATUS&SPI_STATUS_TMT)==SPI_STATUS_TMT);
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @brief Return transmit ready status
+ */
+FlagStatus SPI_GetTrdyStatus(void)
+{
+ return (FlagStatus)((SPI->STATUS&SPI_STATUS_TRDY)==SPI_STATUS_TRDY);
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @brief Returns receive ready status
+ */
+FlagStatus SPI_GetRrdyStatus(void)
+{
+ return (FlagStatus)((SPI->STATUS&SPI_STATUS_RRDY)==SPI_STATUS_RRDY);
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @brief Returns error Status
+ */
+FlagStatus SPI_GetErrStatus(void)
+{
+ return (FlagStatus)((SPI->STATUS&SPI_STATUS_ERR)==SPI_STATUS_ERR);
+}
+/**
+ * @param none
+ * @return none
+ * @brief Clears transmit overrun error status
+ */
+void SPI_ClrToeStatus(void)
+{
+ SPI->STATUS |= SPI_STATUS_TOE;
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Clears receive overrun error status
+ */
+void SPI_ClrRoeStatus(void)
+{
+ SPI->STATUS |= SPI_STATUS_ROE;
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Clears error status
+ */
+void SPI_ClrErrStatus(void)
+{
+ SPI->STATUS |= SPI_STATUS_ERR;
+}
+
+/**
+ * @param uint8_t
+ * @return none
+ * @brief Writes Data
+ */
+void SPI_WriteData(uint8_t data)
+{
+ SPI->WDATA = data;
+}
+
+/**
+ * @param none
+ * @return uint8_t
+ * @brief Reads Data
+ */
+uint8_t SPI_ReadData(void)
+{
+ return (uint8_t)(SPI->RDATA);
+}
+
+/**
+ * @param uint32_t slave address
+ * @return none
+ * @brief Select Slave
+ */
+void SPI_Select_Slave(uint32_t Slave_address)
+{
+ SPI->SSMASK = Slave_address;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Sources/gw1ns4c_syscon.c b/PERIPHERAL/Sources/gw1ns4c_syscon.c
new file mode 100644
index 0000000..e156892
--- /dev/null
+++ b/PERIPHERAL/Sources/gw1ns4c_syscon.c
@@ -0,0 +1,153 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_syscon.c
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the SYSCON firmware library.
+ ******************************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c_syscon.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup SYSCON
+ * @brief SYSCON driver modules
+ * @{
+ */
+
+/** @defgroup SYSCON_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCON_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCON_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCON_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup SYSCON_Private_Functions
+ * @{
+ */
+
+/**
+ * @param none
+ * @return none
+ * @brief Initializes SYSCON
+ */
+void SYSCON_Init(void)
+{
+ SYSCON->REMAP = 0;
+ SYSCON->PMUCTRL = 0;
+ SYSCON->RESETOP = 0;
+ SYSCON->RSTINFO = 0;
+}
+
+/**
+ * @param none
+ * @return uint32_t
+ * @brief Returns REMAP
+ */
+uint32_t SYSCON_GetRemap(void)
+{
+ return SYSCON->REMAP;
+}
+
+/**
+ * @param none
+ * @param uint32_t
+ * @brief Returns PMUCTRL Enable
+ */
+uint32_t SYSCON_GetPmuctrlEnable(void)
+{
+ return SYSCON->PMUCTRL;
+}
+
+/**
+ * @param none
+ * @return uint32_t
+ * @brief Returns RESETOP LOCKUPRST
+ */
+uint32_t SYSCON_GetResetopLockuprst(void)
+{
+ return SYSCON->RESETOP;
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @arg SET
+ * @arg RESET
+ * @brief Returns RSTINFO SYSRESETREQ
+ */
+FlagStatus SYSCON_GetRstinfoSysresetreq(void)
+{
+ return (FlagStatus)((SYSCON->RSTINFO & SYSCON_RSTINFO_SYSRESETREQ) >> SYSCON_RSTINFO_SYSRESETREQ_Pos);
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @arg SET
+ * @arg RESET
+ * @brief Returns RSTINFO WDOGRESETREQ
+ */
+FlagStatus SYSCON_GetRstinfoWdogresetreq(void)
+{
+ return (FlagStatus)((SYSCON->RSTINFO & SYSCON_RSTINFO_WDOGRESETREQ) >> SYSCON_RSTINFO_WDOGRESETREQ_Pos);
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @arg SET
+ * @arg RESET
+ * @brief Returns RSTINFO LOCKRESET
+ */
+FlagStatus SYSCON_GetRstinfoLockreset(void)
+{
+ return (FlagStatus)((SYSCON->RSTINFO & SYSCON_RSTINFO_LOCKUPRESET) >> SYSCON_RSTINFO_LOCKUPRESET_Pos);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Sources/gw1ns4c_timer.c b/PERIPHERAL/Sources/gw1ns4c_timer.c
new file mode 100644
index 0000000..f38fcc6
--- /dev/null
+++ b/PERIPHERAL/Sources/gw1ns4c_timer.c
@@ -0,0 +1,254 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_timer.c
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the TIMER firmware library.
+ ******************************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c_timer.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup TIMER
+ * @brief TIMER driver modules
+ * @{
+ */
+
+/** @defgroup TIMER_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMER_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMER_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMER_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup TIMER_Private_Functions
+ * @{
+ */
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @param TIMER_InitTypeDef Pointer
+ * @return none
+ * @brief Initializes Timer module.
+ * TIMERInt_TypeDef : Interrupt enable.
+ * TIMERExti_TypeDef : Select external input;
+ * Or Initializes the timer to user the internal clock.
+ */
+void TIMER_Init(TIMER_TypeDef* TIMERx,TIMER_InitTypeDef* TIMER_InitStruct)
+{
+ /* Initial all register to zero */
+ TIMERx->CTRL = 0;
+ TIMERx->VALUE = 0;
+ TIMERx->RELOAD = 0;
+ TIMERx->INTCLEAR = 0;
+
+ /* VALUE register */
+ TIMERx->VALUE = TIMER_InitStruct->Reload;
+
+ /* RELOAD register */
+ TIMERx->RELOAD = TIMER_InitStruct->Reload;
+
+ /* CTRL register timer enable */
+ TIMERx->CTRL |= TIMER_CTRL_EN;
+
+ /* if TIMER_Int enable */
+ if(TIMER_InitStruct->TIMER_Int == ENABLE)
+ {
+ TIMERx->CTRL |= TIMER_CTRL_IRQEN;
+ }
+
+/* disable external input */
+ if(TIMER_InitStruct->TIMER_Exti == TIMER_DISABLE)
+ {
+ /* external input as disable */
+ TIMERx->CTRL &= ~(TIMER_CTRL_SELEXTEN |TIMER_CTRL_SELEXTEN );
+ }
+
+ /* select external input */
+ if(TIMER_InitStruct->TIMER_Exti == TIMER_EXTI_EN)
+ {
+ /* select external input as enable */
+ TIMERx->CTRL |= TIMER_CTRL_SELEXTEN;
+ }
+ else if(TIMER_InitStruct->TIMER_Exti == TIMER_EXTI_CLK)
+ {
+ /* select external input as clock */
+ TIMERx->CTRL |= TIMER_CTRL_SELEXTCLK;
+ }
+}
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @return none
+ * @brief Starts Timer.
+ */
+void TIMER_StartTimer(TIMER_TypeDef* TIMERx)
+{
+ TIMERx->CTRL |= TIMER_CTRL_EN;
+}
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @return none
+ * @brief Stops Timer.
+ */
+void TIMER_StopTimer(TIMER_TypeDef* TIMERx)
+{
+ TIMERx->CTRL &= ~TIMER_CTRL_EN;
+}
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @return Interrupt Status
+ * @arg SET
+ * @arg RESET
+ * @brief Returns timer IRQ status.
+ */
+ITStatus TIMER_GetIRQStatus(TIMER_TypeDef* TIMERx)
+{
+ return (ITStatus)(TIMERx->INTSTATUS);
+}
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @return none
+ * @brief Timer interrupt clear.
+ */
+void TIMER_ClearIRQ(TIMER_TypeDef* TIMERx)
+{
+ TIMERx->INTCLEAR = TIMER_INTCLEAR;
+}
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @return reload value
+ * @brief Returns Timer Reload value.
+ * The reload value is the value which the timer is set to after an underflow occurs.
+ */
+uint32_t TIMER_GetReload(TIMER_TypeDef* TIMERx)
+{
+ return TIMERx->RELOAD;
+}
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @param uint32_t value to set reload
+ * @return none
+ * @brief Sets Timer Reload value.
+ * The reload value is the value which the timer is set to after an underflow occurs.
+ */
+void TIMER_SetReload(TIMER_TypeDef* TIMERx,uint32_t value)
+{
+ TIMERx->RELOAD = value;
+}
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @return current value
+ * @brief Returns Timer current value.
+ */
+uint32_t TIMER_GetValue(TIMER_TypeDef* TIMERx)
+{
+ return TIMERx->VALUE;
+}
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @param uint32_t value to set current value
+ * @return none
+ * @brief Sets Timer current value.
+ */
+void TIMER_SetValue(TIMER_TypeDef* TIMERx,uint32_t value)
+{
+ TIMERx->VALUE = value;
+}
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @return none
+ * @brief Enables Timer Interrupt requests.
+ */
+void TIMER_EnableIRQ(TIMER_TypeDef* TIMERx)
+{
+ TIMERx->CTRL |= TIMER_CTRL_IRQEN;
+}
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @return none
+ * @brief Disables Timer Interrupt requests.
+ */
+void TIMER_DisableIRQ(TIMER_TypeDef* TIMERx)
+{
+ TIMERx->CTRL &= ~TIMER_CTRL_IRQEN;
+}
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @return none
+ * @brief Select Ext input Enable.
+ */
+void TIMER_SelExtEnable(TIMER_TypeDef *TIMER)
+{
+ TIMER->CTRL = ~(TIMER_CTRL_SELEXTEN |TIMER_CTRL_SELEXTCLK );
+ TIMER->CTRL |= TIMER_CTRL_SELEXTEN;
+}
+
+/**
+ * @param TIMER_TypeDef Pointer
+ * @return none
+ * @brief Select Ext input Clock.
+ */
+void TIMER_SelExtClock(TIMER_TypeDef *TIMER)
+{
+ TIMER->CTRL = ~(TIMER_CTRL_SELEXTEN |TIMER_CTRL_SELEXTCLK );
+ TIMER->CTRL |= TIMER_CTRL_SELEXTCLK;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Sources/gw1ns4c_uart.c b/PERIPHERAL/Sources/gw1ns4c_uart.c
new file mode 100644
index 0000000..aaaeb1b
--- /dev/null
+++ b/PERIPHERAL/Sources/gw1ns4c_uart.c
@@ -0,0 +1,382 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_uart.c
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the UART firmware library.
+ ******************************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c_uart.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup UART
+ * @brief UART driver modules
+ * @{
+ */
+
+/** @defgroup UART_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup UART_Private_Functions
+ * @{
+ */
+
+/**
+ * @param UART_TypeDef Pointer
+ * @param UART_InitTypeDef Pointer
+ * @return ErrorStatus
+ * @arg ERROR
+ * @arg SUCCESS
+ * @brief Initializes the UART specifying the UART Baud rate divider value.
+ * And whether the send and receive functionality is enabled.
+ * It also specifies which of the various interrupts are enabled.
+ */
+ErrorStatus UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct)
+{
+ uint32_t new_ctrl = 0;
+
+ /* Initial all register to zero */
+ UARTx->DATA = 0;
+ UARTx->STATE = 0;
+ UARTx->CTRL = 0;
+ UARTx->INTCLEAR = 0;
+ UARTx->BAUDDIV = 0;
+
+ /* Config CTRL register */
+ /* Tx Enable */
+ if(UART_InitStruct->UART_Mode.UARTMode_Tx == ENABLE)
+ {
+ new_ctrl |= UART_CTRL_TXEN;
+ }
+
+ /* Rx Enable */
+ if(UART_InitStruct->UART_Mode.UARTMode_Rx == ENABLE)
+ {
+ new_ctrl |= UART_CTRL_RXEN;
+ }
+
+ /* Tx Interrupt Enable */
+ if(UART_InitStruct->UART_Int.UARTInt_Tx == ENABLE)
+ {
+ new_ctrl |= UART_CTRL_TXIRQEN;
+ }
+
+ /* Rx Interrupt Enable */
+ if(UART_InitStruct->UART_Int.UARTInt_Rx == ENABLE)
+ {
+ new_ctrl |= UART_CTRL_RXIRQEN;
+ }
+
+ /* Tx Overrun Enable */
+ if(UART_InitStruct->UART_Ovr.UARTOvr_Tx == ENABLE)
+ {
+ new_ctrl |= UART_CTRL_TXORIRQEN;
+ }
+
+ /* Rx Overrun Enable */
+ if(UART_InitStruct->UART_Ovr.UARTOvr_Rx == ENABLE)
+ {
+ new_ctrl |= UART_CTRL_RXORIRQEN;
+ }
+
+ /* High Speed Test Mode Enable */
+ if(UART_InitStruct->UART_Hstm == ENABLE)
+ {
+ new_ctrl |= UART_CTRL_HSTM;
+ }
+
+ UARTx->CTRL = 0; /* Disable UART when changing configuration */
+ UARTx->CTRL = new_ctrl; /* Update CTRL register to new value */
+
+ /* Config baud divider */
+ UARTx->BAUDDIV = PCLK1 / UART_InitStruct->UART_BaudRate;
+
+ if((UARTx->STATE & (UART_STATE_RXOR | UART_STATE_TXOR)))
+ {
+ return ERROR;
+ }
+ else
+ {
+ return SUCCESS;
+ }
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return RxBufferFull
+ * @arg SET
+ * @arg RESET
+ * @brief Returns whether the RX buffer is full.
+ */
+FlagStatus UART_GetRxBufferFull(UART_TypeDef* UARTx)
+{
+ return (FlagStatus)((UARTx->STATE & UART_STATE_RXBF) >> UART_STATE_RXBF_Pos);
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return TxBufferFull
+ * @arg SET
+ * @arg RESET
+ * @brief Returns whether the TX buffer is full.
+ */
+FlagStatus UART_GetTxBufferFull(UART_TypeDef* UARTx)
+{
+ return (FlagStatus)((UARTx->STATE & UART_STATE_TXBF) >> UART_STATE_TXBF_Pos);
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return RxBufferOverrun
+ * @arg SET
+ * @arg RESET
+ * @brief Returns whether the RX buffer is overrun.
+ */
+FlagStatus UART_GetRxBufferOverrunStatus(UART_TypeDef* UARTx)
+{
+ return (FlagStatus)((UARTx->STATE & UART_STATE_RXOR) >> UART_STATE_RXOR_Pos);
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return TxBufferOverrun
+ * @arg SET
+ * @arg RESET
+ * @brief Returns whether the TX buffer is overrun.
+ */
+FlagStatus UART_GetTxBufferOverrunStatus(UART_TypeDef* UARTx)
+{
+ return (FlagStatus)((UARTx->STATE & UART_STATE_TXOR) >> UART_STATE_TXOR_Pos);
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return None
+ * @brief Clears RxBuffer overrun status.
+ */
+void UART_ClearRxBufferOverrunStatus(UART_TypeDef* UARTx)
+{
+ UARTx->STATE = UART_STATE_RXOR;
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return None
+ * @brief Clears RxBuffer overrun status.
+ */
+void UART_ClearTxBufferOverrunStatus(UART_TypeDef* UARTx)
+{
+ UARTx->STATE = UART_STATE_TXOR;
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @param txchar Character to be sent
+ * @return none
+ * @brief Sends a character to the TX buffer for transmission.
+ */
+void UART_SendChar(UART_TypeDef* UARTx,char txchar)
+{
+ while(UARTx->STATE & UART_STATE_TXBF);
+ UARTx->DATA = (uint32_t)txchar;
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @param str string to be sent
+ * @return none
+ * @brief Sends a string to the TX buffer for transmission.
+ */
+void UART_SendString(UART_TypeDef* pUARTx, char *str)
+{
+ unsigned int k = 0;
+
+ do
+ {
+ UART_SendChar( pUARTx, *(str + k) );
+ k++;
+ } while(*(str + k)!='\0');
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return rxchar
+ * @brief returns the character from the RX buffer which has been received.
+ */
+char UART_ReceiveChar(UART_TypeDef* UARTx)
+{
+ while(!(UARTx->STATE & UART_STATE_RXBF));
+ return (char)(UARTx->DATA);
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return BaudDiv
+ * @brief Returns the current UART Baud rate divider.
+ * Note that the Baud rate divider is the difference between
+ * the clock frequency and the Baud frequency.
+ */
+uint32_t UART_GetBaudDivider(UART_TypeDef* UARTx)
+{
+ return UARTx->BAUDDIV;
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return TX IntStatus
+ * @arg SET
+ * @arg RESET
+ * @brief Returns the TX interrupt status.
+ */
+ITStatus UART_GetTxIRQStatus(UART_TypeDef* UARTx)
+{
+ return (ITStatus)((UARTx->INTSTATUS & UART_INTSTATUS_TXIRQ) >> UART_INTSTATUS_TXIRQ_Pos);
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return RX IntStatus
+ * @arg SET
+ * @arg RESET
+ * @brief Returns the RX interrupt status.
+ */
+ITStatus UART_GetRxIRQStatus(UART_TypeDef* UARTx)
+{
+ return (ITStatus)((UARTx->INTSTATUS & UART_INTSTATUS_RXIRQ) >> UART_INTSTATUS_RXIRQ_Pos);
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return none
+ * @brief Clears the TX buffer full interrupt status.
+ */
+void UART_ClearTxIRQ(UART_TypeDef* UARTx)
+{
+ UARTx->INTCLEAR = UART_INTCLEAR_TXIRQ;
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return none
+ * @brief Clears the RX interrupt status.
+ */
+void UART_ClearRxIRQ(UART_TypeDef* UARTx)
+{
+ UARTx->INTCLEAR = UART_INTCLEAR_RXIRQ;
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return Tx OverrunIRQ
+ * @arg SET
+ * @arg RESET
+ * @brief Return UART TX Overrun Interrupt Status.
+ */
+ITStatus UART_GetTxOverrunIRQStatus(UART_TypeDef* UARTx)
+{
+ return (ITStatus)((UARTx->INTSTATUS & UART_INTSTATUS_TXORIRQ) >> UART_INTSTATUS_TXORIRQ_Pos);
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return Rx OverrunIRQ
+ * @arg SET
+ * @arg RESET
+ * @brief Return UART RX Overrun Interrupt Status.
+ */
+ITStatus UART_GetRxOverrunIRQStatus(UART_TypeDef* UARTx)
+{
+ return (ITStatus)((UARTx->INTSTATUS & UART_INTSTATUS_RXORIRQ) >> UART_INTSTATUS_RXORIRQ_Pos);
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return none
+ * @brief Clear UART TX Overrun Interrupt request.
+ */
+void UART_ClearTxOverrunIRQ(UART_TypeDef* UARTx)
+{
+ UARTx->INTCLEAR = UART_INTCLEAR_TXORIRQ;
+}
+
+/**
+ * @param UART_TypeDef Pointer
+ * @return none
+ * @brief Clear UART RX Overrun Interrupt request.
+ */
+void UART_ClearRxOverrunIRQ(UART_TypeDef* UARTx)
+{
+ UARTx->INTCLEAR = UART_INTCLEAR_RXORIRQ;
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Sets Tx High Speed Test Mode
+ */
+void UART_SetHSTM(UART_TypeDef* UARTx)
+{
+ UARTx->CTRL |= UART_CTRL_HSTM;
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Clears Tx High Speed Test Mode
+ */
+void UART_ClrHSTM(UART_TypeDef* UARTx)
+{
+ UARTx->CTRL &= ~UART_CTRL_HSTM;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/PERIPHERAL/Sources/gw1ns4c_wdog.c b/PERIPHERAL/Sources/gw1ns4c_wdog.c
new file mode 100644
index 0000000..92f3cfd
--- /dev/null
+++ b/PERIPHERAL/Sources/gw1ns4c_wdog.c
@@ -0,0 +1,336 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_wdog.c
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains all the functions prototypes for the WatchDog firmware library.
+ ******************************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c_wdog.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup WDOG
+ * @brief WDOG driver modules
+ * @{
+ */
+
+/** @defgroup WDOG_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WDOG_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WDOG_Private_Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WDOG_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @defgroup WDOG_Private_Functions
+ * @{
+ */
+
+/**
+ *
+ * @param WDOG_InitTypeDef Pointer
+ * @return ErrorStatus
+ * @arg ERROR
+ * @arg SUCCESS
+ * @brief Initials WatchDog.
+ */
+ErrorStatus WDOG_Init(WDOG_InitTypeDef* WDOG_InitStruct)
+{
+ WDOG->LOAD = 0;
+ WDOG->CTRL = 0;
+ WDOG->INTCLR = 0;
+ WDOG->LOCK = 0;
+ WDOG->ITCR = 0;
+ WDOG->ITOP = 0;
+
+ /* Set LOCK register */
+ if(WDOG_InitStruct->WDOG_Lock == DISABLE)
+ {
+ WDOG->LOCK = 0xFFFFFFFF; /* lock : [0] bit is 1, disable write access register */
+ return ERROR;
+ }
+
+ /* unlock : Enable write access all register */
+ WDOG->LOCK = 0xACCE551 << WDOG_LOCK_EN_Pos; /* [0] bit is 0 */
+
+ /* Set Control register Reset bit */
+ if(WDOG_InitStruct->WDOG_Res == ENABLE)
+ {
+ WDOG->CTRL |= WDOG_CTRL_RESEN;
+
+ /* Set Integration Test Mode register */
+ if(WDOG_InitStruct->WDOG_ITMode == ENABLE)
+ {
+ WDOG->ITCR |= WDOG_ITCR_INTEGTESTEN;
+
+ /* Set ITOP register WDOGRES bit */
+ WDOG->ITOP |= WDOG_ITOP_WDOGRES;
+ }
+ }
+
+ /* Set Control register Interrupt bit */
+ if(WDOG_InitStruct->WDOG_Int == ENABLE)
+ {
+ WDOG->CTRL |= WDOG_CTRL_INTEN;
+
+ /* Set Integration Test Mode register */
+ {
+ WDOG->ITCR |= WDOG_ITCR_INTEGTESTEN;
+
+ /* Set ITOP register WDOGINT bit */
+ WDOG->ITOP |= WDOG_ITOP_WDOGINT;
+ }
+ }
+
+ /* RIS register only read */
+
+ /* Set MIS register only read */
+
+ /* Set Reload register */
+ WDOG->LOAD = WDOG_InitStruct->WDOG_Reload;
+
+ /* Set Value register only read */
+
+ return SUCCESS;
+}
+
+/**
+ * @param uint32_t load
+ * @return none
+ * @brief Restart counter, reload value.
+ */
+void WDOG_RestartCounter(uint32_t reload)
+{
+ WDOG->LOAD = reload;
+}
+
+/**
+ * @param none
+ * @return uint32_t value
+ * @brief Returns current counter value.
+ */
+uint32_t WDOG_GetCounterValue(void)
+{
+ return WDOG->VALUE;
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Sets reset enable.
+ */
+void WDOG_SetResetEnable(void)
+{
+ WDOG->CTRL |= WDOG_CTRL_RESEN;
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @arg SET
+ * @arg RESET
+ * @brief Returns reset status.
+ */
+FlagStatus WDOG_GetResStatus(void)
+{
+ return (FlagStatus)(WDOG->CTRL==WDOG_CTRL_RESEN);
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Sets interrupt enable.
+ */
+void WDOG_SetIntEnable(void)
+{
+ WDOG->CTRL |= WDOG_CTRL_INTEN;
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @arg SET
+ * @arg RESET
+ * @brief Returns interrupt status.
+ */
+FlagStatus WDOG_GetIntStatus(void)
+{
+ return (FlagStatus)(WDOG->CTRL==WDOG_CTRL_INTEN);
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Clears interrupt enable.
+ */
+void WDOG_ClrIntEnable(void)
+{
+ /* Write any value to INTCLR clears the interrupt */
+ WDOG->INTCLR = WDOG_INTCLR;
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @arg SET
+ * @arg RESET
+ * @brief Returns raw interrupt status.
+ */
+FlagStatus WDOG_GetRawIntStatus(void)
+{
+ return (FlagStatus)(WDOG->RIS==WDOG_RAWINTSTAT);
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @arg SET
+ * @arg RESET
+ * @brief Return masked interrupt status.
+ */
+FlagStatus WDOG_GetMaskIntStatus(void)
+{
+ return (FlagStatus)(WDOG->MIS==WDOG_MASKINTSTAT);
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Disable write access all registers.
+ */
+void WDOG_LockWriteAccess(void)
+{
+ WDOG->LOCK = 0;
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Enable write access all registers.
+ */
+void WDOG_UnlockWriteAccess(void)
+{
+ WDOG->LOCK = 0x1ACCE551;
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Sets integration test mode enable.
+ */
+void WDOG_SetITModeEnable(void)
+{
+ WDOG->ITCR |= WDOG_ITCR_INTEGTESTEN;
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Clears integration test mode enable.
+ */
+void WDOG_ClrITModeEnable(void)
+{
+ WDOG->ITCR &= ~WDOG_ITCR_INTEGTESTEN;
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @arg SET
+ * @arg RESET
+ * @brief Returns integration test mode status.
+ */
+FlagStatus WDOG_GetITModeStatus(void)
+{
+ return (FlagStatus)(WDOG->ITCR==WDOG_ITCR_INTEGTESTEN);
+}
+
+/**
+ * @param uint32_t
+ * @return none
+ * @brief Sets integration test output reset or interrupt.
+ */
+void WDOG_SetITOP(uint32_t itop)
+{
+ WDOG->ITOP = itop;
+}
+/**
+ * @param uint32_t
+ * @return none
+ * @brief Clear integration test output reset or interrupt.
+ */
+void WDOG_ClrITOP(uint32_t itop)
+{
+ WDOG->ITOP &= ~itop;
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @arg SET
+ * @arg RESET
+ * @brief Returns integration test output reset status.
+ */
+FlagStatus WDOG_GetITOPResStatus(void)
+{
+ return (FlagStatus)(WDOG->ITOP==WDOG_ITOP_WDOGRES);
+}
+
+/**
+ * @param none
+ * @return FlagStatus
+ * @arg SET
+ * @arg RESET
+ * @brief Returns integration test output interrupt status.
+ */
+FlagStatus WDOG_GetITOPIntStatus(void)
+{
+ return (FlagStatus)(WDOG->ITOP==WDOG_ITOP_WDOGINT);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/STARTUP/startup_gw1ns4c.S b/STARTUP/startup_gw1ns4c.S
new file mode 100644
index 0000000..a0a019c
--- /dev/null
+++ b/STARTUP/startup_gw1ns4c.S
@@ -0,0 +1,263 @@
+// **************************************************************************************
+// *
+// (C) COPYRIGHT 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+// *
+// * File Name : startup_gw1ns4c.S
+// * Author : Embedded Development Team
+// * Version : V1.x.x
+// * Date : 2021-01-01 09:00:00
+// * Description: GW1NS-4C Devices vector table for GOWIN MCU Designer
+// * Should use with GOWIN MCU Designer for GW1NS-4C
+// * This module performs:
+// * - Set the initial SP
+// * - Set the initial PC == Reset_Handler
+// * - Set the vector table entries with exceptions ISR address
+// * - Configure the system clock
+// * - Branches to __main in the C library(which eventually calls main())
+// * After Reset the Cortex-M3 processor is in Thread mode,
+// * priority is Privileged and the Stach is set to Main
+// *
+// * <<< Use Configuration Wizard in Context Menu >>>
+// *
+// ****************************************************************************************
+
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+
+//
+// Stack Configuration
+// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//
+//
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+
+//
+// Heap Configuration
+// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+//
+//
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x200
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+
+// Vector Table
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop // Top of Stack
+ .long Reset_Handler // Reset Handler
+ .long NMI_Handler // NMI Handler
+ .long HardFault_Handler // Hard Fault Handler
+ .long MemManage_Handler // MPU Fault Handler
+ .long BusFault_Handler // Bus Fault Handler
+ .long UsageFault_Handler // Usage Fault Handler
+ .long 0 // Reserved
+ .long 0 // Reserved
+ .long 0 // Reserved
+ .long 0 // Reserved
+ .long SVC_Handler // SVCall Handler
+ .long DebugMon_Handler // Debug Monitor Handler
+ .long 0 // Reserved
+ .long PendSV_Handler // PendSV Handler
+ .long SysTick_Handler // SysTick Handler
+
+ //External Interrupts
+ .long UART0_Handler // 16+ 0: UART 0 RX and TX Handler
+ .long USER_INT0_Handler // 16+ 1: Interrupt handler 0 to user extension
+ .long UART1_Handler // 16+ 2: UART 1 RX and TX Handler
+ .long USER_INT1_Handler // 16+ 3: Interrupt handler 1 to user extension
+ .long USER_INT2_Handler // 16+ 4: Interrupt handler 2 to user extension
+ .long RTC_Handler // 16+ 5: RTC Handler
+ .long PORT0_COMB_Handler // 16+ 6: GPIO Port 0 Combined Handler
+ .long USER_INT3_Handler // 16+ 7: Interrupt handler 3 to user extension
+ .long TIMER0_Handler // 16+ 8: TIMER 0 handler
+ .long TIMER1_Handler // 16+ 9: TIMER 1 handler
+ .long 0 // 16+10: Reserved
+ .long I2C_Handler // 16+11: I2C handler
+ .long UARTOVF_Handler // 16+12: UART 0,1 Overflow Handler
+ .long USER_INT4_Handler // 16+13: Interrupt handler 4 to user extension
+ .long USER_INT5_Handler // 16+14: Interrupt handler 5 to user extension
+ .long Spare15_Handler // 16+15: Not Used
+ .long PORT0_0_Handler // 16+16: GPIO Port 0 pin 0 Handler
+ .long PORT0_1_Handler // 16+17: GPIO Port 0 pin 1 Handler
+ .long PORT0_2_Handler // 16+18: GPIO Port 0 pin 2 Handler
+ .long PORT0_3_Handler // 16+19: GPIO Port 0 pin 3 Handler
+ .long PORT0_4_Handler // 16+20: GPIO Port 0 pin 4 Handler
+ .long PORT0_5_Handler // 16+21: GPIO Port 0 pin 5 Handler
+ .long PORT0_6_Handler // 16+22: GPIO Port 0 pin 6 Handler
+ .long PORT0_7_Handler // 16+23: GPIO Port 0 pin 7 Handler
+ .long PORT0_8_Handler // 16+24: GPIO Port 0 pin 8 Handler
+ .long PORT0_9_Handler // 16+25: GPIO Port 0 pin 9 Handler
+ .long PORT0_10_Handler // 16+26: GPIO Port 0 pin 10 Handler
+ .long PORT0_11_Handler // 16+27: GPIO Port 0 pin 11 Handler
+ .long PORT0_12_Handler // 16+28: GPIO Port 0 pin 12 Handler
+ .long PORT0_13_Handler // 16+29: GPIO Port 0 pin 13 Handler
+ .long PORT0_14_Handler // 16+30: GPIO Port 0 pin 14 Handler
+ .long PORT0_15_Handler // 16+31: GPIO Port 0 pin 15 Handler
+ .size __isr_vector, . - __isr_vector
+
+// Reset Handler
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+// Loop to copy data from read only memory to RAM. The ranges
+// of copy from/to are specified by following symbols evaluated in
+// linker script.
+// __etext: End of code section, i.e., begin of data sections to copy from.
+// __data_start__/__data_end__: RAM address range that data should be
+// copied to. Both must be aligned to 4 bytes boundary.
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .LC1
+.LC0:
+ subs r3, #4
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ bgt .LC0
+.LC1:
+
+#ifdef __STARTUP_CLEAR_BSS
+// This part of work usually is done in C library startup code. Otherwise,
+// define this macro to enable it in this startup.
+//
+// Loop to zero out BSS section, which uses following symbols
+// in linker script:
+// __bss_start__: start of BSS section. Must align to 4
+// __bss_end__: end of BSS section. Must align to 4
+
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.LC2:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .LC2
+#endif //__STARTUP_CLEAR_BSS
+
+#ifndef __NO_SYSTEM_INIT
+ // bl SystemInit
+ ldr r0,=SystemInit
+ blx r0
+#endif
+
+ bl main
+ bl exit
+
+
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+// Macro to define default handlers. Default handler
+// will be weak symbol and just dead loops. They can be
+// overwritten by other handlers
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+// System Exception Handlers
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+
+// IRQ Handlers
+
+ def_default_handler UART0_Handler
+ def_default_handler USER_INT0_Handler
+ def_default_handler UART1_Handler
+ def_default_handler USER_INT1_Handler
+ def_default_handler USER_INT2_Handler
+ def_default_handler RTC_Handler
+ def_default_handler PORT0_COMB_Handler
+ def_default_handler USER_INT3_Handler
+ def_default_handler TIMER0_Handler
+ def_default_handler TIMER1_Handler
+ def_default_handler I2C_Handler
+ def_default_handler UARTOVF_Handler
+ def_default_handler USER_INT4_Handler
+ def_default_handler USER_INT5_Handler
+ def_default_handler Spare15_Handler
+ def_default_handler PORT0_0_Handler
+ def_default_handler PORT0_1_Handler
+ def_default_handler PORT0_2_Handler
+ def_default_handler PORT0_3_Handler
+ def_default_handler PORT0_4_Handler
+ def_default_handler PORT0_5_Handler
+ def_default_handler PORT0_6_Handler
+ def_default_handler PORT0_7_Handler
+ def_default_handler PORT0_8_Handler
+ def_default_handler PORT0_9_Handler
+ def_default_handler PORT0_10_Handler
+ def_default_handler PORT0_11_Handler
+ def_default_handler PORT0_12_Handler
+ def_default_handler PORT0_13_Handler
+ def_default_handler PORT0_14_Handler
+ def_default_handler PORT0_15_Handler
+
+ //
+ // def_default_handler Default_Handler
+ //.weak DEF_IRQHandler
+ //.set DEF_IRQHandler, Default_Handler
+
+ .end
+
+//*************************GowinSemiconductor*****END OF FILE*********************
diff --git a/SYSTEM/gw1ns4c.h b/SYSTEM/gw1ns4c.h
new file mode 100644
index 0000000..f93fb2a
--- /dev/null
+++ b/SYSTEM/gw1ns4c.h
@@ -0,0 +1,593 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for Device GW1NS-4C.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for GW1NS-4C Connectivity line,
+ * High density, High density value line, Medium density,
+ * Medium density Value line, Low density, Low density Value line
+ * and XL-density devices.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The device used in the target application
+ * - To use or not the peripheral drivers in application code(i.e.
+ * code will be based on direct access to peripheral registers
+ * rather than drivers API)
+ * - To change few application-specific parameters such as
+ * crystal frequency
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral registers declarations and bits definition
+ * - Macros to access peripheral registers hardware
+ *
+ ******************************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup GW1NS4C
+ * @{
+ */
+
+#ifndef __GW1NS4C_H
+#define __GW1NS4C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/*
+ * Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+#define __CM3_REV 0x0201 /*!< Core Revision r2p1 */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ********************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** GW1NS-4C Specific Interrupt Numbers ************************************/
+ UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */
+ USER_INT0_IRQn = 1, /* Interrupt handler 0 to user extension */
+ UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */
+ USER_INT1_IRQn = 3, /* Interrupt handler 1 to user extension */
+ USER_INT2_IRQn = 4, /* Interrupt handler 2 to user extension */
+ RTC_IRQn = 5, /* RTC Interrupt */
+ PORT0_COMB_IRQn = 6, /* GPIO Port 0 combined Interrupt */
+ USER_INT3_IRQn = 7, /* Interrupt handler 3 to user extension */
+ TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
+ TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
+ I2C_IRQn = 11, /* I2C */
+ UARTOVF_IRQn = 12, /* UART 0,1 Overflow Interrupt */
+ USER_INT4_IRQn = 13, /* Interrupt handler 4 to user extension */
+ USER_INT5_IRQn = 14, /* Interrupt handler 5 to user extension */
+ Spare15_IRQn = 15, /* Undefined */
+ PORT0_0_IRQn = 16, /*!< All P0 I/O pins can be used as interrupt source. */
+ PORT0_1_IRQn = 17, /*!< There are 16 pins in total */
+ PORT0_2_IRQn = 18, /*! PORT0_2 Interrupt */
+ PORT0_3_IRQn = 19, /*! PORT0_3 Interrupt */
+ PORT0_4_IRQn = 20, /*! PORT0_4 Interrupt */
+ PORT0_5_IRQn = 21, /*! PORT0_5 Interrupt */
+ PORT0_6_IRQn = 22, /*! PORT0_6 Interrupt */
+ PORT0_7_IRQn = 23, /*! PORT0_7 Interrupt */
+ PORT0_8_IRQn = 24, /*! PORT0_8 Interrupt */
+ PORT0_9_IRQn = 25, /*! PORT0_9 Interrupt */
+ PORT0_10_IRQn = 26, /*! PORT0_10 Interrupt */
+ PORT0_11_IRQn = 27, /*! PORT0_11 Interrupt */
+ PORT0_12_IRQn = 28, /*! PORT0_12 Interrupt */
+ PORT0_13_IRQn = 29, /*! PORT0_13 Interrupt */
+ PORT0_14_IRQn = 30, /*! PORT0_14 Interrupt */
+ PORT0_15_IRQn = 31 /*! PORT0_15 Interrupt */
+}IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
+#include "system_gw1ns4c.h" /* GW1NS-4C System include file */
+
+/** @addtogroup Exported_types
+ * @{
+ */
+
+typedef enum
+{
+ RESET = 0,
+ SET = !RESET
+}FlagStatus,ITStatus;
+
+typedef enum
+{
+ DISABLE = 0,
+ ENABLE = !DISABLE
+}FunctionalState;
+
+typedef enum
+{
+ ERROR = 0,
+ SUCCESS = !ERROR
+}ErrorStatus;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/* -------------------- Begin of section using anonymous unions ------------------- */
+#if defined ( __CC_ARM )
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+/******************************************************************************/
+/* Peripheral Registers Definition */
+/******************************************************************************/
+
+/*--------- Universal Asynchronous Receiver Transmitter (UART) --------*/
+typedef struct
+{
+ __IO uint32_t DATA; /*!< Offset: 0x000 Data Register (R/W) */
+ __IO uint32_t STATE; /*!< Offset: 0x004 Status Register (R/W) */
+ __IO uint32_t CTRL; /*!< Offset: 0x008 Control Register (R/W) */
+ union
+ {
+ __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
+ __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
+ };
+ __IO uint32_t BAUDDIV; /*!< Offset: 0x010 Baudrate Divider Register (R/W) */
+}UART_TypeDef;
+
+/*------------------------ Timer (TIMER) ------------------------*/
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 Control Register (R/W) */
+ __IO uint32_t VALUE; /*!< Offset: 0x004 Current Value Register (R/W) */
+ __IO uint32_t RELOAD; /*!< Offset: 0x008 Reload Value Register (R/W) */
+ union
+ {
+ __I uint32_t INTSTATUS; /*!< Offset: 0x00C Interrupt Status Register (R/ ) */
+ __O uint32_t INTCLEAR; /*!< Offset: 0x00C Interrupt Clear Register ( /W) */
+ };
+}TIMER_TypeDef;
+
+/*--------------------- General Purpose Input Output (GPIO) ----------*/
+typedef struct
+{
+ __IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
+ __IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
+ uint32_t RESERVED0[2]; /* Offset: 0x010-0x004 */
+ __IO uint32_t OUTENSET; /* Offset: 0x010 (R/W) Output Enable Set Register */
+ __IO uint32_t OUTENCLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
+ __IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
+ __IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
+ __IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
+ __IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
+ __IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
+ __IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
+ __IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
+ __IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
+ union
+ {
+ __I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
+ __O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
+ };
+ uint32_t RESERVED1[241]; /* Offset : 0x400-0x0038 */
+ __IO uint32_t MASKLOWBYTE[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
+ __IO uint32_t MASKHIGHBYTE[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
+}GPIO_TypeDef;
+
+/*----------------------------- WatchDog ------------------------*/
+typedef struct
+{
+ __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
+ __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
+ __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
+ __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
+ __I uint32_t RIS; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
+ __I uint32_t MIS; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
+ uint32_t RESERVED0[762]; /* Offset: 0xC00-0x014 */
+ __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
+ uint32_t RESERVED1[191]; /* Offset: 0xF00-0xC00 */
+ __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
+ __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
+}WDOG_TypeDef;
+
+/*---------------------------------- I2C ------------------------------*/
+typedef struct
+{
+ __IO uint32_t PRER; /* Offset: 0x00 (R/W) I2C Prescale Register */
+ __IO uint32_t CTR; /* Offset: 0x04 (R/W) I2C Control Register */
+ union
+ {
+ __I uint32_t RXR; /* Offset: 0x0C (R/ ) I2C Data Receive Register */
+ __O uint32_t TXR; /* Offset: 0x08 ( /W) I2C Data Transmit Register */
+ };
+ union
+ {
+ __I uint32_t SR; /* Offset: 0x14 (R/ ) I2C Status Register */
+ __O uint32_t CR; /* Offset: 0x10 ( /W) I2C Command Register */
+ };
+}I2C_TypeDef;
+
+/*------------------ System Control (SYSCON) -----------------------*/
+typedef struct
+{
+ __IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
+ __IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
+ __IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
+ __IO uint32_t RESERVED0; /* Offset: 0x00C Reserved */
+ __IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
+}SYSCON_TypeDef;
+
+/*----------------Serial Peripheral Interface (SPI)-----------------*/
+typedef struct
+{
+ __I uint32_t RDATA; /* Offset: 0x00 (R/ ) Data Read Register */
+ __O uint32_t WDATA; /* Offset: 0x04 (/W ) Data Write Register */
+ __IO uint32_t STATUS; /* Offset: 0x08 (R/W) Status Register */
+ __IO uint32_t SSMASK; /* Offset: 0x0C (R/W) Unused Select slave address */
+ __IO uint32_t CTRL; /* Offset: 0x10 (R/W) Control Register */
+}SPI_TypeDef;
+
+/*--------------------Real Timer Clock (RTC)-----------------------*/
+typedef struct
+{
+ __I uint32_t RTC_CURRENT_DATA; /* Offset: 0x000 (R/ ) Data Register */
+ __IO uint32_t RTC_MATCH_VALUE; /* Offset: 0x004 (R/W) Match Register */
+ __IO uint32_t RTC_LOAD_VALUE; /* Offset: 0x008 (R/W) Load Register */
+ __IO uint32_t RTC_CTROLLER_REG; /* Offset: 0x00C (R/W) Control Register */
+ __IO uint32_t RTC_IMSC; /* Offset: 0x010 (R/W) Interrupt Mask Set and Clear Register */
+ __I uint32_t RTC_RIS; /* Offset: 0x014 (R/ ) Raw Interrupt Status Register */
+ __I uint32_t RTC_MIS; /* Offset: 0x018 (R/ ) Masked Interrupt Status Register */
+ __O uint32_t RTC_INTR_CLEAR; /* Offset: 0x01C ( /W) Interrupt Clear Register */
+}RTC_TypeDef;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined ( __CC_ARM )
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+/* Peripheral and SRAM base address */
+#define FLASH_BASE ((uint32_t)0x00000000) /*!< (FLASH ) Base Address */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< (SRAM ) Base Address */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< (Peripheral) Base Address */
+
+#define APB1PERIPH_BASE PERIPH_BASE /* !< APB1_Peripheral Base Address */
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x02000) /* !< APB2_Peripheral Base Address */
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x10000) /* !< AHB1 Peripheral Base Address */
+#define AHB2PERIPH_BASE ((uint32_t)0xA0000000) /* !< AHB2 Peripheral Base Address */
+
+/* APB1 Peripheral base address */
+#define TIMER0_BASE (APB1PERIPH_BASE + 0x0000) /* !< TIMER0 Base Address */
+#define TIMER1_BASE (APB1PERIPH_BASE + 0x1000) /* !< TIMER1 Base Address */
+#define UART0_BASE (APB1PERIPH_BASE + 0x4000) /* !< UART0 Base Address */
+#define UART1_BASE (APB1PERIPH_BASE + 0x5000) /* !< UART1 Base Address */
+#define RTC_BASE (APB1PERIPH_BASE + 0x6000) /* !< RTC Base Address */
+#define WDOG_BASE (APB1PERIPH_BASE + 0x8000) /* !< WATCHDOG Base Address */
+
+/* APB2 Peripheral base address */
+#define I2C_BASE (APB2PERIPH_BASE + 0x0000) /* !< I2C Base Address */
+#define SPI_BASE (APB2PERIPH_BASE + 0x0200) /* !< SPI Base Address */
+
+/* AHB Peripheral base address */
+#define GPIO0_BASE (AHB1PERIPH_BASE + 0x0000) /* !< GPIO0 Base Address */
+#define SYSCTRL_BASE (AHB1PERIPH_BASE + 0xF000) /* !< SYSCON Base Address */
+
+/* APB2 Extension Peripherals base address to user */
+#define APB2MASTER1_BASE (APB2PERIPH_BASE + 0x400) /* !< APB2 Master 1 Base Address */
+#define APB2MASTER2_BASE (APB2PERIPH_BASE + 0x500) /* !< APB2 Master 2 Base Address */
+#define APB2MASTER3_BASE (APB2PERIPH_BASE + 0x600) /* !< APB2 Master 3 Base Address */
+#define APB2MASTER4_BASE (APB2PERIPH_BASE + 0x700) /* !< APB2 Master 4 Base Address */
+#define APB2MASTER5_BASE (APB2PERIPH_BASE + 0x800) /* !< APB2 Master 5 Base Address */
+#define APB2MASTER6_BASE (APB2PERIPH_BASE + 0x900) /* !< APB2 Master 6 Base Address */
+#define APB2MASTER7_BASE (APB2PERIPH_BASE + 0xA00) /* !< APB2 Master 7 Base Address */
+#define APB2MASTER8_BASE (APB2PERIPH_BASE + 0xB00) /* !< APB2 Master 8 Base Address */
+#define APB2MASTER9_BASE (APB2PERIPH_BASE + 0xC00) /* !< APB2 Master 9 Base Address */
+#define APB2MASTER10_BASE (APB2PERIPH_BASE + 0xD00) /* !< APB2 Master 10 Base Address */
+#define APB2MASTER11_BASE (APB2PERIPH_BASE + 0xE00) /* !< APB2 Master 11 Base Address */
+#define APB2MASTER12_BASE (APB2PERIPH_BASE + 0xF00) /* !< APB2 Master 12 Base Address */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define UART0 ((UART_TypeDef *) UART0_BASE)
+#define UART1 ((UART_TypeDef *) UART1_BASE)
+#define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE)
+#define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE)
+#define WDOG ((WDOG_TypeDef *) WDOG_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+
+#define GPIO0 ((GPIO_TypeDef *) GPIO0_BASE)
+#define SYSCON ((SYSCON_TypeDef *) SYSCTRL_BASE)
+
+#define I2C ((I2C_TypeDef *) I2C_BASE) //Soft-Core Extended
+#define SPI ((SPI_TypeDef *) SPI_BASE) //Soft-Core Extended
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Universal Asynchronous Receiver Transmitter (UART) */
+/******************************************************************************/
+/* bit definitions for DATA register */
+#define UART_DATA ((uint32_t) 0x000000FF) /* UART DATA: Data value */
+
+/* bit definitions for STATE register */
+#define UART_STATE_TXBF ((uint32_t) 0x00000001) /* UART STATE: Tx buffer full */
+#define UART_STATE_RXBF ((uint32_t) 0x00000002) /* UART STATE: Rx buffer full */
+#define UART_STATE_TXOR ((uint32_t) 0x00000004) /* UART STATE: Tx buffer overrun */
+#define UART_STATE_RXOR ((uint32_t) 0x00000008) /* UART STATE: Rx buffer overrun */
+
+/* bit definitions for CTRL register */
+#define UART_CTRL_TXEN ((uint32_t) 0x00000001) /* UART CTRL: TX enable */
+#define UART_CTRL_RXEN ((uint32_t) 0x00000002) /* UART CTRL: RX enable
+ */
+#define UART_CTRL_TXIRQEN ((uint32_t) 0x00000004) /* UART CTRL: TX interrupt enable
+ */
+#define UART_CTRL_RXIRQEN ((uint32_t) 0x00000008) /* UART CTRL: RX interrupt enable
+ */
+#define UART_CTRL_TXORIRQEN ((uint32_t) 0x00000010) /* UART CTRL: TX overrun interrupt enable */
+#define UART_CTRL_RXORIRQEN ((uint32_t) 0x00000020) /* UART CTRL: RX overrun interrupt enable */
+#define UART_CTRL_HSTM ((uint32_t) 0x00000040) /* UART CTRL: High-speed test mode for TX enable */
+
+/* bit definitions for INTSTATUS register */
+#define UART_INTSTATUS_TXIRQ ((uint32_t) 0x00000001) /* UART INTCLEAR: Get TX interrupt status */
+#define UART_INTSTATUS_RXIRQ ((uint32_t) 0x00000002) /* UART INTCLEAR: Get RX interrupt status */
+#define UART_INTSTATUS_TXORIRQ ((uint32_t) 0x00000004) /* UART INTCLEAR: Get TX overrun interrupt status */
+#define UART_INTSTATUS_RXORIRQ ((uint32_t) 0x00000008) /* UART INTCLEAR: Get RX overrun interrupt status */
+
+/* bit definitions for INTCLEAR register */
+#define UART_INTCLEAR_TXIRQ ((uint32_t) 0x00000001) /* UART INTCLEAR: Clear TX interrupt */
+#define UART_INTCLEAR_RXIRQ ((uint32_t) 0x00000002) /* UART INTCLEAR: Clear RX interrupt */
+#define UART_INTCLEAR_TXORIRQ ((uint32_t) 0x00000004) /* UART INTCLEAR: Clear TX overrun interrupt */
+#define UART_INTCLEAR_RXORIRQ ((uint32_t) 0x00000008) /* UART INTCLEAR: Clear RX overrun interrupt */
+
+/* bit definitions for BAUDDIV register */
+#define UART_BAUDDIV ((uint32_t) 0x000FFFFF) /* UART BAUDDIV: Baud rate divider*/
+
+
+/******************************************************************************/
+/* Timer (TIMER) */
+/******************************************************************************/
+/* bit definitions for CTRL register */
+#define TIMER_CTRL_EN ((uint32_t) 0x00000001) /* TIMER CTRL: Enable */
+#define TIMER_CTRL_SELEXTEN ((uint32_t) 0x00000002) /* TIMER CTRL: Select external input as enable */
+#define TIMER_CTRL_SELEXTCLK ((uint32_t) 0x00000004) /* TIMER CTRL: Select external input as clock */
+#define TIMER_CTRL_IRQEN ((uint32_t) 0x00000008) /* TIMER CTRL: Timer interrupt enable */
+
+/* bit definitions for VALUE register */
+#define TIMER_VALUE ((uint32_t) 0xFFFFFFFF) /* TIMER VALUE: Current value */
+
+/* bit definitions for RELOAD register */
+#define TIMER_RELOAD ((uint32_t) 0xFFFFFFFF) /* TIMER RELOAD: Reload value */
+
+/* bit definitions for INTSTATUS register */
+#define TIMER_INTSTATUS ((uint32_t) 0x00000001) /* TIMER INTSTATUS: Get Timer interrupt status */
+
+/* bit definitions for INTCLEAR register */
+#define TIMER_INTCLEAR ((uint32_t) 0x00000001) /* TIMER INTCLEAR: Clear Timer interrupt */
+
+/******************************************************************************/
+/* General Purpose Input Output (GPIO) */
+/******************************************************************************/
+/* bit definitions for DATA register */
+#define GPIO_DATA ((uint32_t) 0x0000FFFF) /* GPIO DATA: Data value */
+
+/* bit definitions for DATAOUT register */
+#define GPIO_DATAOUT ((uint32_t) 0x0000FFFF) /* GPIO DATAOUT: Data output value */
+
+/* bit definitions for OUTENSET register */
+#define GPIO_OUTENSET ((uint32_t) 0x0000FFFF) /* GPIO OUTENSET: Output enable set */
+
+/* bit definitions for OUTENCLR register */
+#define GPIO_OUTENCLR ((uint32_t) 0x0000FFFF) /* GPIO OUTENCLR: Output enable clear */
+
+/* bit definitions for ALTFUNCSET register */
+#define GPIO_ALTFUNSET ((uint32_t) 0x0000FFFF) /* GPIO ALTFUNCSET: Alternative function set */
+
+/* bit definitions for ALTFUNCCLR register */
+#define GPIO_ALTFUNCCLR ((uint32_t) 0x0000FFFF) /* GPIO ALTFUNCCLR: Alternative function clear */
+
+/* bit definitions for INTENSET register */
+#define GPIO_INTENSET ((uint32_t) 0x0000FFFF) /* GPIO INTENSET: Interrupt enable set */
+
+/* bit definitions for INTENCLR register */
+#define GPIO_INTENCLR ((uint32_t) 0x0000FFFF) /* GPIO INTENCLR: Interrupt enable clear */
+
+/* bit definitions for INTTYPESET register */
+#define GPIO_INTTYPESET ((uint32_t) 0x0000FFFF) /* GPIO INTTYPESET: Interrupt type set */
+
+/* bit definitions for INTTYPECLR register */
+#define GPIO_INTTYPECLR ((uint32_t) 0x0000FFFF) /* GPIO INTTYPECLR: Interrupt type clear */
+
+/* bit definitions for INTPOLSET register */
+#define GPIO_INTPOLSET ((uint32_t) 0x0000FFFF) /* GPIO INTPOLSET: Interrupt polarity set */
+
+/* bit definitions for INTPOLCLR register */
+#define GPIO_INTPOLCLR ((uint32_t) 0x0000FFFF) /* GPIO INTPOLCLR: Interrupt polarity clear */
+
+/* bit definitions for INTSTATUS register */
+#define GPIO_INTSTATUS ((uint32_t) 0x0000FFFF) /* GPIO INTSTATUS: Get Interrupt status */
+
+/* bit definitions for INTCLEAR register */
+#define GPIO_INTCLEAR ((uint32_t) 0x0000FFFF) /* GPIO INTCLEAR: Interrupt request clear*/
+
+/* bit definitions for MASKLOWBYTE register */
+#define GPIO_MASKLOWBYTE ((uint32_t) 0x000000FF) /* GPIO MASKLOWBYTE: Data for lower byte access */
+
+/* bit definitions for MASKHIGHBYTE register */
+#define GPIO_MASKHIGHBYTE ((uint32_t) 0x0000FF00) /* GPIO MASKHIGHBYTE: Data for high byte access */
+
+/******************************************************************************/
+/* WatchDog (WDOG) */
+/******************************************************************************/
+/* bit definitions for LOAD register */
+#define WDOG_LOAD ((uint32_t) 0xFFFFFFFF) /* the value from which the counter is to decrement */
+
+/* bit definitions for VALUE register */
+#define WDOG_VALUE ((uint32_t) 0xFFFFFFFF) /* the current value of the decrementing counter */
+
+/* bit definitions for CTRL register */
+#define WDOG_CTRL_INTEN ((uint32_t) 0x00000001) /* Enable the interrupt */
+#define WDOG_CTRL_RESEN ((uint32_t) 0x00000002) /* Enable watchdog reset output */
+
+/* bit definitions for INTCLR register */
+#define WDOG_INTCLR ((uint32_t) 0x00000001) /* clear the watchdog interrupt and reloads the counter */
+
+/* bit definitions for RAWINTSTAT register */
+#define WDOG_RAWINTSTAT ((uint32_t) 0x00000001) /* Raw interrupt status from the counter */
+
+/* bit definitions for MASKINTSTAT register */
+#define WDOG_MASKINTSTAT ((uint32_t) 0x00000001) /* Enable interrupt status from the counter */
+
+/* bit definitions for LOCK register */
+#define WDOG_LOCK_ENSTAT ((uint32_t) 0x00000001) /* Register write enable status */
+#define WDOG_LOCK_EN ((uint32_t) 0xFFFFFFFE) /* Enable register writes */
+
+/* bit definitions for ITCR register */
+#define WDOG_ITCR_INTEGTESTEN ((uint32_t) 0x00000001) /* Integration test mode enable */
+
+/* bit definitions for ITOP register */
+#define WDOG_ITOP_WDOGRES ((uint32_t) 0x00000001) /* Integration test WDOGINT value */
+#define WDOG_ITOP_WDOGINT ((uint32_t) 0x00000002) /* Integration test WDOGRES value */
+
+/******************************************************************************/
+/* System Control (SYSCON) */
+/******************************************************************************/
+/* bit definitions for REMAP register */
+#define SYSCON_REMAP ((uint32_t) 0x00000001) /* SYSCON MEME_CTRL */
+
+/* bit definitions for PMUCTRL register */
+#define SYSCON_PMUCTRL_EN ((uint32_t) 0x00000001) /* PMUCTRL ENABLE */
+
+/* bit definitions for RESETOP register */
+#define SYSCON_RESETOP_LOCKUPRST ((uint32_t) 0x00000001) /* LOCKUP RESET ENABLE */
+
+/* bit definitions for RSTINFO register */
+#define SYSCON_RSTINFO_SYSRESETREQ ((uint32_t) 0x00000001) /* System Reset Request */
+#define SYSCON_RSTINFO_WDOGRESETREQ ((uint32_t) 0x00000002) /* WatchDog Reset Request */
+#define SYSCON_RSTINFO_LOCKUPRESET ((uint32_t) 0x00000004) /* Lockup Reset */
+
+/******************************************************************************/
+/* Serial Peripheral Interface (SPI) */
+/******************************************************************************/
+/* bit definitions for CTRL register */
+#define SPI_CR_DIRECTION ((uint32_t) 0x00000001) /* DIRECTION */
+#define SPI_CR_PHASE ((uint32_t) 0x00000002) /* PHASE */
+#define SPI_CR_POLARITY ((uint32_t) 0x00000004) /* POLARITY */
+#define SPI_CR_CLKSEL ((uint32_t) 0x00000018) /* CLKSEL */
+
+/* bit definitions for STATUS register */
+#define SPI_STATUS_ROE ((uint32_t) 0x00000004) /* Receive Overrun Error */
+#define SPI_STATUS_TOE ((uint32_t) 0x00000008) /* Transmit Overrun Error */
+#define SPI_STATUS_TMT ((uint32_t) 0x00000010) /* Transmitting */
+#define SPI_STATUS_TRDY ((uint32_t) 0x00000020) /* Transmit Ready */
+#define SPI_STATUS_RRDY ((uint32_t) 0x00000040) /* Receive Ready */
+#define SPI_STATUS_ERR ((uint32_t) 0x00000080) /* Error */
+
+/**
+ * @}
+ */
+
+/*-------------------------------Include peripherals---------------------------------*/
+#include "gw1ns4c_conf.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GW1NS4C_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/************************GowinSemiconductor******END OF FILE*******************/
diff --git a/SYSTEM/system_gw1ns4c.c b/SYSTEM/system_gw1ns4c.c
new file mode 100644
index 0000000..7098321
--- /dev/null
+++ b/SYSTEM/system_gw1ns4c.c
@@ -0,0 +1,146 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file system_gw1ns4c.c
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ * This file contains the system clock configuration for GW1NS-4C device.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock.
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is mad inside
+ * the "startup_gw1ns4c.s" file.
+ * - SystemCoreClock variable: Contains the core clock, it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ ******************************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup gw1ns4c_system
+ * @{
+ */
+
+/** @addtogroup GW1NS4C_System_Private_Includes
+ * @{
+ */
+
+#include "gw1ns4c.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup GW1NS4C_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GW1NS4C_System_Private_Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GW1NS4C_System_Private_Macros
+ * @{
+ */
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __XTAL (160000000UL) /* Oscillator frequency */
+
+#define __SYSTEM_CLOCK (__XTAL / 2) /* 80MHz */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GW1NS4C_System_Private_Variables
+ * @{
+ */
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+uint32_t PCLK1 = __SYSTEM_CLOCK; /*!< APB1 Clock Frequency */
+uint32_t PCLK2 = __SYSTEM_CLOCK; /*!< APB2 Clock Frequency */
+uint32_t HCLK = __SYSTEM_CLOCK; /*!< AHB Clock Frequency */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GW1NS4C_System_Private_Functions
+ * @{
+ */
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from mcu registers.
+ */
+void SystemCoreClockUpdate (void)
+{
+ SystemCoreClock = __SYSTEM_CLOCK;
+ PCLK1 = SystemCoreClock;
+ PCLK2 = SystemCoreClock;
+ HCLK = SystemCoreClock;
+}
+
+/**
+ * @param none
+ * @return none
+ * @brief Setup the mcu system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+ PCLK1 = SystemCoreClock;
+ PCLK2 = SystemCoreClock;
+ HCLK = SystemCoreClock;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/***********************GowinSemiconductor*******END OF FILE***************/
diff --git a/SYSTEM/system_gw1ns4c.h b/SYSTEM/system_gw1ns4c.h
new file mode 100644
index 0000000..a189d02
--- /dev/null
+++ b/SYSTEM/system_gw1ns4c.h
@@ -0,0 +1,116 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file system_gw1ns4c.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for Device GW1NS-4C
+ *
+ ******************************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup gw1ns4c_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_GW1NS4C_H
+#define __SYSTEM_GW1NS4C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup GW1NS4C_System_Includes
+ * @{
+ */
+
+#include
+
+/**
+ * @}
+ */
+
+/** @addtogroup GW1NS4C_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< Processor Clock Frequency */
+extern uint32_t PCLK1; /*!< APB1 Clock Frequency */
+extern uint32_t PCLK2; /*!< APB2 Clock Frequency */
+extern uint32_t HCLK; /*!< AHB Clock Frequency */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GW1NS4C_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GW1NS4C_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup GW1NS4C_System_Exported_Functions
+ * @{
+ */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the mcu system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from mcu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_GW1NS4C_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**********************GowinSemiconductor**********END OF FILE*****************/
diff --git a/USER/gw1ns4c_conf.h b/USER/gw1ns4c_conf.h
new file mode 100644
index 0000000..ab939d0
--- /dev/null
+++ b/USER/gw1ns4c_conf.h
@@ -0,0 +1,51 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_conf.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief Library configuration file.
+ ******************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion--------------------------------------*/
+#ifndef __GW1NS4C_CONF_H
+#define __GW1NS4C_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
+#include "gw1ns4c_gpio.h" /* GPIO */
+#include "gw1ns4c_wdog.h" /* WatchDog */
+#include "gw1ns4c_uart.h" /* UART */
+#include "gw1ns4c_timer.h" /* TIMER */
+#include "gw1ns4c_spi.h" /* SPI */
+#include "gw1ns4c_i2c.h" /* I2C */
+#include "gw1ns4c_misc.h" /* NVIC and SysTick */
+#include "gw1ns4c_syscon.h" /* System Control */
+#include "gw1ns4c_rtc.h" /* RTC */
+
+/* Exported macro ------------------------------------------------------------*/
+
+//#define USE_FULL_ASSERT
+#ifdef USE_FULL_ASSERT
+
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function which reports
+ * the name of the source file and the source line number of the call
+ * that failed. If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __GW1NS4C_CONF_H */
+
+/*************************GowinSemiconductor*****END OF FILE*********************/
diff --git a/USER/gw1ns4c_it.c b/USER/gw1ns4c_it.c
new file mode 100644
index 0000000..b80d512
--- /dev/null
+++ b/USER/gw1ns4c_it.c
@@ -0,0 +1,399 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_it.c
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief Main Interrupt Service Routines.
+ * This file provides template for all exceptions handler and
+ * peripherals interrupt service routine.
+ ******************************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c_it.h"
+
+/** @addtogroup GW1NS4C_StdPeriph_Template
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+
+/* Private define ------------------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+
+/* Private variables ---------------------------------------------------------*/
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/* Cortex-M3 Processor Exceptions Handlers */
+/******************************************************************************/
+
+/**
+ * @brief This function handles NMI exception.
+ * @param none
+ * @retval none
+ */
+void NMI_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles Hard Fault exception.
+ * @param none
+ * @retval none
+ */
+void HardFault_Handler(void)
+{
+ /* Go to infinite loop when Hard Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+/**
+ * @brief This function handles Memory Manage exception.
+ * @param none
+ * @retval none
+ */
+void MemManage_Handler(void)
+{
+ /* Go to infinite loop when Memory Manage exception occurs */
+ while (1)
+ {
+ }
+}
+
+/**
+ * @brief This function handles Bus Fault exception.
+ * @param none
+ * @retval none
+ */
+void BusFault_Handler(void)
+{
+ /* Go to infinite loop when Bus Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+/**
+ * @brief This function handles Usage Fault exception.
+ * @param none
+ * @retval none
+ */
+void UsageFault_Handler(void)
+{
+ /* Go to infinite loop when Usage Fault exception occurs */
+ while (1)
+ {
+ }
+}
+
+/**
+ * @brief This function handles SVCall exception.
+ * @param none
+ * @retval none
+ */
+void SVC_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles Debug Monitor exception.
+ * @param none
+ * @retval none
+ */
+void DebugMon_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles PendSVC exception.
+ * @param none
+ * @retval none
+ */
+void PendSV_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles SysTick Handler.
+ * @param none
+ * @retval none
+ */
+void SysTick_Handler(void)
+{
+}
+
+/******************************************************************************/
+/* GW1NS4C Peripherals Interrupt Handlers */
+/* Add here the Interrupt Handler for the used peripheral(s) (XXX), for the */
+/* available peripheral interrupt handler's name please refer to the startup */
+/* file (startup_gw1ns4c.s). */
+/******************************************************************************/
+
+/**
+ * @brief This function handles USER INT0 interrupt request.
+ * @param none
+ * @retval none
+ */
+void USER_INT0_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles USER INT1 interrupt request.
+ * @param none
+ * @retval none
+ */
+void USER_INT1_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles USER INT2 interrupt request.
+ * @param none
+ * @retval none
+ */
+void USER_INT2_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles USER INT3 interrupt request.
+ * @param none
+ * @retval none
+ */
+void USER_INT3_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles USER INT4 interrupt request.
+ * @param none
+ * @retval none
+ */
+void USER_INT4_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles USER INT5 interrupt request.
+ * @param none
+ * @retval none
+ */
+void USER_INT5_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles UART0 interrupt request.
+ * @param none
+ * @retval none
+ */
+void UART0_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles UART1 interrupt request.
+ * @param none
+ * @retval none
+ */
+void UART1_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles TIMER0 interrupt request.
+ * @param none
+ * @retval none
+ */
+void TIMER0_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles TIMER1 interrupt request.
+ * @param none
+ * @retval none
+ */
+void TIMER1_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles I2C interrupt request.
+ * @param none
+ * @retval none
+ */
+void I2C_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles RTC interrupt request.
+ * @param none
+ * @retval none
+ */
+void RTC_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_0 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_0_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_1 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_1_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_2 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_2_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_3 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_3_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_4 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_4_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_5 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_5_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_6 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_6_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_7 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_7_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_8 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_8_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_9 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_9_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_10 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_10_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_11 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_11_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_12 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_12_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_13 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_13_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_14 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_14_Handler(void)
+{
+}
+
+/**
+ * @brief This function handles GPIO0_15 interrupt request.
+ * @param none
+ * @retval none
+ */
+void PORT0_15_Handler(void)
+{
+}
+
+/**
+ * @}
+ */
+
+/*************************GowinSemiconductor*****END OF FILE*********************/
diff --git a/USER/gw1ns4c_it.h b/USER/gw1ns4c_it.h
new file mode 100644
index 0000000..3cc1017
--- /dev/null
+++ b/USER/gw1ns4c_it.h
@@ -0,0 +1,80 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_it.h
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @brief This file contains the headers of the interrupt handlers.
+ ******************************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GW1NS4C_IT_H
+#define __GW1NS4C_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c.h"
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions ------------------------------------------------------- */
+
+/* Core Exceptions Handler */
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+/* StdPeriph Interrupts Handler */
+void USER_INT0_Handler(void);
+void USER_INT1_Handler(void);
+void USER_INT2_Handler(void);
+void USER_INT3_Handler(void);
+void USER_INT4_Handler(void);
+void USER_INT5_Handler(void);
+void UART0_Handler(void);
+void UART1_Handler(void);
+void TIMER0_Handler(void);
+void TIMER1_Handler(void);
+void I2C_Handler(void);
+void RTC_Handler(void);
+void PORT0_0_Handler(void);
+void PORT0_1_Handler(void);
+void PORT0_2_Handler(void);
+void PORT0_3_Handler(void);
+void PORT0_4_Handler(void);
+void PORT0_5_Handler(void);
+void PORT0_6_Handler(void);
+void PORT0_7_Handler(void);
+void PORT0_8_Handler(void);
+void PORT0_9_Handler(void);
+void PORT0_10_Handler(void);
+void PORT0_11_Handler(void);
+void PORT0_12_Handler(void);
+void PORT0_13_Handler(void);
+void PORT0_14_Handler(void);
+void PORT0_15_Handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GW1NS4C_IT_H */
+
+/*************************GowinSemiconductor*****END OF FILE*********************/
diff --git a/USER/main.c b/USER/main.c
new file mode 100644
index 0000000..8a9a632
--- /dev/null
+++ b/USER/main.c
@@ -0,0 +1,43 @@
+
+/* Includes ------------------------------------------------------------------*/
+#include "gw1ns4c.h"
+
+/* Declarations ------------------------------------------------------------------*/
+void delay_ms(__IO uint32_t delay_ms);
+void GPIOInit(void);
+
+/* Functions ------------------------------------------------------------------*/
+int main(void)
+{
+ SystemInit(); //Initializes system
+ GPIOInit(); //Initializes GPIO
+ printf("hello UwU");
+ while(1)
+ {
+ GPIO_ResetBit(GPIO0,GPIO_Pin_0); //LED1 on
+ delay_ms(500);
+
+ GPIO_SetBit(GPIO0,GPIO_Pin_0); //LED1 off
+ delay_ms(500);
+ }
+}
+
+//Initializes GPIO
+void GPIOInit(void)
+{
+ GPIO_InitTypeDef GPIO_InitType;
+
+ GPIO_InitType.GPIO_Pin = GPIO_Pin_0;
+ GPIO_InitType.GPIO_Mode = GPIO_Mode_OUT;
+ GPIO_InitType.GPIO_Int = GPIO_Int_Disable;
+
+ GPIO_Init(GPIO0,&GPIO_InitType);
+
+ GPIO_SetBit(GPIO0,GPIO_Pin_0);
+}
+
+//delay ms
+void delay_ms(__IO uint32_t delay_ms)
+{
+ for(delay_ms=(SystemCoreClock>>13)*delay_ms; delay_ms != 0; delay_ms--);
+}
diff --git a/gw1ns4c_flash.ld b/gw1ns4c_flash.ld
new file mode 100644
index 0000000..0b46842
--- /dev/null
+++ b/gw1ns4c_flash.ld
@@ -0,0 +1,142 @@
+/*
+ * *****************************************************************************************
+ *
+ * Copyright (C) 2014-2021 Gowin Semiconductor Technology Co.,Ltd.
+ *
+ * @file gw1ns4c_flash.ld
+ * @author Embedded Development Team
+ * @version V1.x.x
+ * @date 2021-01-01 09:00:00
+ * @Target GowinSemiconductor GW1NS-4C
+ * @Environment GOWIN MCU Designer
+ * @Description Linker script for GW1NS-4C Device with 32K-Byte FLASH, 16K-Byte RAM
+ * Set heap size, stack size and stack location according to application
+ * requirements.
+ * Set memory bank area and size if external memory is used.
+ ******************************************************************************************
+ */
+
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32KByte */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16KByte */
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ *(.init)
+ *(.fini)
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ *(.eh_frame*)
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ *(.preinit_array)
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ *(SORT(.init_array.*))
+ *(.init_array)
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
+
+/*************************GowinSemiconductor*****END OF FILE*********************/