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Blackfin: initial set of models
Signed-off-by: Mike Frysinger <[email protected]>
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‎MAINTAINERS‎

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@@ -226,6 +226,7 @@ Blackfin
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M: Mike Frysinger <[email protected]>
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S: Maintained
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F: target/bfin/
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F: hw/bfin/
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CRIS TCG CPUs
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M: Edgar E. Iglesias <[email protected]>

‎hw/bfin/bfin_boards.c‎

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/*
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* Blackfin board models
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*
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* Copyright 2007-2023 Mike Frysinger
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* Copyright 2007-2011 Analog Devices, Inc.
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*
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* Licensed under the Lesser GPL 2 or later.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "hw/bfin/bfin_uart.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "hw/sysbus.h"
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#include "chardev/char-fe.h"
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#include "sysemu/sysemu.h"
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#include "exec/address-spaces.h"
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#include "migration/vmstate.h"
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struct bfin_memory_layout {
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hwaddr addr;
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ram_addr_t len;
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const char *name;
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};
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#define LAYOUT(_addr, _len, _name) { .addr = _addr, .len = _len, .name = _name, }
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static const struct bfin_memory_layout bf537_mem[] =
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{
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LAYOUT(0xFF800000, 0x4000, "L1 Data A"),
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LAYOUT(0xFF804000, 0x4000, "Data A Cache"),
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LAYOUT(0xFF900000, 0x4000, "Data B"),
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LAYOUT(0xFF904000, 0x4000, "Data B Cache"),
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LAYOUT(0xFFA00000, 0x8000, "Inst A"),
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LAYOUT(0xFFA08000, 0x4000, "Inst B"),
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LAYOUT(0xFFA10000, 0x4000, "Inst Cache"),
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LAYOUT(0, 0, "SDRAM"),
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};
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static void bfin_memory_init(const struct bfin_memory_layout mem_layout[],
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MachineState *machine)
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{
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *mem;
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size_t i;
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for (i = 0; mem_layout[i].len; ++i) {
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mem = g_new(MemoryRegion, 1);
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memory_region_init_ram(mem, NULL, mem_layout[i].name, mem_layout[i].len,
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&error_abort);
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memory_region_add_subregion(address_space_mem, mem_layout[i].addr, mem);
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}
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mem = g_new(MemoryRegion, 1);
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memory_region_init_ram(mem, NULL, mem_layout[i].name, machine->ram_size,
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&error_abort);
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memory_region_add_subregion(address_space_mem, mem_layout[i].addr, mem);
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/* Address space reserved for on-chip (system) devices */
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//mem = g_new(MemoryRegion, 1);
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//memory_region_init_io(mem, NULL, NULL, "System MMRs", 0x200000);
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//memory_region_add_subregion(address_space_mem, 0xFFC00000, mem);
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/* Address space reserved for on-chip (core) devices */
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//mem = g_new(MemoryRegion, 1);
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/* TODO: This should be owned by the CPU. */
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//memory_region_init_io(mem, NULL, NULL, "Core MMRs", 0x200000);
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//memory_region_add_subregion(address_space_mem, 0xFFE00000, mem);
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}
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static void bfin_device_init(void)
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{
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/* Core peripherals */
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sysbus_create_simple("bfin_mmu", 0xFFE00000, NULL);
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sysbus_create_simple("bfin_evt", 0xFFE02000, NULL);
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sysbus_create_simple("bfin_trace", 0xFFE06000, NULL);
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/* System peripherals */
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/* XXX: BF537-specific */
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sysbus_create_simple("bfin_pll", 0xFFC00000, NULL);
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sysbus_create_simple("bfin_sic", 0xFFC00100, NULL);
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bfin_uart_init(0xFFC00400, serial_hd(0));
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bfin_uart_init(0xFFC02000, serial_hd(1));
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}
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static void bfin_common_init(const struct bfin_memory_layout mem_layout[],
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MachineState *machine)
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{
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const char *kernel_filename = machine->kernel_filename;
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CPUState *cs;
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int n;
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bfin_memory_init(mem_layout, machine);
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bfin_device_init();
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for (n = 0; n < 1 /*TODO: smp_cpus*/; n++) {
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cs = CPU(BFIN_CPU(cpu_create(machine->cpu_type)));
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if (cs == NULL) {
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fprintf(stderr, "Unable to find CPU definition!\n");
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exit(1);
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}
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}
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if (kernel_filename) {
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uint64_t entry = 0;
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const char *kernel_cmdline = machine->kernel_cmdline;
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long kernel_size;
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/* TODO: Not SMP safe. */
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CPUArchState *env;
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BlackfinCPU *cpu;
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cs = first_cpu;
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cpu = BFIN_CPU(cs);
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env = &cpu->env;
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kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &entry, NULL,
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NULL, NULL, 0, ELF_MACHINE, 0, 0);
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if (kernel_size < 0) {
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kernel_size = load_image_targphys(kernel_filename, 0, machine->ram_size);
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}
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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env->pc = entry;
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if (kernel_cmdline) {
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pstrcpy_targphys("cmdline", kernel_size, -1, kernel_cmdline);
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}
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}
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}
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static void bf537_stamp_init(MachineState *machine)
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{
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bfin_common_init(bf537_mem, machine);
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}
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static void bf537_stamp_machine_init(MachineClass *mc)
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{
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mc->desc = "Analog Devices Blackfin ADSP-BF537 STAMP";
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mc->init = bf537_stamp_init;
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mc->max_cpus = 1;
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mc->default_cpu_type = BLACKFIN_CPU_TYPE_NAME("bf537");
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mc->default_ram_size = 64 * MiB;
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mc->default_ram_id = "ram";
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mc->is_default = 1;
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}
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DEFINE_MACHINE("bf537-stamp", bf537_stamp_machine_init)
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static void bf537_ezkit_machine_init(MachineClass *mc)
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{
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mc->desc = "Analog Devices Blackfin ADSP-BF537 EZ-KIT";
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mc->init = bf537_stamp_init;
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mc->max_cpus = 1;
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mc->default_cpu_type = BLACKFIN_CPU_TYPE_NAME("bf537");
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mc->default_ram_size = 64 * MiB;
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mc->default_ram_id = "ram";
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}
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DEFINE_MACHINE("bf537-ezkit", bf537_ezkit_machine_init)

‎hw/bfin/bfin_devices.h‎

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/*
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* Common Blackfin device model code
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*
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* Copyright 2007-2023 Mike Frysinger
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* Copyright 2007-2011 Analog Devices, Inc.
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*
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* Licensed under the Lesser GPL 2 or later.
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*/
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#ifndef BFIN_DEVICES_H
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#define BFIN_DEVICES_H
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#define mmr_size() (sizeof(BfinMMRState) - mmr_base())
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#define mmr_offset(mmr) (offsetof(BfinMMRState, mmr) - mmr_base())
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#define mmr_idx(mmr) (mmr_offset(mmr) / 4)
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#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
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#define HW_TRACE_WRITE() \
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trace_bfin_reg_memory_write(addr + s->iomem.addr, mmr_name(addr), size, \
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value)
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#define HW_TRACE_READ() \
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trace_bfin_reg_memory_read(addr + s->iomem.addr, mmr_name(addr), size)
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typedef int16_t bs16;
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typedef int32_t bs32;
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typedef uint16_t bu16;
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typedef uint32_t bu32;
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#define BFIN_MMR_16(mmr) mmr, __pad_##mmr
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#endif

‎hw/bfin/bfin_dma.c‎

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/*
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* Blackfin Direct Memory Access (DMA) Channel model.
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*
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* Copyright 2007-2023 Mike Frysinger
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* Copyright 2007-2011 Analog Devices, Inc.
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*
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* Licensed under the Lesser GPL 2 or later.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "trace-root.h"
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#include "bfin_devices.h"
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#define TYPE_BFIN_DMA "bfin_dma"
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#define BFIN_DMA(obj) OBJECT_CHECK(BfinDMAState, (obj), TYPE_BFIN_DMA)
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typedef struct BfinDMAState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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/* Order after here is important -- matches hardware MMR layout. */
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union {
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struct { bu16 ndpl, ndph; };
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bu32 next_desc_ptr;
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};
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union {
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struct { bu16 sal, sah; };
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bu32 start_addr;
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};
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bu16 BFIN_MMR_16 (config);
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bu32 _pad0;
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bu16 BFIN_MMR_16 (x_count);
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bs16 BFIN_MMR_16 (x_modify);
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bu16 BFIN_MMR_16 (y_count);
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bs16 BFIN_MMR_16 (y_modify);
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bu32 curr_desc_ptr, curr_addr;
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bu16 BFIN_MMR_16 (irq_status);
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bu16 BFIN_MMR_16 (peripheral_map);
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bu16 BFIN_MMR_16 (curr_x_count);
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bu32 _pad1;
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bu16 BFIN_MMR_16 (curr_y_count);
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bu32 _pad2;
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} BfinDMAState;
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#define BfinMMRState BfinDMAState
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#define mmr_base() offsetof(BfinMMRState, next_desc_ptr)
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static const char * const mmr_names[] =
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{
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"NEXT_DESC_PTR", "START_ADDR", "CONFIG", "<INV>", "X_COUNT", "X_MODIFY",
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"Y_COUNT", "Y_MODIFY", "CURR_DESC_PTR", "CURR_ADDR", "IRQ_STATUS",
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"PERIPHERAL_MAP", "CURR_X_COUNT", "<INV>", "CURR_Y_COUNT", "<INV>",
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};
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static void bfin_dma_io_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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BfinDMAState *s = opaque;
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HW_TRACE_WRITE();
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}
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static uint64_t bfin_dma_io_read(void *opaque, hwaddr addr, unsigned size)
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{
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BfinDMAState *s = opaque;
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HW_TRACE_READ();
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return 0;
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}
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static const MemoryRegionOps bfin_dma_io_ops = {
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.read = bfin_dma_io_read,
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.write = bfin_dma_io_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 2,
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.max_access_size = 4,
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},
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};
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static void bfin_dma_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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BfinDMAState *s = BFIN_DMA(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), &bfin_dma_io_ops, s, "dma", mmr_size());
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void bfin_dma_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = bfin_dma_realize;
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}
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static TypeInfo bfin_dma_info = {
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.name = "bfin_dma",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(BfinDMAState),
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.class_init = bfin_dma_class_init,
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};
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static void bfin_dma_register_types(void)
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{
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type_register_static(&bfin_dma_info);
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}
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type_init(bfin_dma_register_types)

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