make test more complex

Author: gussmith23

passes/techmap/lakeroad.cc

@@ -120,7 +120,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN
 	read_verilog_args.push_back(out_verilog_filename);
 	Pass::call(design, read_verilog_args);
 
-	log("Replacing module %s with the output of Lakeroad", top_module_name.c_str());
+	log("Replacing module %s with the output of Lakeroad\n", top_module_name.c_str());
 	design->remove(module);
 	auto new_module = design->module(RTLIL::escape_id(temp_module_name));
 	if (new_module == nullptr)

tests/techmap/lakeroad.ys

@@ -4,27 +4,35 @@
 read_verilog << EOT
   (* template = "dsp",
      architecture = "xilinx-ultrascale-plus",
-     initiation_interval = 1 *)
+     initiation_interval = 2 *)
   module test (
       (* data *) 
-      input [7:0] a,
+      input [17:0] a,
       (* data *)
-      input [7:0] b,
+      input [17:0] b,
+      (* data *)
+      input [17:0] c,
+      (* data *)
+      input [17:0] d,
       (* clk *)
       input clk,
       (* out *)
-      output [7:0] o);
+      output [17:0] o);
 
-    reg [7:0] r0;
-    always @ (posedge clk)
-      r0 <= a*b;
-    assign o = r0;
+    reg [17:0] r0;
+    reg [17:0] r1;
+    always @ (posedge clk) begin
+      r0 <= (d+a)*b&c;
+      r1 <= r0;
+    end
+    assign o = r1;
 
   endmodule
 EOT
 
 # Call Lakeroad pass.
 lakeroad
 
-# Ensure that one DSP has been instantiated.
-select -assert-count 1 */t:DSP48E2
+# Ensure there's exactly one cell, and that that cell is a DSP48E2.
+select -assert-count 1 */t:*
+select -assert-count 1 */t:DSP48E2