dpu: llvm & clang: remove builtin dpu_seqread_get

The builtin lowering is ill-formed with arithmetic+comp+branch instruction.
Emit a splitted version in EmitInstrWithCustomInserter to recombine later
is too complicated.

This commit revert to what it was before, a simple function call in the runtime library.

This revert the followings:

"dpu: llvm: seqread_get: force incr to be a positive signed char to be optimized"
This reverts commit cfc4828

"dpu: llvm: enumerate every nc condition to convert pageSizeLog2"
This reverts commit 3c67e43.

"dpu: llvm & clang: add builtin dpu_seqread_get"
This reverts commit 301a2e2

Author: wwolff42

clang/include/clang/Basic/BuiltinsDPU.def

@@ -17,6 +17,5 @@
 BUILTIN(__builtin_dpu_tid, "UiC", "nc")
 BUILTIN(__builtin_dpu_sdma, "vvC*v*Ui", "")
 BUILTIN(__builtin_dpu_ldma, "vv*vC*Ui", "")
-BUILTIN(__builtin_dpu_seqread_get, "iiUiv*UiC", "")
 
 #undef BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

@@ -17372,17 +17372,6 @@ Value *CodeGenFunction::EmitDPUBuiltinExpr(unsigned BuiltinID,
     Value *Arg2 = EmitScalarExpr(E->getArg(2));
     return Builder.CreateCall(Callee, {Arg0, Arg1, Arg2});
   }
-  case DPU::BI__builtin_dpu_seqread_get: {
-    llvm::Type *ResultType = ConvertType(E->getType());
-    Value *ArgPtr = EmitScalarExpr(E->getArg(0));
-    Value *ArgInc = EmitScalarExpr(E->getArg(1));
-    Value *ArgReader = EmitPointerWithAlignment(E->getArg(2)).getPointer();
-    Value *ArgPageSize = EmitScalarExpr(E->getArg(3));
-
-    llvm::Function *Callee =
-        CGM.getIntrinsic(Intrinsic::dpu_seqread_get, ResultType);
-    return Builder.CreateCall(Callee, {ArgPtr, ArgInc, ArgReader, ArgPageSize});
-  }
 
   default:
     return nullptr;

llvm/include/llvm/IR/IntrinsicsDPU.td

@@ -22,6 +22,4 @@ def int_dpu_ldma : Intrinsic<[], [llvm_wram_ptr_ty, llvm_mram_ptr_ty, llvm_i32_t
 def int_dpu_sdma_unchecked : Intrinsic<[], [llvm_wram_ptr_ty, llvm_wram_ptr_ty, llvm_i32_ty], [IntrHasSideEffects, ReadOnly<ArgIndex<0>>, WriteOnly<ArgIndex<1>>, Throws]>;
 def int_dpu_ldma_unchecked : Intrinsic<[], [llvm_wram_ptr_ty, llvm_wram_ptr_ty, llvm_i32_ty], [IntrHasSideEffects, ReadOnly<ArgIndex<1>>, WriteOnly<ArgIndex<0>>, Throws]>;
 
-def int_dpu_seqread_get : Intrinsic<[llvm_anyint_ty], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty], [IntrHasSideEffects]>;
-
 }

llvm/lib/Target/DPU/DPUISelLowering.h

@@ -157,9 +157,6 @@ enum {
   LDMA,
   SDMA,
 
-  SEQREAD_GET,
-  SEQREAD_GET_CST,
-
   LHU_BIG,
   LHS_BIG,
   LW_BIG,

llvm/lib/Target/DPU/DPUInstrInfo.td

@@ -58,10 +58,6 @@ def SDT_DMA  : SDTypeProfile<0, 3, [SDTCisInt<2>, SDTCisVT<0, iPTR>, SDTCisVT<1,
 def SDT_Ldma : SDNode<"DPUISD::LDMA", SDT_DMA, [SDNPHasChain]>;
 def SDT_Sdma : SDNode<"DPUISD::SDMA", SDT_DMA, [SDNPHasChain]>;
 
-def SDT_SEQREAD_GET : SDTypeProfile<1, 5, [SDTCisInt<0>, SDTCisInt<1>, SDTCisVT<2, iPTR>, SDTCisInt<3>, SDTCisInt<4>]>;
-def DPUSeqreadGet : SDNode<"DPUISD::SEQREAD_GET", SDT_SEQREAD_GET, [SDNPHasChain]>;
-def DPUSeqreadGetCst : SDNode<"DPUISD::SEQREAD_GET_CST", SDT_SEQREAD_GET, [SDNPHasChain]>;
-
 // To promote special types of operands to registers (see the patterns below).
 def SDTDPUWrapper       : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
 def DPUWrapper          : SDNode<"DPUISD::Wrapper", SDTDPUWrapper>;
@@ -77,20 +73,6 @@ def DPULdBig : SDNode <"DPUISD::LD_BIG", SDT_DPULoadBig, [SDNPHasChain, SDNPMayL
 
 include "DPUInstrFormats.td"
 
-let usesCustomInserter = 1 in {
-def SEQREAD_GET: PseudoDPUInstruction<
-    (outs SimpleReg:$rc),
-    (ins SimpleReg:$ptr, SimpleReg:$inc, SimpleReg:$reader, i32imm:$cc, i32imm:$pageSize),
-    "",
-    [(set i32:$rc, (DPUSeqreadGet i32:$ptr, i32:$inc, i32:$reader, (i32 imm:$cc), (i32 imm:$pageSize)))]>;
-
-def SEQREAD_GET_CST: PseudoDPUInstruction<
-    (outs SimpleReg:$rc),
-    (ins SimpleReg:$ptr, s8_imm:$inc, SimpleReg:$reader, i32imm:$cc, i32imm:$pageSize),
-    "",
-    [(set i32:$rc, (DPUSeqreadGetCst i32:$ptr, (s8_imm:$inc), i32:$reader, (i32 imm:$cc), (i32 imm:$pageSize)))]>;
-}
-
 def ADD_VAStart: PseudoDPUInstruction<
                     (outs SimpleReg:$rc), (ins SimpleReg:$ra),
                     "",

llvm/lib/Target/DPU/DPUTargetLowering.cpp

@@ -405,10 +405,6 @@ const char *DPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch (Opcode) {
   default:
     return nullptr;
-  case DPUISD::SEQREAD_GET:
-    return "DPUISD::SEQREAD_GET";
-  case DPUISD::SEQREAD_GET_CST:
-    return "DPUISD::SEQREAD_GET_CST";
   case DPUISD::LHU_BIG:
     return "DPUISD::LHU_BIG";
   case DPUISD::LHS_BIG:
@@ -1848,15 +1844,13 @@ SDValue DPUTargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG,
   }
 }
 
-static uint64_t FormatDMASize(uint64_t size) { return (size >> 3) - 1; }
-
 SDValue DPUTargetLowering::LowerDMAUnchecked(
     SelectionDAG &DAG, const SDLoc &dl, const EVT &evt, SDValue Chain,
     SDValue ra, SDValue rb, SDValue Size, bool CanFetchConstant,
     uint64_t Length, int DPUISD) const {
 
   if (CanFetchConstant) {
-    Size = DAG.getConstant(FormatDMASize(Length), dl, MVT::i32);
+    Size = DAG.getConstant((Length >> 3) - 1, dl, MVT::i32);
   } else {
     const EVT &raVT = ra.getValueType();
     // to + (((nb_of_bytes >> 3) - 1) << 24);
@@ -1907,71 +1901,6 @@ SDValue DPUTargetLowering::LowerDMA(SDValue Op, SelectionDAG &DAG,
                            CanFetchConstant, size, DPUISD);
 }
 
-static uint64_t PageSizeLog2ToNcCondition(uint64_t pageSize) {
-  switch (pageSize) {
-  case 5:
-    return DPUAsmCondition::NotCarry5;
-  case 6:
-    return DPUAsmCondition::NotCarry6;
-  case 7:
-    return DPUAsmCondition::NotCarry7;
-  case 8:
-    return DPUAsmCondition::NotCarry8;
-  case 9:
-    return DPUAsmCondition::NotCarry9;
-  case 10:
-    return DPUAsmCondition::NotCarry10;
-  case 11:
-    return DPUAsmCondition::NotCarry11;
-  case 12:
-    return DPUAsmCondition::NotCarry12;
-  case 13:
-    return DPUAsmCondition::NotCarry13;
-  case 14:
-    return DPUAsmCondition::NotCarry14;
-  default:
-    return DPUAsmCondition::NR_CONDITIONS;
-  }
-}
-
-SDValue DPUTargetLowering::LowerSeqreadGet(SDValue Op,
-                                           SelectionDAG &DAG) const {
-  SDLoc dl(Op);
-  SDValue incValue = Op.getOperand(3);
-  SDValue pageSizeValue = Op.getOperand(5);
-  uint64_t pageSize, pageSizeLog2, inc;
-  if (!canFetchConstantTo(pageSizeValue, &pageSize)) {
-    LowerUnsupported(
-        Op, DAG, "NC only apply on constant and staticaly defined page size");
-  }
-  pageSizeLog2 = (uint64_t)log2((double)pageSize);
-  if (pageSize != ((uint64_t)pow(2, (double)pageSizeLog2)) ||
-      pageSizeLog2 < 5 || pageSizeLog2 > 14) {
-    LowerUnsupported(
-        Op, DAG,
-        "NC only apply on a page size of a power of 2 in range [64;32768]");
-  }
-
-  int Opcode = DPUISD::SEQREAD_GET;
-  SDValue cond =
-      DAG.getConstant(PageSizeLog2ToNcCondition(pageSizeLog2), dl, MVT::i32);
-  if (canFetchConstantTo(incValue, &inc) && (inc > 0) && (inc < 128)) {
-    Opcode = DPUISD::SEQREAD_GET_CST;
-    incValue = DAG.getConstant(inc, dl, MVT::i32);
-  }
-
-  SmallVector<EVT, 2> ResTys;
-
-  for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
-       I != E; ++I)
-    ResTys.push_back(*I);
-
-  SDValue Ops[] = {
-      Op.getOperand(0), Op.getOperand(2), incValue, Op.getOperand(4), cond,
-      pageSizeValue};
-  return DAG.getNode(Opcode, dl, ResTys, Ops);
-}
-
 SDValue DPUTargetLowering::LowerIntrinsic(SDValue Op, SelectionDAG &DAG,
                                           int IntrinsicType) const {
   SDLoc dl(Op);
@@ -1992,12 +1921,6 @@ SDValue DPUTargetLowering::LowerIntrinsic(SDValue Op, SelectionDAG &DAG,
     }
     break;
   case ISD::INTRINSIC_W_CHAIN:
-    switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
-    case Intrinsic::dpu_seqread_get: {
-      result = LowerSeqreadGet(Op, DAG);
-      break;
-    }
-    }
     break;
   case ISD::INTRINSIC_VOID:
     switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
@@ -3134,92 +3057,12 @@ static MachineBasicBlock *EmitClz64WithCustomInserter(MachineInstr &MI,
   return endMBB;
 }
 
-static MachineBasicBlock *EmitSeqreadGet(MachineInstr &MI,
-                                         MachineBasicBlock *BB, bool IsIncCst) {
-  const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
-  DebugLoc dl = MI.getDebugLoc();
-  const BasicBlock *LLVM_BB = BB->getBasicBlock();
-  MachineFunction::iterator I = ++BB->getIterator();
-  MachineFunction *F = BB->getParent();
-  MachineBasicBlock *slowMBB = F->CreateMachineBasicBlock(LLVM_BB);
-  MachineBasicBlock *fastMBB = F->CreateMachineBasicBlock(LLVM_BB);
-  F->insert(I, slowMBB);
-  F->insert(I, fastMBB);
-  // Update machine-CFG edges by transferring all successors of the current
-  // block to the new block which will contain the Phi node for the select.
-  fastMBB->splice(fastMBB->begin(), BB,
-                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
-  fastMBB->transferSuccessorsAndUpdatePHIs(BB);
-  // Next, add the true and fallthrough blocks as its successors.
-  BB->addSuccessor(slowMBB);
-  BB->addSuccessor(fastMBB);
-  slowMBB->addSuccessor(fastMBB);
-
-  unsigned int Dest = MI.getOperand(0).getReg();
-  unsigned int PtrInit = MI.getOperand(1).getReg();
-  unsigned int Reader = MI.getOperand(3).getReg();
-  unsigned int Cond = MI.getOperand(4).getImm();
-  unsigned int PageSize = MI.getOperand(5).getImm();
-
-  MachineRegisterInfo &RI = F->getRegInfo();
-  unsigned int PtrIncremented = RI.createVirtualRegister(&DPU::GP_REGRegClass);
-
-  if (IsIncCst) {
-    BuildMI(BB, dl, TII.get(DPU::ADDrrici), PtrIncremented)
-        .addReg(PtrInit)
-        .addImm(MI.getOperand(2).getImm())
-        .addImm(Cond)
-        .addMBB(fastMBB);
-  } else {
-    BuildMI(BB, dl, TII.get(DPU::ADDrrrci), PtrIncremented)
-        .addReg(PtrInit)
-        .addReg(MI.getOperand(2).getReg())
-        .addImm(Cond)
-        .addMBB(fastMBB);
-  }
-
-  unsigned int WramCache = RI.createVirtualRegister(&DPU::GP_REGRegClass);
-  unsigned int MramCache = RI.createVirtualRegister(&DPU::GP_REGRegClass);
-  unsigned int MramCacheUpdated =
-      RI.createVirtualRegister(&DPU::GP_REGRegClass);
-  unsigned int PtrUpdated = RI.createVirtualRegister(&DPU::GP_REGRegClass);
-  BuildMI(slowMBB, dl, TII.get(DPU::LWrri), MramCache).addReg(Reader).addImm(4);
-  BuildMI(slowMBB, dl, TII.get(DPU::ADDrri), MramCacheUpdated)
-      .addReg(MramCache)
-      .addImm(PageSize);
-  BuildMI(slowMBB, dl, TII.get(DPU::SWrir))
-      .addReg(Reader)
-      .addImm(4)
-      .addReg(MramCacheUpdated);
-  BuildMI(slowMBB, dl, TII.get(DPU::LWrri), WramCache).addReg(Reader).addImm(0);
-  BuildMI(slowMBB, dl, TII.get(DPU::LDMArri))
-      .addReg(WramCache)
-      .addReg(MramCacheUpdated)
-      .addImm(FormatDMASize(PageSize * 2));
-  BuildMI(slowMBB, dl, TII.get(DPU::ADDrri), PtrUpdated)
-      .addReg(PtrIncremented)
-      .addImm(-PageSize);
-
-  BuildMI(*fastMBB, fastMBB->begin(), dl, TII.get(TargetOpcode::PHI), Dest)
-      .addReg(PtrIncremented)
-      .addMBB(BB)
-      .addReg(PtrUpdated)
-      .addMBB(slowMBB);
-
-  MI.eraseFromParent(); // The pseudo instruction is gone now.
-  return fastMBB;
-}
-
 MachineBasicBlock *
 DPUTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
                                                MachineBasicBlock *BB) const {
   switch (MI.getOpcode()) {
   default:
     llvm_unreachable("Unexpected instr type to insert");
-  case DPU::SEQREAD_GET:
-    return EmitSeqreadGet(MI, BB, false);
-  case DPU::SEQREAD_GET_CST:
-    return EmitSeqreadGet(MI, BB, true);
   case DPU::Mul16UUrr:
     return EmitMul16WithCustomInserter(MI, BB, DPU::MUL_UL_ULrrrci,
                                        DPU::MUL_UH_ULrrr, DPU::MUL_UH_ULrrr,

llvm/lib/Target/DPU/DPUTargetLowering.h

@@ -121,8 +121,6 @@ class DPUTargetLowering : public TargetLowering {
 
   SDValue LowerDMA(SDValue Op, SelectionDAG &DAG, int DPUISD) const;
 
-  SDValue LowerSeqreadGet(SDValue Op, SelectionDAG &DAG) const;
-
   SDValue LowerIntrinsic(SDValue Op, SelectionDAG &DAG,
                          int IntrinsicType) const;