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AsmMigration.cpp
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//===----------------------- AsmMigration.cpp -------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "AsmMigration.h"
#include "AnalysisInfo.h"
#include "Diagnostics/Diagnostics.h"
#include "ErrorHandle/CrashRecovery.h"
#include "RuleInfra/MapNames.h"
#include "RulesAsm/Parser/AsmNodes.h"
#include "RulesAsm/Parser/AsmParser.h"
#include "RulesAsm/Parser/AsmTokenKinds.h"
#include "TextModification.h"
#include "Utility.h"
#include "clang/AST/Expr.h"
#include "clang/AST/Stmt.h"
#include "clang/Basic/TokenKinds.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/Sequence.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/FormatVariadic.h"
#include "llvm/Support/SaveAndRestore.h"
#include "llvm/Support/raw_ostream.h"
#include <cstdio>
using namespace clang;
using namespace clang::dpct;
namespace {
inline bool SYCLGenError() { return true; }
inline bool SYCLGenSuccess() { return false; }
/// This is used to handle all the AST nodes (except specific instructions, Eg.
/// mov/setp), and generate functionally equivalent SYCL code.
class SYCLGenBase {
bool IsInMacroDef = false;
bool EmitNewLine = true;
bool EmitSemi = true;
unsigned NumIndent = 0;
SmallString<4> IndentUnit{" "};
SmallString<16> Indent;
SmallString<4> NewLine;
SmallVector<SmallString<10>, 4> VecExprTypeRecord;
raw_ostream *Stream;
InlineAsmContext &Context;
bool MigrationStopped = false;
protected:
const InlineAsmInstruction *CurrInst = nullptr;
const GCCAsmStmt *GAS;
class BlockDelimiterGuard {
SYCLGenBase &CodeGen;
public:
BlockDelimiterGuard(SYCLGenBase &CG) : CodeGen(CG) {
CodeGen.OS() << "{";
CodeGen.endl();
CodeGen.incIndent();
}
~BlockDelimiterGuard() {
CodeGen.decIndent();
CodeGen.indent();
CodeGen.OS() << "}";
CodeGen.endl();
}
};
struct EnterEmitVectorExpressionContext {
SYCLGenBase &CodeGen;
bool ShouldEnter;
EnterEmitVectorExpressionContext(SYCLGenBase &CodeGen, StringRef Type,
bool ShouldEnter = true)
: CodeGen(CodeGen), ShouldEnter(ShouldEnter) {
if (ShouldEnter)
CodeGen.VecExprTypeRecord.push_back(Type);
}
~EnterEmitVectorExpressionContext() {
if (ShouldEnter)
CodeGen.VecExprTypeRecord.pop_back();
}
};
template <typename IDTy, typename... Ts>
inline void report(IDTy MsgID, bool UseTextBegin, Ts &&...Vals) {
TransformSetTy TS;
auto SL = GAS->getBeginLoc();
DiagnosticsUtils::report<IDTy, Ts...>(SL, MsgID, &TS, UseTextBegin,
std::forward<Ts>(Vals)...);
for (auto &T : TS)
DpctGlobalInfo::getInstance().addReplacement(
T->getReplacement(DpctGlobalInfo::getContext()));
}
public:
SYCLGenBase(llvm::raw_ostream &OS, InlineAsmContext &Ctx, const GCCAsmStmt *G)
: Stream(&OS), Context(Ctx), GAS(G) {}
virtual ~SYCLGenBase() = default;
unsigned getNumIndent() const { return NumIndent; }
void setIndentUnit(StringRef Unit) {
if (!Unit.empty())
IndentUnit = Unit;
}
void setInMacroDefine() { IsInMacroDef = true; }
bool isInMacroDefine() const { return IsInMacroDef; }
void decIndent(unsigned Num = 1) {
if (NumIndent >= Num) {
NumIndent -= Num;
for (unsigned I = 0; I < Num; ++I)
Indent.pop_back_n(IndentUnit.size());
} else {
NumIndent = 0;
Indent.clear();
}
}
void incIndent(unsigned Num = 1) {
NumIndent += Num;
for (unsigned I = 0; I < Num; ++I)
Indent.append(IndentUnit);
}
void cutOffMigration() { MigrationStopped = true; }
bool isMigrationStopped() const { return MigrationStopped; }
protected:
void indent() { OS() << Indent; }
void endl() {
if (EmitNewLine) {
if (NewLine.empty()) {
if (isInMacroDefine())
NewLine.append("\\");
NewLine.append(getNL());
}
OS() << NewLine;
}
}
void semi() {
if (EmitSemi)
OS() << ";";
}
void endstmt() {
if (EmitSemi)
OS() << ";";
endl();
}
void insertHeader(HeaderType HT) const {
DpctGlobalInfo::getInstance().insertHeader(GAS->getBeginLoc(), HT);
}
llvm::raw_ostream &OS() { return *Stream; }
void switchOutStream(llvm::raw_ostream &NewOS) { Stream = &NewOS; }
bool tryEmitStmt(std::string &Buffer, const InlineAsmStmt *S) {
llvm::raw_string_ostream TmpOS(Buffer);
llvm::SaveAndRestore<llvm::raw_ostream *> OutStream(Stream);
switchOutStream(TmpOS);
if (emitStmt(S))
return SYCLGenError();
TmpOS.flush();
return SYCLGenSuccess();
}
bool tryEmitType(std::string &Buffer, const InlineAsmType *T) {
llvm::raw_string_ostream TmpOS(Buffer);
llvm::SaveAndRestore<llvm::raw_ostream *> OutStream(Stream);
switchOutStream(TmpOS);
if (emitType(T))
return SYCLGenError();
TmpOS.flush();
return SYCLGenSuccess();
}
bool tryEmitAllInputOperands(MutableArrayRef<std::string> Ops,
const InlineAsmInstruction *Inst) {
for (unsigned I = 0, E = Inst->getNumInputOperands(); I != E; ++I)
if (tryEmitStmt(Ops[I], Inst->getInputOperand(I)))
return SYCLGenError();
return SYCLGenSuccess();
}
bool needBitCast(const InlineAsmType *From, const InlineAsmType *To) {
if (From == To)
return false;
if (const auto *BIFrom = dyn_cast<InlineAsmBuiltinType>(From),
*BITo = dyn_cast<InlineAsmBuiltinType>(To);
BIFrom->isScalar() && BITo->isScalar())
return false;
return true;
}
bool emitBitCast(const InlineAsmType *From, const InlineAsmType *To,
std::string &Val) {
assert(needBitCast(From, To) && "Bit cast is unnecessary");
std::string Buffer;
llvm::raw_string_ostream TmpOS(Buffer);
llvm::SaveAndRestore<llvm::raw_ostream *> OutStream(Stream);
switchOutStream(TmpOS);
std::string FromT, ToT;
if (tryEmitType(FromT, From))
return SYCLGenError();
if (tryEmitType(ToT, To))
return SYCLGenError();
auto isVecTy = [&](const InlineAsmType *Ty) {
if (isa<InlineAsmVectorType>(Ty))
return true;
const auto *BI = dyn_cast<InlineAsmBuiltinType>(Ty);
return BI && BI->isVector();
};
if (isVecTy(From))
OS() << Val;
else
OS() << MapNames::getClNamespace() << "vec<" << FromT << ", 1>(" << Val
<< ')';
OS() << ".template as<";
if (isVecTy(To))
OS() << ToT << ">()";
else
OS() << MapNames::getClNamespace() << "vec<" << ToT << ", 1>>().x()";
Val = std::move(Buffer);
return SYCLGenSuccess();
}
// Types
bool emitType(const InlineAsmType *T);
bool emitBuiltinType(const InlineAsmBuiltinType *T);
bool emitVectorType(const InlineAsmVectorType *T);
// Declarations
bool emitDeclaration(const InlineAsmDecl *D);
bool emitVariableDeclaration(const InlineAsmVarDecl *D);
// Statements && Expressions
bool emitStmt(const InlineAsmStmt *S);
bool emitCompoundStmt(const InlineAsmCompoundStmt *S);
bool emitDeclStmt(const InlineAsmDeclStmt *S);
bool emitInstruction(const InlineAsmInstruction *I);
bool emitConditionalInstruction(const InlineAsmConditionalInstruction *I);
bool emitUnaryOperator(const InlineAsmUnaryOperator *Op);
bool emitBinaryOperator(const InlineAsmBinaryOperator *Op);
bool emitConditionalOperator(const InlineAsmConditionalOperator *Op);
bool emitVectorExpr(const InlineAsmVectorExpr *E);
bool emitDiscardExpr(const InlineAsmDiscardExpr *E) { return SYCLGenError(); }
bool emitAddressExpr(const InlineAsmAddressExpr *E);
bool emitCastExpr(const InlineAsmCastExpr *E);
bool emitParenExpr(const InlineAsmParenExpr *E);
bool emitDeclRefExpr(const InlineAsmDeclRefExpr *E);
bool emitIntegerLiteral(const InlineAsmIntegerLiteral *I);
bool emitFloatingLiteral(const InlineAsmFloatingLiteral *Fp);
// Instructions
#define INSTRUCTION(X) \
virtual bool handle_##X(const InlineAsmInstruction *I) { \
return SYCLGenError(); \
}
#include "RulesAsm/Parser/AsmTokenKinds.def"
};
bool SYCLGenBase::emitStmt(const InlineAsmStmt *S) {
switch (S->getStmtClass()) {
#define STMT(CLASS, PARENT) \
case InlineAsmStmt::CLASS##Class: \
return emit##CLASS(dyn_cast<InlineAsm##CLASS>(S));
#define ABSTRACT_STMT(STMT)
#include "RulesAsm/Parser/AsmNodes.def"
}
return SYCLGenError();
}
bool SYCLGenBase::emitDeclStmt(const InlineAsmDeclStmt *S) {
if (S->getNumDecl() == 0)
return SYCLGenError();
if (S->getDeclSpec().Alignment) {
OS() << "alignas(";
OS() << S->getDeclSpec().Alignment->getValue().getZExtValue();
OS() << ") ";
}
if (emitType(S->getDeclSpec().Type))
return SYCLGenError();
OS() << " ";
int NumCommas = S->getNumDecl() - 1;
for (const auto *D : S->decls()) {
if (emitDeclaration(D))
return SYCLGenError();
if (NumCommas-- > 0)
OS() << ", ";
}
endstmt();
return SYCLGenSuccess();
}
bool SYCLGenBase::emitCompoundStmt(const InlineAsmCompoundStmt *S) {
llvm::SaveAndRestore<bool> StoreEndl(EmitNewLine);
llvm::SaveAndRestore<bool> StoreSemi(EmitSemi);
EmitNewLine = true;
EmitSemi = true;
BlockDelimiterGuard Guard(*this);
for (const auto *SubStmt : S->stmts()) {
indent();
if (emitStmt(SubStmt))
return SYCLGenError();
}
return SYCLGenSuccess();
}
bool SYCLGenBase::emitInstruction(const InlineAsmInstruction *I) {
switch (I->getOpcodeID()->getTokenID()) {
#define INSTRUCTION(X) \
case asmtok::op_##X: \
return handle_##X(I);
#include "RulesAsm/Parser/AsmTokenKinds.def"
default:
break;
}
return SYCLGenError();
}
bool SYCLGenBase::emitConditionalInstruction(
const InlineAsmConditionalInstruction *I) {
OS() << "if (";
if (I->hasNot())
OS() << "!";
if (emitStmt(I->getPred()))
return SYCLGenError();
OS() << ") ";
BlockDelimiterGuard Guard(*this);
indent();
return emitInstruction(I->getInstruction());
}
bool SYCLGenBase::emitUnaryOperator(const InlineAsmUnaryOperator *Op) {
switch (Op->getOpcode()) {
// clang-format off
case InlineAsmUnaryOperator::Plus: OS() << "+"; break;
case InlineAsmUnaryOperator::Minus: OS() << "-"; break;
case InlineAsmUnaryOperator::Not: OS() << "~"; break;
case InlineAsmUnaryOperator::LNot: OS() << "!"; break;
// clang-format on
}
return emitStmt(Op->getSubExpr());
}
bool SYCLGenBase::emitBinaryOperator(const InlineAsmBinaryOperator *Op) {
if (emitStmt(Op->getLHS()))
return SYCLGenError();
OS() << " ";
// clang-format off
switch (Op->getOpcode()) {
case InlineAsmBinaryOperator::Mul: OS() << "*"; break;
case InlineAsmBinaryOperator::Div: OS() << "/"; break;
case InlineAsmBinaryOperator::Rem: OS() << "%"; break;
case InlineAsmBinaryOperator::Add: OS() << "+"; break;
case InlineAsmBinaryOperator::Sub: OS() << "-"; break;
case InlineAsmBinaryOperator::Shl: OS() << "<<"; break;
case InlineAsmBinaryOperator::Shr: OS() << ">>"; break;
case InlineAsmBinaryOperator::LT: OS() << "<"; break;
case InlineAsmBinaryOperator::GT: OS() << ">"; break;
case InlineAsmBinaryOperator::LE: OS() << "<="; break;
case InlineAsmBinaryOperator::GE: OS() << ">="; break;
case InlineAsmBinaryOperator::EQ: OS() << "=="; break;
case InlineAsmBinaryOperator::NE: OS() << "!="; break;
case InlineAsmBinaryOperator::And: OS() << "&"; break;
case InlineAsmBinaryOperator::Xor: OS() << "^"; break;
case InlineAsmBinaryOperator::Or: OS() << "|"; break;
case InlineAsmBinaryOperator::LAnd: OS() << "&&"; break;
case InlineAsmBinaryOperator::LOr: OS() << "||"; break;
case InlineAsmBinaryOperator::Assign: OS() << "="; break;
}
// clang-format on
OS() << " ";
return emitStmt(Op->getRHS());
}
bool SYCLGenBase::emitConditionalOperator(
const InlineAsmConditionalOperator *Op) {
if (emitStmt(Op->getCond()))
return SYCLGenError();
OS() << " ? ";
if (emitStmt(Op->getLHS()))
return SYCLGenError();
OS() << " : ";
return emitStmt(Op->getRHS());
}
bool SYCLGenBase::emitCastExpr(const InlineAsmCastExpr *E) {
OS() << "static_cast<";
if (emitType(E->getType()))
return SYCLGenError();
OS() << ">(";
if (emitStmt(E->getSubExpr()))
return SYCLGenError();
OS() << ")";
return SYCLGenSuccess();
}
bool SYCLGenBase::emitParenExpr(const InlineAsmParenExpr *E) {
OS() << "(";
if (emitStmt(E->getSubExpr()))
return SYCLGenError();
OS() << ")";
return SYCLGenSuccess();
}
bool SYCLGenBase::emitDeclRefExpr(const InlineAsmDeclRefExpr *E) {
auto *VD = dyn_cast_or_null<InlineAsmVarDecl>(&E->getDecl());
if (!VD)
return SYCLGenError();
if (VD->getDeclName()->isSpecialReg()) {
switch (VD->getDeclName()->getTokenID()) {
case asmtok::bi_laneid:
OS() << DpctGlobalInfo::getItem(GAS)
<< ".get_sub_group().get_local_linear_id()";
break;
case asmtok::bi_warpid:
OS() << DpctGlobalInfo::getItem(GAS)
<< ".get_sub_group().get_group_linear_id()";
break;
case asmtok::bi_WARP_SZ:
OS() << DpctGlobalInfo::getItem(GAS)
<< ".get_sub_group().get_local_range().get(0)";
break;
default:
return SYCLGenError();
}
return SYCLGenSuccess();
}
OS() << VD->getDeclName()->getName();
if (E->hasParameterizedName()) {
OS() << '[' << E->getParameterizedNameIndex() << ']';
}
return SYCLGenSuccess();
}
bool SYCLGenBase::emitIntegerLiteral(const InlineAsmIntegerLiteral *I) {
OS() << I->getLiteral();
return SYCLGenSuccess();
}
bool SYCLGenBase::emitFloatingLiteral(const InlineAsmFloatingLiteral *Fp) {
if (!Fp->isExactMachineFloatingLiteral()) {
OS() << Fp->getLiteral();
} else {
std::string Fmt =
MapNames::getClNamespace() + "bit_cast<{0}>({1}(0x{2}{3}))";
if (const auto *T = dyn_cast<InlineAsmBuiltinType>(Fp->getType())) {
switch (T->getKind()) {
case InlineAsmBuiltinType::f32:
OS() << llvm::formatv(Fmt.c_str(), "float", "uint32_t",
Fp->getLiteral(), "U");
break;
case InlineAsmBuiltinType::f64:
OS() << llvm::formatv(Fmt.c_str(), "double", "uint64_t",
Fp->getLiteral(), "ULL");
break;
default:
return SYCLGenError();
}
return SYCLGenSuccess();
}
}
return SYCLGenSuccess();
}
bool SYCLGenBase::emitVectorExpr(const InlineAsmVectorExpr *E) {
if (!VecExprTypeRecord.empty())
OS() << VecExprTypeRecord.back();
OS() << "{";
unsigned NumCommas = E->getNumElements() - 1;
for (const auto *Element : E->elements()) {
if (emitStmt(Element))
return SYCLGenError();
if (NumCommas) {
OS() << ", ";
NumCommas--;
}
}
OS() << "}";
return SYCLGenSuccess();
}
bool SYCLGenBase::emitType(const InlineAsmType *T) {
switch (T->getTypeClass()) {
case InlineAsmType::BuiltinClass:
return emitBuiltinType(dyn_cast<InlineAsmBuiltinType>(T));
case InlineAsmType::VectorClass:
return emitVectorType(dyn_cast<InlineAsmVectorType>(T));
default:
break;
}
return SYCLGenError();
}
bool SYCLGenBase::emitBuiltinType(const InlineAsmBuiltinType *T) {
switch (T->getKind()) {
// clang-format off
case InlineAsmBuiltinType::b8: OS() << "uint8_t"; break;
case InlineAsmBuiltinType::b16: OS() << "uint16_t"; break;
case InlineAsmBuiltinType::b32: OS() << "uint32_t"; break;
case InlineAsmBuiltinType::b64: OS() << "uint64_t"; break;
case InlineAsmBuiltinType::u8: OS() << "uint8_t"; break;
case InlineAsmBuiltinType::u16: OS() << "uint16_t"; break;
case InlineAsmBuiltinType::u32: OS() << "uint32_t"; break;
case InlineAsmBuiltinType::u64: OS() << "uint64_t"; break;
case InlineAsmBuiltinType::s8: OS() << "int8_t"; break;
case InlineAsmBuiltinType::s16: OS() << "int16_t"; break;
case InlineAsmBuiltinType::s32: OS() << "int32_t"; break;
case InlineAsmBuiltinType::s64: OS() << "int64_t"; break;
case InlineAsmBuiltinType::f16: OS() << MapNames::getClNamespace() + "half"; break;
case InlineAsmBuiltinType::f32: OS() << "float"; break;
case InlineAsmBuiltinType::f64: OS() << "double"; break;
case InlineAsmBuiltinType::byte: OS() << "uint8_t"; break;
// case InlineAsmBuiltinType::4byte: OS() << "uint32_t"; break;
case InlineAsmBuiltinType::pred: OS() << "bool"; break;
case InlineAsmBuiltinType::s16x2: OS() << MapNames::getClNamespace() + "short2"; break;
case InlineAsmBuiltinType::u16x2: OS() << MapNames::getClNamespace() + "ushort2"; break;
case InlineAsmBuiltinType::bf16: OS() << MapNames::getClNamespace() + "ext::oneapi::bfloat16"; break;
case InlineAsmBuiltinType::f16x2: OS() << MapNames::getClNamespace() + "half2"; break;
case InlineAsmBuiltinType::e4m3:
case InlineAsmBuiltinType::e5m2:
case InlineAsmBuiltinType::tf32:
case InlineAsmBuiltinType::bf16x2:
case InlineAsmBuiltinType::e4m3x2:
case InlineAsmBuiltinType::e5m2x2:
[[fallthrough]];
default:
return SYCLGenError();
}
// clang-format on
return SYCLGenSuccess();
}
bool SYCLGenBase::emitVectorType(const InlineAsmVectorType *T) {
OS() << MapNames::getClNamespace() << "vec<";
if (emitType(T->getElementType()))
return SYCLGenError();
OS() << ", ";
switch (T->getKind()) {
case InlineAsmVectorType::v2:
OS() << 2;
break;
case InlineAsmVectorType::v4:
OS() << 4;
break;
case InlineAsmVectorType::v8:
OS() << 8;
break;
}
OS() << ">";
return SYCLGenSuccess();
}
bool SYCLGenBase::emitDeclaration(const InlineAsmDecl *D) {
switch (D->getDeclClass()) {
case InlineAsmDecl::VariableDeclClass:
return emitVariableDeclaration(dyn_cast<InlineAsmVarDecl>(D));
default:
break;
}
return SYCLGenError();
}
bool SYCLGenBase::emitVariableDeclaration(const InlineAsmVarDecl *D) {
OS() << D->getDeclName()->getName();
if (D->isParameterizedNameDecl())
OS() << '[' << D->getNumParameterizedNames() << ']';
return SYCLGenSuccess();
}
bool SYCLGenBase::emitAddressExpr(const InlineAsmAddressExpr *Dst) {
// Address expression only support ld/st/red & atom instructions.
if (!CurrInst ||
!CurrInst->is(asmtok::op_st, asmtok::op_ld, asmtok::op_atom,
asmtok::op_prefetch, asmtok::op_red, asmtok::op_cp)) {
return SYCLGenError();
}
std::string Type;
if (tryEmitType(Type, CurrInst->getType(0)))
return SYCLGenError();
auto CanSuppressCast = [&](InlineAsmDeclRefExpr *DRE) {
auto *VD = dyn_cast<InlineAsmVarDecl>(&Dst->getSymbol()->getDecl());
if (VD->getInlineAsmOp()) {
if (const auto *Ptr = dyn_cast<PointerType>(
VD->getInlineAsmOp()->getType().getTypePtr())) {
return Context.getTypeFromClangType(
Ptr->getPointeeType().getTypePtr()) == CurrInst->getType(0);
}
}
return false;
};
if (CurrInst->is(asmtok::op_ld, asmtok::op_red))
OS() << "*";
switch (Dst->getMemoryOpKind()) {
case InlineAsmAddressExpr::Imm:
OS() << llvm::formatv("(({0} *)(uintptr_t){1})", Type,
Dst->getImmAddr()->getValue().getZExtValue());
break;
case InlineAsmAddressExpr::Reg: {
std::string Reg;
if (tryEmitStmt(Reg, Dst->getSymbol()))
return SYCLGenSuccess();
if (CurrInst->is(asmtok::op_prefetch, asmtok::op_red) ||
CanSuppressCast(Dst->getSymbol()))
OS() << llvm::formatv("{0}", Reg);
else
OS() << llvm::formatv("(({0} *)(uintptr_t){1})", Type, Reg);
break;
}
case InlineAsmAddressExpr::RegImm: {
std::string Reg;
if (tryEmitStmt(Reg, Dst->getSymbol()))
return SYCLGenSuccess();
if (CurrInst->is(asmtok::op_st))
OS() << llvm::formatv("(uintptr_t){0}", Reg);
else
OS() << llvm::formatv("(({0} *)((uintptr_t){1} + {2}))", Type, Reg,
Dst->getImmAddr()->getValue().getZExtValue());
break;
}
case InlineAsmAddressExpr::Var: {
std::string Reg;
if (tryEmitStmt(Reg, Dst->getSymbol()))
return SYCLGenSuccess();
if (CanSuppressCast(Dst->getSymbol()))
OS() << llvm::formatv("{0}", Reg);
else
OS() << llvm::formatv("(({0} *)&{1})", Type, Reg);
break;
}
case InlineAsmAddressExpr::VarImm: {
std::string Reg;
if (tryEmitStmt(Reg, Dst->getSymbol()))
return SYCLGenSuccess();
OS() << llvm::formatv("(({0} *)((uintptr_t)&{1} + {2}))", Type, Reg,
Dst->getImmAddr()->getValue().getZExtValue());
break;
}
}
return SYCLGenSuccess();
}
/// This used to handle the specific instruction.
class SYCLGen : public SYCLGenBase {
public:
SYCLGen(llvm::raw_ostream &OS, InlineAsmContext &Ctx, const GCCAsmStmt *G)
: SYCLGenBase(OS, Ctx, G) {}
bool handleStatement(const InlineAsmStmt *S) { return emitStmt(S); }
protected:
unsigned getBitSizeTypeWidth(const InlineAsmBuiltinType *T) const {
switch (T->getKind()) {
case InlineAsmBuiltinType::b8:
return 8;
case InlineAsmBuiltinType::b16:
return 16;
case InlineAsmBuiltinType::b32:
return 32;
case InlineAsmBuiltinType::b64:
return 64;
default:
return 0;
}
}
const char *unpackBitSizeType(const InlineAsmBuiltinType *T,
unsigned N) const {
assert(T->isBit());
unsigned OriginTypeWidth = getBitSizeTypeWidth(T);
unsigned UnpackTypeWidth = OriginTypeWidth / N;
switch (UnpackTypeWidth) {
case 8:
return "uint8_t";
case 16:
return "uint16_t";
case 32:
return "uint32_t";
default:
return nullptr;
}
}
bool handle_mov(const InlineAsmInstruction *I) override {
if (I->getNumInputOperands() != 1)
return SYCLGenError();
// Handle data unpack mov.
// mov.b32 {%0, %1}, %2;
// %0 = sycl::vec<uint32_t, 1>(%2).template as<sycl::vec<uint16_t, 2>>()[0];
// %1 = sycl::vec<uint32_t, 1>(%2).template as<sycl::vec<uint16_t, 2>>()[1];
if (const auto *VE = dyn_cast<InlineAsmVectorExpr>(I->getOutputOperand())) {
const auto *Type =
llvm::dyn_cast_or_null<InlineAsmBuiltinType>(I->getType(0));
if (!Type || !Type->isBit())
return SYCLGenError();
std::string OriginType, InputOp;
std::string UnpackType = unpackBitSizeType(Type, VE->getNumElements());
if (tryEmitType(OriginType, Type) ||
tryEmitStmt(InputOp, I->getInputOperand(0)))
return SYCLGenError();
std::string SYCLVec;
{
llvm::raw_string_ostream TmpOS(SYCLVec);
TmpOS << MapNames::getClNamespace() << "vec<" << OriginType << ", 1>("
<< InputOp << ").template as<" << MapNames::getClNamespace()
<< "vec<" << UnpackType << ", " << VE->getNumElements() << ">>()";
}
for (unsigned I = 0, E = VE->getNumElements(); I != E; ++I) {
if (isa<InlineAsmDiscardExpr>(VE->getElement(I)))
continue;
if (I > 0)
indent();
if (emitStmt(VE->getElement(I)))
return SYCLGenError();
OS() << " = " << SYCLVec << '[' << I << ']';
endstmt();
}
} else if (const auto *VE =
dyn_cast<InlineAsmVectorExpr>(I->getInputOperand(0))) {
// Handle data pack ov.
// mov.b32 %0, {%1, %2};
// %0 = sycl::vec<uint16_t, 2>{%1, %2}.template as<sycl::vec<uint32_t,
// 1>>()[0];
const auto *Type =
llvm::dyn_cast_or_null<InlineAsmBuiltinType>(I->getType(0));
if (!Type || !Type->isBit())
return SYCLGenError();
std::string PackType, OutputOp;
std::string OriginType = unpackBitSizeType(Type, VE->getNumElements());
if (tryEmitType(PackType, Type))
return SYCLGenError();
if (emitStmt(I->getOutputOperand()))
return SYCLGenError();
OS() << " = " << MapNames::getClNamespace() << "vec<" << OriginType
<< ", " << VE->getNumElements() << ">(";
if (emitStmt(VE))
return SYCLGenError();
OS() << ").template as<" << MapNames::getClNamespace() << "vec<"
<< PackType << ", 1>>()[0]";
endstmt();
} else {
if (emitStmt(I->getOutputOperand()))
return SYCLGenError();
OS() << " = ";
if (emitStmt(I->getInputOperand(0)))
return SYCLGenError();
endstmt();
}
return SYCLGenSuccess();
}
bool handle_setp(const InlineAsmInstruction *I) override {
if (I->getNumInputOperands() != 2 && I->getNumInputOperands() == 1)
return SYCLGenError();
auto *T = dyn_cast<InlineAsmBuiltinType>(I->getType(0));
if (!T)
return SYCLGenError();
if (emitStmt(I->getOutputOperand()))
return SYCLGenError();
OS() << " = ";
std::string Op[2];
for (int i = 0; i < 2; ++i)
if (tryEmitStmt(Op[i], I->getInputOperand(i)))
return SYCLGenError();
std::string TypeStr;
if (tryEmitType(TypeStr, I->getType(0)))
return SYCLGenError();
auto ExprCmp = [&](StringRef BinOp) {
OS() << Op[0] << ' ' << BinOp << ' ' << Op[1];
};
auto DpctCmp = [&](const char *Fmt) {
OS() << MapNames::getDpctNamespace()
<< llvm::formatv(Fmt, TypeStr, Op[0], Op[1]);
};
bool IsInteger = T->isInt() || T->isBit();
for (const auto A : I->attrs()) {
switch (A) {
case InstAttr::eq:
if (IsInteger)
ExprCmp("==");
else if (T->isFloat())
DpctCmp("compare<{0}>({1}, {2}, std::equal_to<>())");
else
return SYCLGenError();
break;
case InstAttr::ne:
if (IsInteger)
ExprCmp("!=");
else if (T->isFloat())
DpctCmp("compare<{0}>({1}, {2}, std::not_equal_to<>())");
else
return SYCLGenError();
break;
case InstAttr::lt:
if (IsInteger)
ExprCmp("<");
else if (T->isFloat())
DpctCmp("compare<{0}>({1}, {2}, std::less<>())");
else
return SYCLGenError();
break;
case InstAttr::le:
if (IsInteger)
ExprCmp("<=");
else if (T->isFloat())
DpctCmp("compare<{0}>({1}, {2}, std::less_equal<>())");
else
return SYCLGenError();
break;
case InstAttr::gt:
if (IsInteger)
ExprCmp(">");
else if (T->isFloat())
DpctCmp("compare<{0}>({1}, {2}, std::greater<>())");
else
return SYCLGenError();
break;
case InstAttr::ge:
if (IsInteger)
ExprCmp(">=");
else if (T->isFloat())
DpctCmp("compare<{0}>({1}, {2}, std::greater_equal<>())");
else
return SYCLGenError();
break;
case InstAttr::lo:
if (T->isUnsigned())
ExprCmp("<");
else
return SYCLGenError();
break;
case InstAttr::ls:
if (T->isUnsigned())
ExprCmp("<=");
else
return SYCLGenError();
break;
case InstAttr::hi:
if (T->isUnsigned())
ExprCmp(">");
else
return SYCLGenError();
break;
case InstAttr::hs:
if (T->isUnsigned())
ExprCmp(">=");
else
return SYCLGenError();
break;
case InstAttr::equ:
if (T->isFloat())
DpctCmp("unordered_compare<{0}>({1}, {2}, std::equal_to<>())");
else
return SYCLGenError();
break;
case InstAttr::neu:
if (T->isFloat())
DpctCmp("unordered_compare<{0}>({1}, {2}, std::not_equal_to<>())");
else
return SYCLGenError();
break;
case InstAttr::ltu:
if (T->isFloat())
DpctCmp("unordered_compare<{0}>({1}, {2}, std::less<>())");
else
return SYCLGenError();
break;
case InstAttr::leu:
if (T->isFloat())
DpctCmp("unordered_compare<{0}>({1}, {2}, std::less_equal<>())");
else
return SYCLGenError();
break;
case InstAttr::gtu:
if (T->isFloat())
DpctCmp("unordered_compare<{0}>({1}, {2}, std::greater<>())");
else
return SYCLGenError();
break;
case InstAttr::geu:
if (T->isFloat())
DpctCmp("unordered_compare<{0}>({1}, {2}, std::greater_equal<>())");
else
return SYCLGenError();
break;
case InstAttr::num:
if (T->isFloat()) {
OS() << '!' << MapNames::getClNamespace();
OS() << "isnan(" << Op[0] << ")";
OS() << " && ";
OS() << '!' << MapNames::getClNamespace();
OS() << "isnan(" << Op[1] << ")";
} else
return SYCLGenError();
break;
case InstAttr::nan:
if (T->isFloat()) {
OS() << MapNames::getClNamespace();
OS() << "isnan(" << Op[0] << ")";
OS() << " || ";
OS() << MapNames::getClNamespace();
OS() << "isnan(" << Op[1] << ")";
} else
return SYCLGenError();
break;
default:
break;
}
}
endstmt();
return SYCLGenSuccess();
}
bool handle_lop3(const InlineAsmInstruction *I) override {
if (I->getNumInputOperands() != 4 || I->getNumTypes() != 1 ||
!isa<InlineAsmBuiltinType>(I->getType(0)) ||
dyn_cast<InlineAsmBuiltinType>(I->getType(0))->getKind() !=
InlineAsmBuiltinType::b32)
return SYCLGenError();
if (emitStmt(I->getOutputOperand()))
return SYCLGenError();
OS() << " = ";
std::string Op[4];
for (auto Idx : llvm::seq(0, 4)) {
if (tryEmitStmt(Op[Idx], I->getInputOperand(Idx)))
return SYCLGenError();
}
if (!isa<InlineAsmIntegerLiteral>(I->getInputOperand(3))) {
OS() << MapNames::getDpctNamespace() << "ternary_logic_op(" << Op[0]
<< ", " << Op[1] << ", " << Op[2] << ", " << Op[3] << ")";
} else {
unsigned Imm = dyn_cast<InlineAsmIntegerLiteral>(I->getInputOperand(3))
->getValue()
.getZExtValue();
#define EMPTY nullptr
#define EMPTY4 EMPTY, EMPTY, EMPTY, EMPTY
#define EMPTY16 EMPTY4, EMPTY4, EMPTY4, EMPTY4
constexpr const char *FastMap[256] = {
/*0x00*/ "0",
// clang-format off
EMPTY16, EMPTY4, EMPTY4, EMPTY,
/*0x1a*/ "({0} & {1} | {2}) ^ {0}",
EMPTY, EMPTY, EMPTY,
/*0x1e*/ "{0} ^ ({1} | {2})",
EMPTY4, EMPTY4, EMPTY4, EMPTY, EMPTY,
/*0x2d*/ "~{0} ^ (~{1} & {2})",
EMPTY16, EMPTY, EMPTY,
/*0x40*/ "{0} & {1} & ~{2}",
EMPTY16, EMPTY16, EMPTY16, EMPTY4, EMPTY, EMPTY, EMPTY,
/*0x78*/ "{0} ^ ({1} & {2})",
EMPTY4, EMPTY, EMPTY, EMPTY,
/*0x80*/ "{0} & {1} & {2}",
EMPTY16, EMPTY4, EMPTY,
/*0x96*/ "{0} ^ {1} ^ {2}",
EMPTY16, EMPTY4, EMPTY4, EMPTY4, EMPTY,
/*0xb4*/ "{0} ^ ({1} & ~{2})",
EMPTY, EMPTY, EMPTY,
/*0xb8*/ "({0} ^ ({1} & ({2} ^ {0})))",
EMPTY16, EMPTY4, EMPTY4, EMPTY,
/*0xd2*/ "{0} ^ (~{1} & {2})",
EMPTY16, EMPTY4, EMPTY,
/*0xe8*/ "(({0} & ({1} | {2})) | ({1} & {2}))",
EMPTY,
/*0xea*/ "({0} & {1}) | {2}",
EMPTY16, EMPTY, EMPTY, EMPTY,
/*0xfe*/ "{0} | {1} | {2}",