Rotation, swap, multiply files added

Author: tom2238

Diff for: src/alu_top.vhd

@@ -217,6 +217,70 @@ begin
         Y_o => rs_not
     );    
 
+    -- Rotace vpravo
+    RS_RR_COM: entity work.rotate_right
+    port map (
+       -- vstup
+       A_i => number_a_i,
+       C_i => carry_i,
+       -- vystup
+       Y_o => rs_rr,
+       C_o => rs_rr_c
+    );
+    
+    -- Rotace vlevo
+    RS_RL_COM: entity work.rotate_left
+    port map (
+       -- vstup
+       A_i => number_a_i,
+       C_i => carry_i,
+       -- vystup
+       Y_o => rs_rl,
+       C_o => rs_rl_c
+    );
+    
+    -- Rotace vpravo s prenosem
+    RS_RRC_COM: entity work.rotate_right_with_carry
+    port map (
+       -- vstup
+       A_i => number_a_i,
+       C_i => carry_i,
+       -- vystup
+       Y_o => rs_rrc,
+       C_o => rs_rrc_c
+    );
+    
+    -- Rotace vlevo s prenosem
+    RS_RLC_COM: entity work.rotate_left_with_carry
+    port map (
+       -- vstup
+       A_i => number_a_i,
+       C_i => carry_i,
+       -- vystup
+       Y_o => rs_rlc,
+       C_o => rs_rlc_c
+    );
+    
+    -- Prehozeni bitu
+    RS_SWAP_COM: entity work.bitswap
+    port map (
+       -- vstup
+       A_i => number_a_i,
+       -- vystup
+       Y_o => rs_swap
+    );   
+    
+    -- Nasobeni
+    RS_MUL_COM: entity work.multiply
+    port map (
+       -- vstup
+       A_i => number_a_i,
+       B_i => number_b_i,
+       -- vystup
+       Y_o => rs_mul,
+       C_o => rs_mul_c
+    );
+    
     -- Mux , vyber z vysledku z operace
     with control_sig_i select
         alu_result <= rs_plus when x"0",

Diff for: src/bitswap.vhd

@@ -0,0 +1,38 @@
+--------------------------------------------------------------------------------
+-- Brno University of Technology, Department of Radio Electronics
+--------------------------------------------------------------------------------
+-- Author: Tomas Dubina
+-- Date: 2019-02-14 07:44
+-- Design: bitswap
+-- Description: bitswap
+--------------------------------------------------------------------------------
+-- TODO: 
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+--------------------------------------------------------------------------------
+-- Entity declaration for bitswap
+--------------------------------------------------------------------------------
+entity bitswap is
+    port(
+        -- Entity input signals
+        A_i : in std_logic_vector(3 downto 0);     -- input 
+
+        -- Entity output signals
+        Y_o : out std_logic_vector(3 downto 0)    -- output 
+    );
+end bitswap;
+
+--------------------------------------------------------------------------------
+-- Architecture declaration for bitswap
+--------------------------------------------------------------------------------     
+architecture Behavioral of bitswap is
+
+begin
+
+Y_o(3 downto 2) <= A_i(1 downto 0);
+Y_o(1 downto 0) <= A_i(3 downto 2);
+
+end Behavioral;

Diff for: src/multiply.vhd

@@ -0,0 +1,39 @@
+--------------------------------------------------------------------------------
+-- Brno University of Technology, Department of Radio Electronics
+--------------------------------------------------------------------------------
+-- Author: Tomáš Dubina
+-- Date: 2019-02-14 07:44
+-- Design: multiply
+-- Description: MUL operation, Y = A * B
+--------------------------------------------------------------------------------
+-- TODO: all
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+--------------------------------------------------------------------------------
+-- Entity declaration for multiply
+--------------------------------------------------------------------------------
+entity multiply is
+    port(
+        -- Entity input signals
+        A_i : in std_logic_vector(3 downto 0);     
+        B_i : in std_logic_vector(3 downto 0); 
+        -- Entity output signals
+        Y_o : out std_logic_vector(3 downto 0);
+        C_o : out std_logic    
+    );
+end multiply;
+
+--------------------------------------------------------------------------------
+-- Architecture declaration for multiply
+--------------------------------------------------------------------------------     
+architecture Behavioral of multiply is
+
+begin
+
+
+
+end Behavioral;
+

Diff for: src/rotate_left.vhd

@@ -0,0 +1,41 @@
+--------------------------------------------------------------------------------
+-- Brno University of Technology, Department of Radio Electronics
+--------------------------------------------------------------------------------
+-- Author: Milan hornik
+-- Design: rotate_left
+-- Description: Implementation of <<
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+--------------------------------------------------------------------------------
+-- Entity declaration for rotate_left
+--------------------------------------------------------------------------------
+entity rotate_left is
+    port(
+        -- Global input signals at CPLD expansion board
+		  
+		  A_i : in std_logic_vector(4-1 downto 0);
+		  C_i : in std_logic;
+			
+
+        -- Global output signals at Coolrunner-II board
+
+		  Y_o : out std_logic_vector(4-1 downto 0) ;
+		  C_o : out std_logic
+    );
+end rotate_left;
+
+--------------------------------------------------------------------------------
+-- Architecture declaration for rotate_right
+--------------------------------------------------------------------------------
+architecture Behavioral of rotate_left is
+    
+begin
+
+
+
+ 
+end Behavioral;

Diff for: src/rotate_left_with_carry.vhd

@@ -0,0 +1,41 @@
+--------------------------------------------------------------------------------
+-- Brno University of Technology, Department of Radio Electronics
+--------------------------------------------------------------------------------
+-- Author: Milan hornik
+-- Design: rotate_left_with_carry
+-- Description: Implementation of <<
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+--------------------------------------------------------------------------------
+-- Entity declaration for rotate_left_with_carry
+--------------------------------------------------------------------------------
+entity rotate_left_with_carry is
+    port(
+        -- Global input signals at CPLD expansion board
+		  
+		  A_i : in std_logic_vector(4-1 downto 0);
+		  C_i : in std_logic;
+			
+
+        -- Global output signals at Coolrunner-II board
+
+		  Y_o : out std_logic_vector(4-1 downto 0) ;
+		  C_o : out std_logic
+    );
+end rotate_left_with_carry;
+
+--------------------------------------------------------------------------------
+-- Architecture declaration for rotate_left_with_carry
+--------------------------------------------------------------------------------
+architecture Behavioral of rotate_left_with_carry is
+    
+begin
+
+
+
+ 
+end Behavioral;

Diff for: src/rotate_right.vhd

@@ -0,0 +1,41 @@
+--------------------------------------------------------------------------------
+-- Brno University of Technology, Department of Radio Electronics
+--------------------------------------------------------------------------------
+-- Author: Milan hornik
+-- Design: rotate_right
+-- Description: Implementation of >>
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+--------------------------------------------------------------------------------
+-- Entity declaration for rotate_right
+--------------------------------------------------------------------------------
+entity rotate_right is
+    port(
+        -- Global input signals at CPLD expansion board
+		  
+		  A_i : in std_logic_vector(4-1 downto 0);
+		  C_i : in std_logic;
+			
+
+        -- Global output signals at Coolrunner-II board
+
+		  Y_o : out std_logic_vector(4-1 downto 0) ;
+		  C_o : out std_logic
+    );
+end rotate_right;
+
+--------------------------------------------------------------------------------
+-- Architecture declaration for rotate_right
+--------------------------------------------------------------------------------
+architecture Behavioral of rotate_right is
+    
+begin
+
+
+
+ 
+end Behavioral;

Diff for: src/rotate_right_with_carry.vhd

@@ -0,0 +1,41 @@
+--------------------------------------------------------------------------------
+-- Brno University of Technology, Department of Radio Electronics
+--------------------------------------------------------------------------------
+-- Author: Milan hornik
+-- Design: rotate_right_with_carry
+-- Description: Implementation of >>
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+--------------------------------------------------------------------------------
+-- Entity declaration for rotate_right_with_carry
+--------------------------------------------------------------------------------
+entity rotate_right_with_carry is
+    port(
+        -- Global input signals at CPLD expansion board
+		  
+		  A_i : in std_logic_vector(4-1 downto 0);
+		  C_i : in std_logic;
+			
+
+        -- Global output signals at Coolrunner-II board
+
+		  Y_o : out std_logic_vector(4-1 downto 0) ;
+		  C_o : out std_logic
+    );
+end rotate_right_with_carry;
+
+--------------------------------------------------------------------------------
+-- Architecture declaration for rotate_right_with_carry
+--------------------------------------------------------------------------------
+architecture Behavioral of rotate_right_with_carry is
+    
+begin
+
+
+
+ 
+end Behavioral;