You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Copy file name to clipboardExpand all lines: README.md
+6-4
Original file line number
Diff line number
Diff line change
@@ -82,7 +82,7 @@ module modular_square_simple
82
82
-**sq_out** - The result of the squaring operation. This should be fed back internally to sq_in for repeated squaring. It will be consumed externally at the clock edge trailing the valid signal pulse.
83
83
-**valid** - A one cycle pulse indicating that sq_out is valid.
84
84
85
-
If you have requirements that go beyond this interface, such as loading precomputed values, contact us by email (hello@supranational.net) and we will work with you to determine the best path forward. We are very interested in seeing alternative approaches and algorithms.
85
+
If you have requirements that go beyond this interface, such as loading precomputed values, contact us by email (hello@vdfalliance.org) and we will work with you to determine the best path forward. We are very interested in seeing alternative approaches and algorithms.
86
86
87
87
## Baseline models
88
88
@@ -183,7 +183,7 @@ The following are some potential optimization paths.
183
183
* Shorten the pipeline - we believe a 4-5 cycle pipeline is possible with this design
184
184
* Lengthen the pipeline - insert more pipe stages, run with a faster clock
185
185
* Change the partial product multiplier size. The DSPs are 26x17 bit multipliers and the modular squaring circuit supports using either by changing a define at the top.
186
-
* This design uses lookup tables stored in BlockRAM for the reduction step. These are easy to change to distributed memory and there is support in the model to use UltraRAM. **TODO - point to a branch with this code**
186
+
* This design uses lookup tables stored in BlockRAM for the reduction step. These are easy to change to distributed memory and there is support in the model to use UltraRAM. For an example using UltraRAM see https://github.com/supranational/vdf-fpga/tree/f72eb8c06eec94a09142f675cde8d1514fb72e60
187
187
* Optimize the compression trees and accumulators to make the best use of FPGA LUTs and CARRY8 primitives.
188
188
* Floorplan the design.
189
189
* Use High Level Synthesis (HLS) or other techniques.
@@ -206,5 +206,7 @@ AWS online documentation:
206
206
207
207
## Questions?
208
208
209
-
Please reach out with any questions, comments, or feedback through **TODO - channels**
210
-
209
+
Please reach out with any questions, comments, or feedback through any of the following channels:
0 commit comments