fix: astyle

Author: zfields

variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/variant_CYGNET.cpp

@@ -56,11 +56,11 @@ const PinName digitalPin[] = {
 
 // Analog (Ax) to digital pin number array
 const uint32_t analogInputPin[] = {
-   0,  // PA0, A0
-   1,  // PA1, A1
-   2,  // PA2, A2
-   3,  // PA3, A3
-   4,  // PB1, A4
+  0,   // PA0, A0
+  1,   // PA1, A1
+  2,   // PA2, A2
+  3,   // PA3, A3
+  4,   // PB1, A4
   14,  // PA7, A5
   30   // PA4, A6/BATTERY_VOLTAGE (STAT)
 };
@@ -194,7 +194,7 @@ WEAK void SystemClock_Config(void)
   *   - FLASH_LATENCY: 4 (required for 80 MHz / VOS1 per RM0394 s.3.3)
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE
-                                      | RCC_OSCILLATORTYPE_MSI;
+                                     | RCC_OSCILLATORTYPE_MSI;
   RCC_OscInitStruct.LSEState = RCC_LSE_ON;
   RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
   RCC_OscInitStruct.MSIState = RCC_MSI_ON;
@@ -257,35 +257,35 @@ WEAK void SystemClock_Config(void)
     Error_Handler();
   }
 
-/** Enable MSI Auto calibration (MSIPLLEN, RCC_CR[2])
- *
- * RM0394 s.6.2 (MSI clock): setting MSIPLLEN causes the MSI hardware
- * to automatically trim itself against LSE as a phase reference,
- * reducing MSI frequency error to < +/-0.25%. LSE must already be
- * stable (LSERDY=1) before the bit is set -- guaranteed here because
- * HAL_RCC_OscConfig() waited for LSERDY before returning.
- *
- * Setting MSIPLLEN causes MSIRDY to deassert transiently while MSI
- * re-synchronises to LSE. HAL_RCCEx_EnableMSIPLLMode() returns
- * immediately (it is a single SET_BIT); no MSIRDY wait is performed
- * inside it. Two conclusions follow:
- *
- *   (1) This call must come AFTER any HAL routine that polls MSIRDY
- *       under a HAL_GetTick() timeout -- if MSIRDY drops inside such
- *       a routine, the routine returns HAL_TIMEOUT and leaves the
- *       clock tree in an undefined state.
- *
- *   (2) If SYSCLK were MSI, a deadlock would be possible: MSIRDY
- *       drops -> SysTick stalls -> HAL_GetTick() freezes -> any
- *       subsequent timeout loop never exits. RM0394 s.6.2.9 confirms
- *       SysTick is driven by HCLK (= SYSCLK / AHBdiv). Because
- *       SYSCLK is now PLLCLK (80 MHz), SysTick is completely
- *       decoupled from MSI and the transient is harmless.
- *
- * Placement here -- after PeriphCLKConfig -- satisfies both constraints
- * and mirrors the ordering generated by CubeMX for the Nucleo L432KC.
- */
-HAL_RCCEx_EnableMSIPLLMode();
+  /** Enable MSI Auto calibration (MSIPLLEN, RCC_CR[2])
+   *
+   * RM0394 s.6.2 (MSI clock): setting MSIPLLEN causes the MSI hardware
+   * to automatically trim itself against LSE as a phase reference,
+   * reducing MSI frequency error to < +/-0.25%. LSE must already be
+   * stable (LSERDY=1) before the bit is set -- guaranteed here because
+   * HAL_RCC_OscConfig() waited for LSERDY before returning.
+   *
+   * Setting MSIPLLEN causes MSIRDY to deassert transiently while MSI
+   * re-synchronises to LSE. HAL_RCCEx_EnableMSIPLLMode() returns
+   * immediately (it is a single SET_BIT); no MSIRDY wait is performed
+   * inside it. Two conclusions follow:
+   *
+   *   (1) This call must come AFTER any HAL routine that polls MSIRDY
+   *       under a HAL_GetTick() timeout -- if MSIRDY drops inside such
+   *       a routine, the routine returns HAL_TIMEOUT and leaves the
+   *       clock tree in an undefined state.
+   *
+   *   (2) If SYSCLK were MSI, a deadlock would be possible: MSIRDY
+   *       drops -> SysTick stalls -> HAL_GetTick() freezes -> any
+   *       subsequent timeout loop never exits. RM0394 s.6.2.9 confirms
+   *       SysTick is driven by HCLK (= SYSCLK / AHBdiv). Because
+   *       SYSCLK is now PLLCLK (80 MHz), SysTick is completely
+   *       decoupled from MSI and the transient is harmless.
+   *
+   * Placement here -- after PeriphCLKConfig -- satisfies both constraints
+   * and mirrors the ordering generated by CubeMX for the Nucleo L432KC.
+   */
+  HAL_RCCEx_EnableMSIPLLMode();
 
   /** Ensure that MSI is wake-up system clock
   *

variants/STM32L4xx/L433C(B-C)(T-U)_L443CC(T-U)/variant_CYGNET.h

@@ -100,23 +100,23 @@
 
 // Macro functions for 3V3 regulator management
 #ifndef ENABLE_3V3_REGULATOR
-  #define ENABLE_3V3_REGULATOR()  do { \
-    digitalWrite(DISCHARGE_3V3, DISABLE_DISCHARGING); \
-    digitalWrite(ENABLE_3V3, HIGH); \
-  } while (0)
+#  define ENABLE_3V3_REGULATOR()  do { \
+     digitalWrite(DISCHARGE_3V3, DISABLE_DISCHARGING); \
+     digitalWrite(ENABLE_3V3, HIGH); \
+   } while (0)
 #endif
 #ifndef DISABLE_3V3_REGULATOR
-  #define DISABLE_3V3_REGULATOR() do { \
-    digitalWrite(ENABLE_3V3, LOW); \
-  } while (0)
+#  define DISABLE_3V3_REGULATOR() do { \
+     digitalWrite(ENABLE_3V3, LOW); \
+   } while (0)
 #endif
 #ifndef DRAIN_3V3_REGULATOR_MS
-  #define DRAIN_3V3_REGULATOR_MS(ms) do { \
-    if (digitalRead(ENABLE_3V3)) { break; } \
-    digitalWrite(DISCHARGE_3V3, ENABLE_DISCHARGING); \
-    delay(ms); \
-    digitalWrite(DISCHARGE_3V3, DISABLE_DISCHARGING); \
-  } while (0)
+#  define DRAIN_3V3_REGULATOR_MS(ms) do { \
+     if (digitalRead(ENABLE_3V3)) { break; } \
+     digitalWrite(DISCHARGE_3V3, ENABLE_DISCHARGING); \
+     delay(ms); \
+     digitalWrite(DISCHARGE_3V3, DISABLE_DISCHARGING); \
+   } while (0)
 #endif
 
 // Dedicated board pins
@@ -127,9 +127,9 @@
   #define VMAIN_DIV_K             ((double)((VMAIN_ADC_DIV_TOP_R + VMAIN_ADC_DIV_BOT_R) / VMAIN_ADC_DIV_BOT_R))
 #endif
 #ifndef VMAIN_MV
-  #define VMAIN_MV() ({ \
-    __HAL_ADC_CALC_DATA_TO_VOLTAGE(__LL_ADC_CALC_VREFANALOG_VOLTAGE(analogRead(AVREF), LL_ADC_GetResolution(ADC1)), analogRead(VMAIN_ADC), LL_ADC_GetResolution(ADC1)) * VMAIN_DIV_K; \
-  })
+#  define VMAIN_MV() ({ \
+     __HAL_ADC_CALC_DATA_TO_VOLTAGE(__LL_ADC_CALC_VREFANALOG_VOLTAGE(analogRead(AVREF), LL_ADC_GetResolution(ADC1)), analogRead(VMAIN_ADC), LL_ADC_GetResolution(ADC1)) * VMAIN_DIV_K; \
+   })
 #endif
 #ifndef CHARGE_DETECT
   #define CHARGE_DETECT           PA15