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Store Tx and Rx in Serial.
1 parent e64497b commit 48e737f

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+35
-45
lines changed

1 file changed

+35
-45
lines changed

src/serial.rs

Lines changed: 35 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -208,6 +208,8 @@ impl From<Bps> for Config {
208208
pub struct Serial<USART, PINS> {
209209
usart: USART,
210210
pins: PINS,
211+
tx: Tx<USART>,
212+
rx: Rx<USART>,
211213
}
212214

213215
/// Serial receiver
@@ -372,7 +374,11 @@ macro_rules! hal {
372374
.cr1
373375
.modify(|_, w| w.ue().set_bit().re().set_bit().te().set_bit());
374376

375-
Serial { usart, pins }
377+
Serial {
378+
usart, pins,
379+
tx: Tx { _usart: PhantomData },
380+
rx: Rx { _usart: PhantomData },
381+
}
376382
}
377383

378384
/// Starts listening for an interrupt event
@@ -400,10 +406,28 @@ macro_rules! hal {
400406
///
401407
/// See [`Rx::check_for_error`].
402408
pub fn check_for_error() -> Result<(), Error> {
403-
let mut rx: Rx<pac::$USARTX> = Rx {
404-
_usart: PhantomData,
405-
};
406-
rx.check_for_error()
409+
// NOTE(unsafe): Only used for atomic access.
410+
let isr = unsafe { (*pac::$USARTX::ptr()).isr.read() };
411+
let icr = unsafe { &(*pac::$USARTX::ptr()).icr };
412+
413+
if isr.pe().bit_is_set() {
414+
icr.write(|w| w.pecf().clear());
415+
return Err(Error::Parity);
416+
}
417+
if isr.fe().bit_is_set() {
418+
icr.write(|w| w.fecf().clear());
419+
return Err(Error::Framing);
420+
}
421+
if isr.nf().bit_is_set() {
422+
icr.write(|w| w.ncf().clear());
423+
return Err(Error::Noise);
424+
}
425+
if isr.ore().bit_is_set() {
426+
icr.write(|w| w.orecf().clear());
427+
return Err(Error::Overrun);
428+
}
429+
430+
Ok(())
407431
}
408432

409433
/// Stops listening for an interrupt event
@@ -430,12 +454,8 @@ macro_rules! hal {
430454
/// Splits the `Serial` abstraction into a transmitter and a receiver half
431455
pub fn split(self) -> (Tx<pac::$USARTX>, Rx<pac::$USARTX>) {
432456
(
433-
Tx {
434-
_usart: PhantomData,
435-
},
436-
Rx {
437-
_usart: PhantomData,
438-
},
457+
self.tx,
458+
self.rx,
439459
)
440460
}
441461

@@ -449,10 +469,7 @@ macro_rules! hal {
449469
type Error = Error;
450470

451471
fn read(&mut self) -> nb::Result<u8, Error> {
452-
let mut rx: Rx<pac::$USARTX> = Rx {
453-
_usart: PhantomData,
454-
};
455-
rx.read()
472+
self.rx.read()
456473
}
457474
}
458475

@@ -480,17 +497,11 @@ macro_rules! hal {
480497
type Error = Error;
481498

482499
fn flush(&mut self) -> nb::Result<(), Error> {
483-
let mut tx: Tx<pac::$USARTX> = Tx {
484-
_usart: PhantomData,
485-
};
486-
tx.flush()
500+
self.tx.flush()
487501
}
488502

489503
fn write(&mut self, byte: u8) -> nb::Result<(), Error> {
490-
let mut tx: Tx<pac::$USARTX> = Tx {
491-
_usart: PhantomData,
492-
};
493-
tx.write(byte)
504+
self.tx.write(byte)
494505
}
495506
}
496507

@@ -579,28 +590,7 @@ macro_rules! hal {
579590
/// `Ok(())`, it should be possible to proceed with the next
580591
/// `read` call unimpeded.
581592
pub fn check_for_error(&mut self) -> Result<(), Error> {
582-
// NOTE(unsafe): Only used for atomic access.
583-
let isr = unsafe { (*pac::$USARTX::ptr()).isr.read() };
584-
let icr = unsafe { &(*pac::$USARTX::ptr()).icr };
585-
586-
if isr.pe().bit_is_set() {
587-
icr.write(|w| w.pecf().clear());
588-
return Err(Error::Parity);
589-
}
590-
if isr.fe().bit_is_set() {
591-
icr.write(|w| w.fecf().clear());
592-
return Err(Error::Framing);
593-
}
594-
if isr.nf().bit_is_set() {
595-
icr.write(|w| w.ncf().clear());
596-
return Err(Error::Noise);
597-
}
598-
if isr.ore().bit_is_set() {
599-
icr.write(|w| w.orecf().clear());
600-
return Err(Error::Overrun);
601-
}
602-
603-
Ok(())
593+
<Serial<pac::$USARTX, ()>>::check_for_error()
604594
}
605595

606596
/// Checks to see if the USART peripheral has detected an idle line and clears

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