@@ -324,8 +324,7 @@ macro_rules! adc_hal {
324
324
/// Software can use CkMode::SYNCDIV1 only if
325
325
/// hclk and sysclk are the same. (see reference manual 15.3.3)
326
326
fn clocks_welldefined( & self , clocks: Clocks ) -> bool {
327
- if ( self . ckmode == CkMode :: SYNCDIV1 )
328
- {
327
+ if ( self . ckmode == CkMode :: SYNCDIV1 ) {
329
328
clocks. hclk( ) . 0 == clocks. sysclk( ) . 0
330
329
} else {
331
330
true
@@ -348,7 +347,7 @@ macro_rules! adc_hal {
348
347
}
349
348
350
349
fn set_sequence_len( & mut self , len: u8 ) {
351
- debug_assert !( len <= 16 ) ;
350
+ assert !( len - 1 < 16 , "ADC sequence length must be in 1..=16" ) ;
352
351
self . rb. sqr1. modify( |_, w| w. l( ) . bits( len - 1 ) ) ;
353
352
}
354
353
@@ -362,7 +361,7 @@ macro_rules! adc_hal {
362
361
}
363
362
364
363
fn disable( & mut self ) {
365
- self . rb. cr. modify( |_, w| w. aden ( ) . clear_bit ( ) ) ;
364
+ self . rb. cr. modify( |_, w| w. addis ( ) . disable ( ) ) ;
366
365
}
367
366
368
367
/// Calibrate according to 15.3.8 in the Reference Manual
@@ -378,7 +377,7 @@ macro_rules! adc_hal {
378
377
. adcaldif( ) . single_ended( )
379
378
. adcal( ) . calibration( ) ) ;
380
379
381
- while ! self . rb. cr. read( ) . adcal( ) . is_complete ( ) { }
380
+ while self . rb. cr. read( ) . adcal( ) . is_calibration ( ) { }
382
381
}
383
382
384
383
fn wait_adc_clk_cycles( & self , cycles: u32 ) {
0 commit comments