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fix some errors from the review
1 parent 0c472c7 commit ff7a430

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src/adc.rs

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -324,8 +324,7 @@ macro_rules! adc_hal {
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/// Software can use CkMode::SYNCDIV1 only if
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/// hclk and sysclk are the same. (see reference manual 15.3.3)
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fn clocks_welldefined(&self, clocks: Clocks) -> bool {
327-
if (self.ckmode == CkMode::SYNCDIV1)
328-
{
327+
if (self.ckmode == CkMode::SYNCDIV1) {
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clocks.hclk().0 == clocks.sysclk().0
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} else {
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true
@@ -348,7 +347,7 @@ macro_rules! adc_hal {
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}
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fn set_sequence_len(&mut self, len: u8) {
351-
debug_assert!(len <= 16);
350+
assert!(len - 1 < 16, "ADC sequence length must be in 1..=16");
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self.rb.sqr1.modify(|_, w| w.l().bits(len - 1));
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}
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@@ -362,7 +361,7 @@ macro_rules! adc_hal {
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}
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fn disable(&mut self) {
365-
self.rb.cr.modify(|_, w| w.aden().clear_bit());
364+
self.rb.cr.modify(|_, w| w.addis().disable());
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}
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/// Calibrate according to 15.3.8 in the Reference Manual
@@ -378,7 +377,7 @@ macro_rules! adc_hal {
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.adcaldif().single_ended()
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.adcal() .calibration());
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381-
while !self.rb.cr.read().adcal().is_complete() {}
380+
while self.rb.cr.read().adcal().is_calibration() {}
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}
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384383
fn wait_adc_clk_cycles(&self, cycles: u32) {

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