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Commit 45cce7d

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AndreySmirnov81AndreySmirnov81
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rcc: access to Enable and Reset for owner only
1 parent 9d33a94 commit 45cce7d

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13 files changed

+37
-42
lines changed

13 files changed

+37
-42
lines changed

‎src/adc.rs

+3-3
Original file line numberDiff line numberDiff line change
@@ -271,15 +271,15 @@ macro_rules! adc_hal {
271271
}
272272

273273
fn reset(&mut self) {
274-
<$ADC>::reset();
274+
self.rb.reset();
275275
}
276276

277277
fn enable_clock(&mut self) {
278-
<$ADC>::enable();
278+
self.rb.enable();
279279
}
280280

281281
fn disable_clock(&mut self) {
282-
<$ADC>::disable();
282+
self.rb.disable();
283283
}
284284

285285
fn calibrate(&mut self) {

‎src/afio.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,8 @@ pub trait AfioExt {
1313

1414
impl AfioExt for AFIO {
1515
fn constrain(self) -> Parts {
16-
AFIO::enable();
17-
AFIO::reset();
16+
self.enable();
17+
self.reset();
1818

1919
Parts {
2020
evcr: EVCR { _0: () },

‎src/can.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -95,15 +95,15 @@ where
9595
/// prevent accidental shared usage.
9696
#[cfg(not(feature = "connectivity"))]
9797
pub fn new(can: Instance, _usb: pac::USB) -> Can<Instance> {
98-
Instance::enable();
98+
can.enable();
9999

100100
Can { _peripheral: can }
101101
}
102102

103103
/// Creates a CAN interaface.
104104
#[cfg(feature = "connectivity")]
105105
pub fn new(can: Instance) -> Can<Instance> {
106-
Instance::enable();
106+
can.enable();
107107

108108
Can { _peripheral: can }
109109
}

‎src/crc.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ pub trait CrcExt {
1212

1313
impl CrcExt for CRC {
1414
fn new(self) -> Crc {
15-
CRC::enable();
15+
self.enable();
1616

1717
Crc { crc: self }
1818
}

‎src/dma.rs

+1-1
Original file line numberDiff line numberDiff line change
@@ -447,7 +447,7 @@ macro_rules! dma {
447447
type Channels = Channels;
448448

449449
fn split(self) -> Channels {
450-
$DMAX::enable();
450+
self.enable();
451451

452452
// reset the DMA control registers (stops all on-going transfers)
453453
$(

‎src/gpio.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -366,8 +366,8 @@ macro_rules! gpio {
366366
type Parts = Parts;
367367

368368
fn split(self) -> Parts {
369-
$GPIOX::enable();
370-
$GPIOX::reset();
369+
self.enable();
370+
self.reset();
371371

372372
Parts {
373373
crl: Cr::<$port_id, false>(()),

‎src/i2c.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -166,8 +166,8 @@ where
166166
/// Configures the I2C peripheral to work in master mode
167167
fn configure<M: Into<Mode>>(i2c: I2C, pins: PINS, mode: M, clocks: Clocks) -> Self {
168168
let mode = mode.into();
169-
I2C::enable();
170-
I2C::reset();
169+
i2c.enable();
170+
i2c.reset();
171171

172172
let pclk1 = I2C::clock(&clocks);
173173

‎src/rcc.rs

+5-12
Original file line numberDiff line numberDiff line change
@@ -73,13 +73,6 @@ impl APB1 {
7373
}
7474
}
7575

76-
impl APB1 {
77-
/// Set power interface clock (PWREN) bit in RCC_APB1ENR
78-
pub fn set_pwren() {
79-
PWR::enable();
80-
}
81-
}
82-
8376
/// Advanced Peripheral Bus 2 (APB2) registers
8477
pub struct APB2 {
8578
_0: (),
@@ -308,8 +301,8 @@ impl BKP {
308301
/// Enables write access to the registers in the backup domain
309302
pub fn constrain(self, bkp: crate::pac::BKP, pwr: &mut PWR) -> BackupDomain {
310303
// Enable the backup interface by setting PWREN and BKPEN
311-
crate::pac::BKP::enable();
312-
crate::pac::PWR::enable();
304+
bkp.enable();
305+
pwr.enable();
313306

314307
// Enable access to the backup registers
315308
pwr.cr.modify(|_r, w| w.dbp().set_bit());
@@ -468,12 +461,12 @@ pub trait RccBus: crate::Sealed {
468461

469462
/// Enable/disable peripheral
470463
pub trait Enable: RccBus {
471-
fn enable();
472-
fn disable();
464+
fn enable(&self);
465+
fn disable(&self);
473466
}
474467
/// Reset peripheral
475468
pub trait Reset: RccBus {
476-
fn reset();
469+
fn reset(&self);
477470
}
478471

479472
#[derive(Clone, Copy, Debug, PartialEq)]

‎src/rcc/enable.rs

+5-5
Original file line numberDiff line numberDiff line change
@@ -11,14 +11,14 @@ macro_rules! bus {
1111
}
1212
impl Enable for crate::pac::$PER {
1313
#[inline(always)]
14-
fn enable() {
14+
fn enable(&self) {
1515
let rcc = unsafe { &(*RCC::ptr()) };
1616
unsafe {
1717
bb::set(Self::Bus::enr(rcc), $bit);
1818
}
1919
}
2020
#[inline(always)]
21-
fn disable() {
21+
fn disable(&self) {
2222
let rcc = unsafe { &(*RCC::ptr()) };
2323
unsafe {
2424
bb::clear(Self::Bus::enr(rcc), $bit);
@@ -27,7 +27,7 @@ macro_rules! bus {
2727
}
2828
impl Reset for crate::pac::$PER {
2929
#[inline(always)]
30-
fn reset() {
30+
fn reset(&self) {
3131
let rcc = unsafe { &(*RCC::ptr()) };
3232
unsafe {
3333
bb::set(Self::Bus::rstr(rcc), $bit);
@@ -49,14 +49,14 @@ macro_rules! ahb_bus {
4949
}
5050
impl Enable for crate::pac::$PER {
5151
#[inline(always)]
52-
fn enable() {
52+
fn enable(&self) {
5353
let rcc = unsafe { &(*RCC::ptr()) };
5454
unsafe {
5555
bb::set(Self::Bus::enr(rcc), $bit);
5656
}
5757
}
5858
#[inline(always)]
59-
fn disable() {
59+
fn disable(&self) {
6060
let rcc = unsafe { &(*RCC::ptr()) };
6161
unsafe {
6262
bb::clear(Self::Bus::enr(rcc), $bit);

‎src/serial.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -292,8 +292,8 @@ impl<USART: Instance, PINS> Serial<USART, PINS> {
292292
PINS: Pins<USART>,
293293
{
294294
// Enable and reset USART
295-
USART::enable();
296-
USART::reset();
295+
usart.enable();
296+
usart.reset();
297297

298298
PINS::remap(mapr);
299299

‎src/spi.rs

+4-4
Original file line numberDiff line numberDiff line change
@@ -468,8 +468,8 @@ where
468468
{
469469
fn configure(spi: SPI, pins: PINS, mode: Mode, freq: Hertz, clocks: Clocks) -> Self {
470470
// enable or reset SPI
471-
SPI::enable();
472-
SPI::reset();
471+
spi.enable();
472+
spi.reset();
473473

474474
// disable SS output
475475
spi.cr2.write(|w| w.ssoe().clear_bit());
@@ -539,8 +539,8 @@ where
539539
{
540540
fn configure(spi: SPI, pins: PINS, mode: Mode) -> Self {
541541
// enable or reset SPI
542-
SPI::enable();
543-
SPI::reset();
542+
spi.enable();
543+
spi.reset();
544544

545545
// disable SS output
546546
spi.cr2.write(|w| w.ssoe().clear_bit());

‎src/timer.rs

+4-4
Original file line numberDiff line numberDiff line change
@@ -637,8 +637,8 @@ impl<TIM: Instance> Timer<TIM> {
637637
/// Initialize timer
638638
pub fn new(tim: TIM, clocks: &Clocks) -> Self {
639639
// Enable and reset the timer peripheral
640-
TIM::enable();
641-
TIM::reset();
640+
tim.enable();
641+
tim.reset();
642642

643643
Self {
644644
clk: TIM::timer_clock(clocks),
@@ -710,8 +710,8 @@ impl<TIM: Instance, const FREQ: u32> FTimer<TIM, FREQ> {
710710
/// Initialize timer
711711
pub fn new(tim: TIM, clocks: &Clocks) -> Self {
712712
// Enable and reset the timer peripheral
713-
TIM::enable();
714-
TIM::reset();
713+
tim.enable();
714+
tim.reset();
715715

716716
let mut t = Self { tim };
717717
t.configure(clocks);

‎src/usb.rs

+4-2
Original file line numberDiff line numberDiff line change
@@ -28,10 +28,12 @@ unsafe impl UsbPeripheral for Peripheral {
2828
const EP_MEMORY_ACCESS_2X16: bool = false;
2929

3030
fn enable() {
31+
// TODO: use self.usb, after adding the &self parameter
32+
let usb = unsafe { crate::pac::Peripherals::steal().USB };
3133
// Enable USB peripheral
32-
USB::enable();
34+
usb.enable();
3335
// Reset USB peripheral
34-
USB::reset();
36+
usb.reset();
3537
}
3638

3739
fn startup_delay() {

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