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Merge pull request #179 from urdh/update-pac-crate-to-0.15
Update stm32f0 PAC crate to 0.15
2 parents b2e2e9d + 07f8382 commit 5f31f9e

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6 files changed

+60
-59
lines changed

6 files changed

+60
-59
lines changed

‎CHANGELOG.md

+1
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
1010
### Changed
1111

1212
- Updated the `cast` dependency from 0.2 to 0.3
13+
- Updated `stm32f0` peripheral access crate from 0.14 to 0.15
1314

1415
### Added
1516

‎Cargo.toml

+1-1
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ bare-metal = { version = "1.0.0" }
3434
cast = "0.3"
3535
cortex-m = "0.7"
3636
embedded-hal = { version = "0.2", features = ["unproven"] }
37-
stm32f0 = "0.14"
37+
stm32f0 = "0.15"
3838
nb = "1"
3939
void = { version = "1.0", default-features = false }
4040
stm32-usbd = { version = "0.6", optional = true }

‎src/adc.rs

+15-15
Original file line numberDiff line numberDiff line change
@@ -103,14 +103,14 @@ impl AdcSampleTime {
103103
impl From<AdcSampleTime> for SMP_A {
104104
fn from(val: AdcSampleTime) -> Self {
105105
match val {
106-
AdcSampleTime::T_1 => SMP_A::CYCLES1_5,
107-
AdcSampleTime::T_7 => SMP_A::CYCLES7_5,
108-
AdcSampleTime::T_13 => SMP_A::CYCLES13_5,
109-
AdcSampleTime::T_28 => SMP_A::CYCLES28_5,
110-
AdcSampleTime::T_41 => SMP_A::CYCLES41_5,
111-
AdcSampleTime::T_55 => SMP_A::CYCLES55_5,
112-
AdcSampleTime::T_71 => SMP_A::CYCLES71_5,
113-
AdcSampleTime::T_239 => SMP_A::CYCLES239_5,
106+
AdcSampleTime::T_1 => SMP_A::Cycles15,
107+
AdcSampleTime::T_7 => SMP_A::Cycles75,
108+
AdcSampleTime::T_13 => SMP_A::Cycles135,
109+
AdcSampleTime::T_28 => SMP_A::Cycles285,
110+
AdcSampleTime::T_41 => SMP_A::Cycles415,
111+
AdcSampleTime::T_55 => SMP_A::Cycles555,
112+
AdcSampleTime::T_71 => SMP_A::Cycles715,
113+
AdcSampleTime::T_239 => SMP_A::Cycles2395,
114114
}
115115
}
116116
}
@@ -148,9 +148,9 @@ impl AdcAlign {
148148
impl From<AdcAlign> for ALIGN_A {
149149
fn from(val: AdcAlign) -> Self {
150150
match val {
151-
AdcAlign::Left => ALIGN_A::LEFT,
152-
AdcAlign::Right => ALIGN_A::RIGHT,
153-
AdcAlign::LeftAsRM => ALIGN_A::LEFT,
151+
AdcAlign::Left => ALIGN_A::Left,
152+
AdcAlign::Right => ALIGN_A::Right,
153+
AdcAlign::LeftAsRM => ALIGN_A::Left,
154154
}
155155
}
156156
}
@@ -178,10 +178,10 @@ impl AdcPrecision {
178178
impl From<AdcPrecision> for RES_A {
179179
fn from(val: AdcPrecision) -> Self {
180180
match val {
181-
AdcPrecision::B_12 => RES_A::TWELVEBIT,
182-
AdcPrecision::B_10 => RES_A::TENBIT,
183-
AdcPrecision::B_8 => RES_A::EIGHTBIT,
184-
AdcPrecision::B_6 => RES_A::SIXBIT,
181+
AdcPrecision::B_12 => RES_A::TwelveBit,
182+
AdcPrecision::B_10 => RES_A::TenBit,
183+
AdcPrecision::B_8 => RES_A::EightBit,
184+
AdcPrecision::B_6 => RES_A::SixBit,
185185
}
186186
}
187187
}

‎src/pwm.rs

+32-32
Original file line numberDiff line numberDiff line change
@@ -206,7 +206,7 @@ macro_rules! pwm_4_channels {
206206

207207
//NOTE(unsafe) atomic read with no side effects
208208
fn get_duty(&self) -> u16 {
209-
unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 }
209+
unsafe { (*$TIMX::ptr()).ccr1().read().ccr().bits() as u16 }
210210
}
211211

212212
//NOTE(unsafe) atomic read with no side effects
@@ -216,7 +216,7 @@ macro_rules! pwm_4_channels {
216216

217217
//NOTE(unsafe) atomic write with no side effects
218218
fn set_duty(&mut self, duty: u16) {
219-
unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) }
219+
unsafe { (*$TIMX::ptr()).ccr1().write(|w| w.ccr().bits(duty.into())) }
220220
}
221221
}
222222

@@ -235,7 +235,7 @@ macro_rules! pwm_4_channels {
235235

236236
//NOTE(unsafe) atomic read with no side effects
237237
fn get_duty(&self) -> u16 {
238-
unsafe { (*$TIMX::ptr()).ccr2.read().ccr().bits() as u16 }
238+
unsafe { (*$TIMX::ptr()).ccr2().read().ccr().bits() as u16 }
239239
}
240240

241241
//NOTE(unsafe) atomic read with no side effects
@@ -245,7 +245,7 @@ macro_rules! pwm_4_channels {
245245

246246
//NOTE(unsafe) atomic write with no side effects
247247
fn set_duty(&mut self, duty: u16) {
248-
unsafe { (*$TIMX::ptr()).ccr2.write(|w| w.ccr().bits(duty.into())) }
248+
unsafe { (*$TIMX::ptr()).ccr2().write(|w| w.ccr().bits(duty.into())) }
249249
}
250250
}
251251

@@ -264,7 +264,7 @@ macro_rules! pwm_4_channels {
264264

265265
//NOTE(unsafe) atomic read with no side effects
266266
fn get_duty(&self) -> u16 {
267-
unsafe { (*$TIMX::ptr()).ccr3.read().ccr().bits() as u16 }
267+
unsafe { (*$TIMX::ptr()).ccr3().read().ccr().bits() as u16 }
268268
}
269269

270270
//NOTE(unsafe) atomic read with no side effects
@@ -274,7 +274,7 @@ macro_rules! pwm_4_channels {
274274

275275
//NOTE(unsafe) atomic write with no side effects
276276
fn set_duty(&mut self, duty: u16) {
277-
unsafe { (*$TIMX::ptr()).ccr3.write(|w| w.ccr().bits(duty.into())) }
277+
unsafe { (*$TIMX::ptr()).ccr3().write(|w| w.ccr().bits(duty.into())) }
278278
}
279279
}
280280

@@ -293,7 +293,7 @@ macro_rules! pwm_4_channels {
293293

294294
//NOTE(unsafe) atomic read with no side effects
295295
fn get_duty(&self) -> u16 {
296-
unsafe { (*$TIMX::ptr()).ccr4.read().ccr().bits() as u16 }
296+
unsafe { (*$TIMX::ptr()).ccr4().read().ccr().bits() as u16 }
297297
}
298298

299299
//NOTE(unsafe) atomic read with no side effects
@@ -303,7 +303,7 @@ macro_rules! pwm_4_channels {
303303

304304
//NOTE(unsafe) atomic write with no side effects
305305
fn set_duty(&mut self, duty: u16) {
306-
unsafe { (*$TIMX::ptr()).ccr4.write(|w| w.ccr().bits(duty.into())) }
306+
unsafe { (*$TIMX::ptr()).ccr4().write(|w| w.ccr().bits(duty.into())) }
307307
}
308308
}
309309
)+
@@ -395,7 +395,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
395395

396396
//NOTE(unsafe) atomic read with no side effects
397397
fn get_duty(&self) -> u16 {
398-
unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 }
398+
unsafe { (*$TIMX::ptr()).ccr1().read().ccr().bits() as u16 }
399399
}
400400

401401
//NOTE(unsafe) atomic read with no side effects
@@ -405,7 +405,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
405405

406406
//NOTE(unsafe) atomic write with no side effects
407407
fn set_duty(&mut self, duty: u16) {
408-
unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) }
408+
unsafe { (*$TIMX::ptr()).ccr1().write(|w| w.ccr().bits(duty.into())) }
409409
}
410410
}
411411

@@ -424,7 +424,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
424424

425425
//NOTE(unsafe) atomic read with no side effects
426426
fn get_duty(&self) -> u16 {
427-
unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 }
427+
unsafe { (*$TIMX::ptr()).ccr1().read().ccr().bits() as u16 }
428428
}
429429

430430
//NOTE(unsafe) atomic read with no side effects
@@ -434,7 +434,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
434434

435435
//NOTE(unsafe) atomic write with no side effects
436436
fn set_duty(&mut self, duty: u16) {
437-
unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) }
437+
unsafe { (*$TIMX::ptr()).ccr1().write(|w| w.ccr().bits(duty.into())) }
438438
}
439439
}
440440

@@ -453,7 +453,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
453453

454454
//NOTE(unsafe) atomic read with no side effects
455455
fn get_duty(&self) -> u16 {
456-
unsafe { (*$TIMX::ptr()).ccr2.read().ccr().bits() as u16 }
456+
unsafe { (*$TIMX::ptr()).ccr2().read().ccr().bits() as u16 }
457457
}
458458

459459
//NOTE(unsafe) atomic read with no side effects
@@ -463,7 +463,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
463463

464464
//NOTE(unsafe) atomic write with no side effects
465465
fn set_duty(&mut self, duty: u16) {
466-
unsafe { (*$TIMX::ptr()).ccr2.write(|w| w.ccr().bits(duty.into())) }
466+
unsafe { (*$TIMX::ptr()).ccr2().write(|w| w.ccr().bits(duty.into())) }
467467
}
468468
}
469469

@@ -482,7 +482,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
482482

483483
//NOTE(unsafe) atomic read with no side effects
484484
fn get_duty(&self) -> u16 {
485-
unsafe { (*$TIMX::ptr()).ccr2.read().ccr().bits() as u16 }
485+
unsafe { (*$TIMX::ptr()).ccr2().read().ccr().bits() as u16 }
486486
}
487487

488488
//NOTE(unsafe) atomic read with no side effects
@@ -492,7 +492,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
492492

493493
//NOTE(unsafe) atomic write with no side effects
494494
fn set_duty(&mut self, duty: u16) {
495-
unsafe { (*$TIMX::ptr()).ccr2.write(|w| w.ccr().bits(duty.into())) }
495+
unsafe { (*$TIMX::ptr()).ccr2().write(|w| w.ccr().bits(duty.into())) }
496496
}
497497
}
498498

@@ -511,7 +511,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
511511

512512
//NOTE(unsafe) atomic read with no side effects
513513
fn get_duty(&self) -> u16 {
514-
unsafe { (*$TIMX::ptr()).ccr3.read().ccr().bits() as u16 }
514+
unsafe { (*$TIMX::ptr()).ccr3().read().ccr().bits() as u16 }
515515
}
516516

517517
//NOTE(unsafe) atomic read with no side effects
@@ -521,7 +521,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
521521

522522
//NOTE(unsafe) atomic write with no side effects
523523
fn set_duty(&mut self, duty: u16) {
524-
unsafe { (*$TIMX::ptr()).ccr3.write(|w| w.ccr().bits(duty.into())) }
524+
unsafe { (*$TIMX::ptr()).ccr3().write(|w| w.ccr().bits(duty.into())) }
525525
}
526526
}
527527

@@ -540,7 +540,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
540540

541541
//NOTE(unsafe) atomic read with no side effects
542542
fn get_duty(&self) -> u16 {
543-
unsafe { (*$TIMX::ptr()).ccr3.read().ccr().bits() as u16 }
543+
unsafe { (*$TIMX::ptr()).ccr3().read().ccr().bits() as u16 }
544544
}
545545

546546
//NOTE(unsafe) atomic read with no side effects
@@ -550,7 +550,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
550550

551551
//NOTE(unsafe) atomic write with no side effects
552552
fn set_duty(&mut self, duty: u16) {
553-
unsafe { (*$TIMX::ptr()).ccr3.write(|w| w.ccr().bits(duty.into())) }
553+
unsafe { (*$TIMX::ptr()).ccr3().write(|w| w.ccr().bits(duty.into())) }
554554
}
555555
}
556556

@@ -569,7 +569,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
569569

570570
//NOTE(unsafe) atomic read with no side effects
571571
fn get_duty(&self) -> u16 {
572-
unsafe { (*$TIMX::ptr()).ccr4.read().ccr().bits() as u16 }
572+
unsafe { (*$TIMX::ptr()).ccr4().read().ccr().bits() as u16 }
573573
}
574574

575575
//NOTE(unsafe) atomic read with no side effects
@@ -579,7 +579,7 @@ macro_rules! pwm_4_channels_with_3_complementary_outputs {
579579

580580
//NOTE(unsafe) atomic write with no side effects
581581
fn set_duty(&mut self, duty: u16) {
582-
unsafe { (*$TIMX::ptr()).ccr4.write(|w| w.ccr().bits(duty.into())) }
582+
unsafe { (*$TIMX::ptr()).ccr4().write(|w| w.ccr().bits(duty.into())) }
583583
}
584584
}
585585
)+
@@ -666,7 +666,7 @@ macro_rules! pwm_2_channels {
666666

667667
//NOTE(unsafe) atomic read with no side effects
668668
fn get_duty(&self) -> u16 {
669-
unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 }
669+
unsafe { (*$TIMX::ptr()).ccr1().read().ccr().bits() as u16 }
670670
}
671671

672672
//NOTE(unsafe) atomic read with no side effects
@@ -676,7 +676,7 @@ macro_rules! pwm_2_channels {
676676

677677
//NOTE(unsafe) atomic write with no side effects
678678
fn set_duty(&mut self, duty: u16) {
679-
unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) }
679+
unsafe { (*$TIMX::ptr()).ccr1().write(|w| w.ccr().bits(duty.into())) }
680680
}
681681
}
682682

@@ -695,7 +695,7 @@ macro_rules! pwm_2_channels {
695695

696696
//NOTE(unsafe) atomic read with no side effects
697697
fn get_duty(&self) -> u16 {
698-
unsafe { (*$TIMX::ptr()).ccr2.read().ccr().bits() as u16 }
698+
unsafe { (*$TIMX::ptr()).ccr2().read().ccr().bits() as u16 }
699699
}
700700

701701
//NOTE(unsafe) atomic read with no side effects
@@ -705,7 +705,7 @@ macro_rules! pwm_2_channels {
705705

706706
//NOTE(unsafe) atomic write with no side effects
707707
fn set_duty(&mut self, duty: u16) {
708-
unsafe { (*$TIMX::ptr()).ccr2.write(|w| w.ccr().bits(duty.into())) }
708+
unsafe { (*$TIMX::ptr()).ccr2().write(|w| w.ccr().bits(duty.into())) }
709709
}
710710
}
711711
)+
@@ -775,7 +775,7 @@ macro_rules! pwm_1_channel {
775775

776776
//NOTE(unsafe) atomic read with no side effects
777777
fn get_duty(&self) -> u16 {
778-
unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 }
778+
unsafe { (*$TIMX::ptr()).ccr1().read().ccr().bits() as u16 }
779779
}
780780

781781
//NOTE(unsafe) atomic read with no side effects
@@ -785,7 +785,7 @@ macro_rules! pwm_1_channel {
785785

786786
//NOTE(unsafe) atomic write with no side effects
787787
fn set_duty(&mut self, duty: u16) {
788-
unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) }
788+
unsafe { (*$TIMX::ptr()).ccr1().write(|w| w.ccr().bits(duty.into())) }
789789
}
790790
}
791791
)+
@@ -858,7 +858,7 @@ macro_rules! pwm_1_channel_with_complementary_outputs {
858858

859859
//NOTE(unsafe) atomic read with no side effects
860860
fn get_duty(&self) -> u16 {
861-
unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 }
861+
unsafe { (*$TIMX::ptr()).ccr1().read().ccr().bits() as u16 }
862862
}
863863

864864
//NOTE(unsafe) atomic read with no side effects
@@ -868,7 +868,7 @@ macro_rules! pwm_1_channel_with_complementary_outputs {
868868

869869
//NOTE(unsafe) atomic write with no side effects
870870
fn set_duty(&mut self, duty: u16) {
871-
unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) }
871+
unsafe { (*$TIMX::ptr()).ccr1().write(|w| w.ccr().bits(duty.into())) }
872872
}
873873
}
874874

@@ -887,7 +887,7 @@ macro_rules! pwm_1_channel_with_complementary_outputs {
887887

888888
//NOTE(unsafe) atomic read with no side effects
889889
fn get_duty(&self) -> u16 {
890-
unsafe { (*$TIMX::ptr()).ccr1.read().ccr().bits() as u16 }
890+
unsafe { (*$TIMX::ptr()).ccr1().read().ccr().bits() as u16 }
891891
}
892892

893893
//NOTE(unsafe) atomic read with no side effects
@@ -897,7 +897,7 @@ macro_rules! pwm_1_channel_with_complementary_outputs {
897897

898898
//NOTE(unsafe) atomic write with no side effects
899899
fn set_duty(&mut self, duty: u16) {
900-
unsafe { (*$TIMX::ptr()).ccr1.write(|w| w.ccr().bits(duty.into())) }
900+
unsafe { (*$TIMX::ptr()).ccr1().write(|w| w.ccr().bits(duty.into())) }
901901
}
902902
}
903903
)+

‎src/rcc.rs

+5-5
Original file line numberDiff line numberDiff line change
@@ -154,8 +154,8 @@ mod inner {
154154

155155
pub(super) fn get_sww(c_src: &SysClkSource) -> SW_A {
156156
match c_src {
157-
SysClkSource::HSI => SW_A::HSI,
158-
SysClkSource::HSE(_, _) => SW_A::HSE,
157+
SysClkSource::HSI => SW_A::Hsi,
158+
SysClkSource::HSE(_, _) => SW_A::Hse,
159159
}
160160
}
161161
}
@@ -316,7 +316,7 @@ mod inner {
316316

317317
pub(super) fn get_sww(c_src: &SysClkSource) -> SW_A {
318318
match c_src {
319-
SysClkSource::HSI => SW_A::HSI,
319+
SysClkSource::HSI => SW_A::Hsi,
320320
#[cfg(any(
321321
feature = "stm32f042",
322322
feature = "stm32f048",
@@ -326,8 +326,8 @@ mod inner {
326326
feature = "stm32f091",
327327
feature = "stm32f098",
328328
))]
329-
SysClkSource::HSI48 => SW_A::HSI48,
330-
SysClkSource::HSE(_, _) => SW_A::HSE,
329+
SysClkSource::HSI48 => SW_A::Hsi48,
330+
SysClkSource::HSE(_, _) => SW_A::Hse,
331331
}
332332
}
333333
}

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