2020import array
2121from uctypes import addressof
2222from ulab import numpy as np
23- from ..utils import colors
24- from ..utils import memory
23+ from ..utils import colors as rv_colors
24+ from ..utils import memory as rv_memory
2525
2626class DVI_RP2_HSTX ():
2727 """
@@ -200,7 +200,7 @@ def color_mode_default(self):
200200 """
201201 Returns the default color mode for the display.
202202 """
203- return colors .COLOR_MODE_BGR565
203+ return rv_colors .COLOR_MODE_BGR565
204204
205205 def color_mode_is_supported (self , color_mode ):
206206 """
@@ -211,7 +211,7 @@ def color_mode_is_supported(self, color_mode):
211211 Returns:
212212 bool: True if the color mode is supported, otherwise False
213213 """
214- return color_mode == colors .COLOR_MODE_BGR565
214+ return color_mode == rv_colors .COLOR_MODE_BGR565
215215
216216 def _configure_hstx (self ):
217217 """
@@ -261,7 +261,7 @@ def _configure_hstx(self):
261261 # With BGR color modes, B is the least significant bits, and R is the
262262 # most significant bits. This means the bits are in RGB order, which is
263263 # opposite of what one might expect.
264- if self ._color_mode == colors .COLOR_MODE_BGR233 :
264+ if self ._color_mode == rv_colors .COLOR_MODE_BGR233 :
265265 # BGR233 (00000000 00000000 00000000 RRRGGGBB)
266266 expand_tmds = self ._hstx .pack_expand_tmds (
267267 l2_nbits = 2 , # 3 bits (red)
@@ -271,7 +271,7 @@ def _configure_hstx(self):
271271 l0_nbits = 1 , # 2 bits (blue)
272272 l0_rot = 26 , # Shift right 26 bits to align MSB (left 6 bits)
273273 )
274- elif self ._color_mode == colors .COLOR_MODE_GRAY8 :
274+ elif self ._color_mode == rv_colors .COLOR_MODE_GRAY8 :
275275 # GRAY8 (00000000 00000000 00000000 GGGGGGGG)
276276 expand_tmds = self ._hstx .pack_expand_tmds (
277277 l2_nbits = 7 , # 8 bits (red)
@@ -281,7 +281,7 @@ def _configure_hstx(self):
281281 l0_nbits = 7 , # 8 bits (blue)
282282 l0_rot = 0 , # Shift right 0 bits to align MSB
283283 )
284- elif self ._color_mode == colors .COLOR_MODE_BGR565 :
284+ elif self ._color_mode == rv_colors .COLOR_MODE_BGR565 :
285285 # BGR565 (00000000 00000000 RRRRRGGG GGGBBBBB)
286286 expand_tmds = self ._hstx .pack_expand_tmds (
287287 l2_nbits = 4 , # 5 bits (red)
@@ -291,7 +291,7 @@ def _configure_hstx(self):
291291 l0_nbits = 4 , # 5 bits (blue)
292292 l0_rot = 29 , # Shift right 29 bits to align MSB (left 3 bits)
293293 )
294- elif self ._color_mode == colors .COLOR_MODE_BGRA8888 :
294+ elif self ._color_mode == rv_colors .COLOR_MODE_BGRA8888 :
295295 # BGRA8888 (AAAAAAAA RRRRRRRR GGGGGGGG BBBBBBBB) alpha is ignored
296296 expand_tmds = self ._hstx .pack_expand_tmds (
297297 l2_nbits = 7 , # 8 bits (red)
@@ -526,7 +526,7 @@ def _configure_dmas(self):
526526 self ._dma_executer = rp2 .DMA ()
527527
528528 # Check if the display buffer is in PSRAM.
529- self ._buffer_is_in_psram = memory .is_in_external_ram (self ._buffer )
529+ self ._buffer_is_in_psram = rv_memory .is_in_external_ram (self ._buffer )
530530
531531 # If the buffer is in PSRAM, create the streamer DMA channel and row
532532 # buffer in SRAM.
@@ -544,7 +544,7 @@ def _configure_dmas(self):
544544 # BGR233 or GRAY8). Larger color modes (2 or 4 bytes per pixel) can
545545 # only be used with scaling.
546546 hstx_pixels_per_second = machine .freq () / 5
547- psram_bytes_per_second = memory .external_ram_max_bytes_per_second ()
547+ psram_bytes_per_second = rv_memory .external_ram_max_bytes_per_second ()
548548 psram_pixels_per_second = psram_bytes_per_second * self ._width_scale / self ._bytes_per_pixel
549549 if psram_pixels_per_second < hstx_pixels_per_second :
550550 raise ValueError ("PSRAM transfer speed too low for specified resolution and color mode" )
@@ -555,7 +555,7 @@ def _configure_dmas(self):
555555
556556 # Verify row buffer is in SRAM. If not, we'll still have the same
557557 # latency problem.
558- if memory .is_in_external_ram (self ._row_buffer ):
558+ if rv_memory .is_in_external_ram (self ._row_buffer ):
559559 raise MemoryError ("not enough space in SRAM for row buffer" )
560560
561561 # We'll use a DMA to trigger the XIP stream. However the RP2350's
@@ -725,7 +725,7 @@ def _create_control_blocks(self):
725725
726726 # The control block array must be in SRAM, otherwise we run into the
727727 # same latency problem with DMA transfers from PSRAM.
728- if memory .is_in_external_ram (self ._control_blocks ):
728+ if rv_memory .is_in_external_ram (self ._control_blocks ):
729729 raise MemoryError ("not enough space in SRAM for control block array" )
730730
731731 # Create the HSTX command sequences so the control blocks can reference
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